JPH1173245A - Data storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To operate the writing and reading operation of a flash memory 36 by obtaining a power from a data input edge RXD and a data request input edge CTS of a serial interface RS232C, and driving a processing circuit. SOLUTION: An input signal having waveform changing across +10 V corresponding to a logic '1' and -10 V corresponding to a logic '0' is applied to signal input lines 8 and 9, and first and second capacitors C1 and C2 are changed through diodes D1, D2: D3, D4. The charge of the second capacitor C2 is polarity inverted by a polarity converting circuit 24, and stored in a third capacitor C3. The output voltages of the first and third capacitors C1 and C3 are voltage converted by a step-down type chopper system switching regulator, and applied to a processing circuit 31. Thus, the writing and reading operation of a flash memory 36 is controlled. Therefore, an outside power source can be unnecessitated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a data storage device used by connecting to a serial interface used to connect a computer or the like.

[0002]

2. Description of the Related Art Conventionally, in order to store data from a serial interface, a cable is used, a signal source is connected to a computer, and data is stored and stored in a memory provided in the computer. . In this prior art, a computer power supply is required, and if the power supply is configured to be rechargeable, it cannot be used for a long time. Further, in the prior art in which the data itself is stored in a semiconductor memory such as a random access memory, a power supply for the memory is required, so that data cannot be stored for a long time.

[0003]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a data storage device which does not require an external power supply and can store and store transmitted input data for a long period of time.

[0004]

According to the present invention, a diode D1 connected to a signal input line to which an input signal is supplied is provided.
D3, capacitors C1 and C2 charged by current flowing through the diodes D1 and D3, a memory for storing an input signal from a signal input line, a processing circuit for storing the input signal in the memory, and capacitors C1 and C2.
And a power supply circuit for energizing the processing circuit by the output of the data storage device.

According to the present invention, input signals such as data are supplied to the capacitors C1 and C3 via the diodes D1 and D3.
2 and the capacitors C1 and C2 are charged,
Utilizing the electric charge stored in the capacitor, power is supplied to a processing circuit that controls a store operation of the memory by a power supply circuit. Therefore, when an input signal is applied to the signal input line, power is supplied to the processing circuit and other components that consume power, and thus input signals such as data to the memory are stored and the stored state is maintained. Will be.

The capacitance of the capacitors C1 and C2 is selected so that the waveform of the input signal on the signal input line is not likely to be deformed, and may be, for example, 470 μF.

Further, according to the present invention, the input signal has a waveform that changes over a positive polarity and a negative polarity with respect to a reference potential, and the diodes D1 and D3 are connected to a signal input line with a pair of mutually opposite polarities. Diode D
1 and D3, wherein the capacitors C1 and C2 are connected between a first capacitor C1 connected between the output of one diode D1 and the reference potential and a capacitor connected between the output of the other diode D3 and the reference potential. The power supply circuit comprises a third capacitor C3 and a second capacitor C2.
A polarity conversion circuit for inverting the polarity of the output of the capacitor C2 and supplying the output of the second capacitor C2 to the third capacitor C3 for charging.

According to the present invention, the input signal has a waveform that varies positively and negatively with respect to a reference potential, for example, the ground potential, for example, +1 corresponding to logic "1".
0 V and −10 V corresponding to logic “0”. The first capacitor stores a charge of one polarity, for example, positive, and the second capacitor stores a charge of another polarity, for example, negative. The charge is stored, and the charge of the second capacitor C2 is inverted in polarity by the polarity conversion circuit and is stored in the third capacitor C3. Thus, power is supplied to the processing circuit by the outputs of the first and third capacitors C1 and C3. Therefore, power for driving the processing circuit can be obtained by using both positive and negative voltages with respect to the reference potential of the input signal.

Further, according to the present invention, the polarity conversion circuit comprises third and fourth diodes D5 and D6 connected in series between the output of the first capacitor C1 and a reference potential, and a second capacitor C2. The first switching element TR1 having one terminal connected to the output of the first switching element TR1, the other terminal of the first switching element TR1 opposite to the second capacitor C2 has one terminal connected thereto, and the other terminal connected to the reference potential. And an oscillating circuit that performs on / off control such that one of the first and second switching elements TR1 and TR2 is turned off when one is turned on and the other is turned off when the other is turned on. And one terminal of the third capacitor C3 is connected to the third and fourth diodes D
5, the other terminal of the third capacitor C3 is connected to a connection point between the other terminal of the first switching element TR1 and the one terminal of the second switching element TR2. , And is powered by the outputs of the first and third capacitors C1 and C3.

According to the present invention, the on / off control of the first and second switching elements TR1 and TR2 is performed by the output of the oscillation circuit, and the first switching element TR1 conducts, thereby discharging the electric charge of the second capacitor C2. Moving to the third capacitor C3, the second switching element TR2 is cut off at this time, and then the second transistor TR2 is turned on and the first switching element TR1 is cut off, so that the output of the third capacitor C3 is derived. Will be done. In this manner, the polarity of the charge of the second capacitor C2 can be inverted and supplied from the third capacitor C3 for driving components such as a processing circuit.

Further, according to the present invention, a step-down type chopper type switching regulator is interposed between the output of the first and third capacitors C1 and C3 and the processing circuit, and the step-down type chopper type switching regulator comprises: A transistor TR3 and (b) an inductance element L1 connected to the switching transistor TR3
(C) a capacitor C5 to which the output of the inductance element L1 is applied; and (d) a duty ratio of a control signal to be applied to the control terminal of the switching transistor TR3 in response to the output voltage of the inductance element L1 to change the output voltage. When the output voltage is lower than a predetermined reference voltage, the duty ratio is changed so that the ratio of the conduction period of the switching transistor TR3 is increased. When the output voltage is higher than the predetermined reference voltage, the ratio of the conduction period of the switching transistor TR3 is changed. And a control circuit for changing the duty so as to shorten the duty.

According to the present invention, the advantages of the so-called chopper type high efficiency are exhibited, and the first and third capacitors C and C are used.
1 and C3 can be converted.

The present invention also provides a step-down chopper switching regulator, wherein the output voltage is a voltage dividing resistor R1,
The voltage is divided by a voltage dividing circuit composed of R2 and input to the control circuit,
A power-on switching element TR4 is connected in series with the voltage dividing circuit, has a time constant longer than the rise time of the processing circuit when the voltage is turned on, and includes first and third capacitors C1 and C3.
And a time constant circuit for delaying the output of the power supply switching element TR4 from the cutoff state to the conduction state by delaying the output of the power supply switching element TR4.

In the step-down chopper switching regulator, the output voltage is always lower than the input voltage by using the inductance element L1. That is, the input voltage cannot be lower than the output voltage. Even if the input voltage exceeds the output voltage, if there is no margin, the load current increases and the current increase increases the voltage drop due to the internal resistance of the signal source through the signal input line, causing a vicious cycle. There is a possibility that the regulator cannot be started.

Therefore, according to the present invention, a voltage dividing circuit 38 and a time constant circuit 43 are additionally provided in order to reduce the inrush current at the time of starting. At the time of startup, since the capacitor C4 included in the time constant circuit is not charged, the power-on switching element TR4 is in the cut-off state. Therefore, the output voltage is directly supplied to the control circuit that changes the duty ratio of the switching regulator, and has the same value as the reference voltage and a low value. Therefore, even if the input voltage is a low value, the present switching regulator can be started.

The capacitor C provided in the time constant circuit
When 4 is charged by the resistor R3, the power-on switching element TR4 is turned on. Therefore, the output voltage of the control circuit is increased by the operation of the voltage dividing circuit.
Thereby, a desired DC voltage can be obtained from the inductance element L1.

The time constant of the time constant circuit is selected to be longer than the rise time when the processing circuit is turned on, that is, the time from when power is supplied to the processing circuit to when the processing circuit starts normal operation. The time constant is chosen to be longer than the rise time. Therefore, the switching regulator can be started stably.

According to the present invention, a signal output switching element SW1 or SW2 is provided on a signal output line for outputting an output signal from a processing circuit, and the output signal output from the processing circuit to the signal output line is based on a reference voltage. It has a waveform that changes over the positive polarity and the negative polarity, and the processing circuit keeps the signal output switching elements SW1 and SW2 shut off except when the output signal is derived.

According to the present invention, the output signal output from the processing circuit to the signal output line has a waveform that varies between positive and negative with respect to the reference potential, for example, the ground potential. For example, when the voltage changes between +10 V corresponding to logic "1" and -10 V corresponding to logic "0", for example, and the output signal is not derived, the signal output line is set to +10 V or -10 V, for example. Is kept. As a result, power is wasted when the load resistor is connected to the output signal line.

In order to solve this problem, according to the present invention, a signal output switching element SW1,
When SW2 is interposed and the output signal is not derived, these signal output switching elements SW1 and SW2 are kept off. As a result, there is no possibility that power is wasted in a state where the output signal is not derived.

In the present invention, the electric power by the signal such as data from the signal input line is transferred to the capacitors C1, C2 and C3.
It is important to have a configuration for storing and powering the processing circuit, thus preventing such wasted power consumption.

The present invention controls the operation of a memory for storing data. Therefore, in the memory, one of writing and reading is performed, and both writing and reading are not performed simultaneously. Therefore, when the signal output lines are the data output TXD and the data request output RTS as described later, the signal output switching elements SW1 and SW2 of these two signal output lines do not conduct at the same time. Can be prevented from flowing, and thereby the operations of the processing circuit and the memory can be stably performed.

According to the present invention, the memory is a flash memory, and all the bits of the memory area are changed while changing the address of each bit in order to erase the stored contents.
On the other hand, an erasing operation for writing the logical value and then removing the charge of the floating gate is sequentially performed. This erasing operation step is stored in a sequence counter built in the memory, and is executed to execute the erasing operation of the memory. The required current consumption changes as the erase operation steps progress,
The erase operation can be interrupted. At the time of resumption, the erase operation step is continuously performed according to the stored contents of the sequence counter, and the processing circuit performs the erase time w1 and the standby time during the execution of the erase operation step with small current consumption. It is characterized in that the duty ratio w1 / (w1 + w2) with respect to w2 is selected to be large, and the duty ratio w3 / (w3 + w4) is selected to be small during execution of the erasing operation step which consumes a large current.

According to the present invention, in the flash memory,
When erasing the stored contents of the memory area, when removing the charge of the floating gate, for example, it is performed in blocks of several kilobytes, so that a large current flows,
There is a possibility that the outputs of the first to third capacitors C1, C2, C3 become insufficient. In order to solve this problem, in the present invention, the flash memory is erased in a time-division manner.

Further, according to the present invention, the change of the current consumption with the lapse of time in each operation step during the erasing operation of the flash memory is known in advance, and therefore, for example, according to the progress of the erasing step, With the lapse of time of the erase operation, current consumption is predicted. When the current consumption is small, the duty ratio is increased to speed up the progress of the erase operation. In the period during which the erasing step with a large current consumption is performed, the duty ratio is reduced, and therefore the time interval between the intermittent erasing steps is increased, whereby the first to third capacitors C1
The charging time is extended so as to increase the charge stored in C3.

As described above, the first to first signals flowing to the signal input line are
The average load current by charging the third capacitors C1 to C3 can be made as constant as possible. Therefore, the function of the power supply circuit of the present invention can provide a function as a load resistance of an original input signal.

The present invention also provides a connector detachably connected to a signal input line and a signal output line, the connector being fixed, diodes D1 and D3, and capacitors C1 and C2.
A housing containing components including a memory, a processing circuit, and a power supply circuit; a liquid crystal display provided in the housing to display processing contents of the processing circuit; and a liquid crystal display provided in the housing to control the operation of the processing circuit. Input means for inputting an upper part to be controlled.

According to the present invention, the connector is fixed to and integrated with the housing, so that the cable can be eliminated. This eliminates the need to consider the installation location of the data storage device of the present invention, and eliminates the problem of installation location. In addition, the effect of the present invention that a power supply is unnecessary can be further effectively exhibited.

[0029]

FIG. 1 is an electric circuit diagram showing the entire configuration of an embodiment of the present invention. The data storage device 1 of the present invention is connected to a processing unit 2 such as a computer by a detachable connector 3. Connector 3
Is composed of a connector unit 5 integrally fixed to a housing 4 of the data processing device 1 and a connector unit 7 integrally fixed to a housing 6 of the arithmetic processing device 2, and the data storage device 1 and the arithmetic processing device 2 is, for example, EIA / TI
A-232-E standard serial interface RS232
Connected by C.

In the data storage device 1, the signal input line 8
Is for the data input RXD and the signal input line 9 is for the data request input CTS. Further, the signal output line 10 has a data output terminal TXD
The signal output line 11 is for a data request output terminal RTS. The data request includes a function of synchronizing whether any one of the data storage device 1 and the arithmetic processing device 2 receives the current data.

The connector 3 leads the data output terminal TXD from the signal output line 12 of the processing unit 2 to the signal input line 8 for the data input terminal RXD in the data storage device 1. In addition, the data request output terminal RTS from the arithmetic processing unit 2 is connected to the signal output line 1 of the data request input terminal CTS of the data storage device 1.
3 is derived. The data output terminal TXD of the data storage device 1 is supplied from the signal output line 10 to the signal input line 14 as the data input terminal RXD of the arithmetic processing device 2. Data request output terminal RTS from data storage device 1
Is supplied from the signal output line 11 to the signal input line 15 as a data request input terminal CTS of the arithmetic processing unit 2.

FIG. 2 is a waveform diagram for explaining signal levels of terminals RXD, CTS, TXD and RTS on lines 8 to 15 shown in FIG. These terminals RXD,
CTS, TXD and RTS are +10 V corresponding to logic "1" which is positive with respect to a reference potential which is a ground level.
And -10 V corresponding to logic "0" which is negative polarity, and takes values of only these voltages +10 V and -10 V.

In the arithmetic processing unit 2, a signal from a signal source passes through buffers 16 and 17 and internal resistors 18 and 19, and from signal output lines 12 and 13 to a data storage device 1.
Are applied to the signal input lines 8, 9 via the data input terminal RXD and the data request input terminal CTS. This signal input line 8 is connected to one terminal of the first and second capacitors C1 and C2 via the diodes D1 and D3. The other terminals of the first and second capacitors C1 and C2 are set to the ground potential, which is the reference potential. Another signal input line 9 is similarly connected to the one terminal of the first and second capacitors C1 and C2 via diodes D2 and D4. The diodes D1, D2 and the diodes D3, D4 are connected in the reverse direction, and
The line 21 of the one terminal of the capacitor C1 has a positive polarity, and the line 22 of the one terminal of the second capacitor C2 has a positive polarity.
Is a negative polarity.

The power supply circuit 23 includes a third capacitor C3 and a voltage polarity conversion circuit 24. Voltage polarity conversion circuit 24
Functions to invert the polarity of the charged charge in the second capacitor C2 and accumulate it in the third capacitor C3.

In the voltage polarity conversion circuit 24, a transistor TR1 as a first switching element is interposed between the one terminal of the second capacitor C2 and the line 25 of the third capacitor C3. A transistor TR2 as a second switching element is interposed between the line 25 and the ground potential. The other terminal of the third capacitor C3 is connected at a connection point 26 to the anode of the diode D5 and the cathode of the diode D6. The cathode of diode D5 is connected to line 21. The anode of the diode D6 is grounded.

The conductivity types of transistors TR1 and TR2 are different from each other.
The transistor TR2 may be a P-type FET (field-effect transistor). Transistor T
R1 may be an NPN bipolar transistor, and transistor TR2 may be a PNP bipolar transistor. A control signal from the oscillation circuit 27 is commonly supplied to the control terminals that are the gates or bases of the transistors TR1 and TR2. Thereby, one transistor TR
1 repeats the on / off operation as shown in FIG. 3A, and the other transistor TR2
As shown in (2), an on / off operation is performed. When one transistor TR1 is on, the other transistor TR2 is off, and when one transistor TR1 is off, the other transistor TR2 is off. Conducted. The output frequency of the oscillation circuit 27 is, for example, 100
kHz and has a period shorter than the pulse width of the input signal on lines 8 and 9, for example at 9600 baud rate.

In operation, the line 22 of the second capacitor C2
Has a negative value. When the transistor TR1 conducts at times t1 to t2 in FIG. 3A, the electric charge of the second capacitor C2 is changed to the third capacitor C3.
And the line 25 becomes negative. Next time t2
At t3, as shown in FIG.
R2 conducts and line 25 is at ground potential. Therefore, the connection point 26 has a positive polarity with respect to the ground potential. Thus, the output of the first capacitor C1 and the output of the third capacitor C3 are supplied from a line 28 to a step-down chopper type switching regulator 29. From a line 30, power having a voltage of a predetermined voltage + 3V with respect to the ground potential is obtained.
It is provided to the processing circuit 31. The processing circuit 31 is realized by a microcomputer or the like. Power from line 30 is also provided to oscillating circuit 27. Further, the power from the line 30 is supplied to other components included in the data storage device 1.

Capacitors C1, C2 and C3 have a relatively large capacitance of, for example, 470 μF.
Therefore, each input signal from the signal input lines 8 and 9 is not distorted, and passes through the buffers Q5 and Q6 and is transmitted and received by the transmission / reception interface circuit UART (Universal Ansynchronous Resonance)
receive Transmit 32). The output of the transmission / reception interface circuit UART32 is connected to the processing circuit 31 via a line 33. Transmission / reception interface circuit U
The ART 32 is an interface that performs transmission and reception asynchronously.

The processing circuit 31 is connected to a liquid crystal display means 34, which displays the contents of arithmetic processing by the processing circuit 31, and also displays the contents of data received and transmitted. Input means 35 operated by an operator through key input or the like is connected to the processing circuit 31 and can control the operation of the processing circuit 31. Further, a flash memory 36, which is a non-volatile memory, is connected to the processing circuit 31, and the data input signal RXD
Can be stored, further information can be stored, and the stored contents can be read.

The first to third capacitors C1 to C3 accumulate the charges of the input signals from the signal input lines 8 and 9 and control the power consumption in the data storage device 1 to be kept substantially constant. Input lines 8, 9
This is equivalent to a configuration in which a load resistance having a predetermined constant resistance value is connected between the power supply and the ground potential. Thus, the input signals of the signal input lines 8 and 9 can be received without distortion. If such a load resistor is connected to the signal input lines 8 and 9, the energy of the input signal is converted into heat and consumed.
In the present invention, the energy of the input signal is used as power for operating the data storage device 1.

FIG. 4 is an electric circuit diagram showing a specific configuration of the step-down type chopper type switching regulator 29. Line 28 has a PNP type bipolar transistor T
R3 is connected, and an inductance element L1, which is a coil, is connected in series via a line 37, and its output is output to a line 30. A diode D6 is connected between the line 37 and the ground potential. On line 30,
A smoothing capacitor C5 is connected between the capacitor and the ground potential.
The line 30 is grounded via a voltage dividing circuit 38 composed of voltage dividing resistors R1 and R2, and further via an NPN transistor TR4. The voltage V1 at the connection point 39 between the voltage dividing resistors R1 and R2 is supplied to one input of a comparison circuit 40, and the other input of the comparison circuit 40 is supplied with a reference voltage Vr from a reference voltage source 41. The comparison circuit 40 supplies the control circuit 42 with a voltage representing the difference (= V1−Vr) between the connection point 39 and the reference voltage.

The control circuit 42 has a base, which is a control terminal of the transistor TR3, provided with a PWM whose duty ratio changes.
(Pulse width modulated) control signal. As a result, the switching of the transistor TR3 is controlled such that the voltage V1 at the connection point 39 becomes equal to the reference voltage Vr. For example, when the voltage V1 at the connection point 39 increases, the control signal from the control circuit 42 changes so that the ratio of the period during which the transistor TR3 conducts decreases, and the connection point 3
When the voltage V1 of No. 9 becomes lower than the reference voltage Vr, the switching of the transistor TR3 is controlled so that the ratio of the period during which the transistor TR3 is conductive increases.

The input voltage from the line 28 of the step-down chopper type switching regulator 29 cannot be lower than the output voltage from the line 30. The current derived from the line 30 becomes a large inrush current at the time of start-up. Therefore, a voltage drop occurs in the internal resistors 12 and 13 in the arithmetic processing device 2 serving as a signal source, and the input voltage on the line 28 of the switching regulator 29 becomes There is a possibility that the voltage becomes lower than the operating voltage. Therefore, the switching regulator 29 cannot be started as it is. That is, the input voltage on line 28 is
Even if the output voltage exceeds the output voltage of the line 30, if there is no margin, the load current increases and the voltage increase in the internal resistances 12 and 13 on the signal source side increases due to the increase in current. May not be possible.

In order to solve this problem, in the present invention, the switching element TR4 and the time constant circuit 43 are provided to reduce the inrush current at the time of starting. A time constant circuit 43 is connected to the line 28. This time constant circuit 43
The output from the line 44 is supplied to a base which is a control terminal of the transistor TR4 which is a switching element. The time constant circuit 43 includes a resistor R connected to the line 28.
3 and a capacitor C4 connected between the ground potential and a resistor R4 in parallel with the capacitor C4.

The voltage on the line 28 is shown in FIG. 5 (1). At time t11 when the power is turned on, the capacitor C4 of the time constant circuit 43 is not charged, and the output voltage of this capacitor C4 is as shown in FIG. ). The ON / OFF state of the transistor TR4 is as shown in FIG. At times t11 to t12 when the transistor TR4 is lower than the discrimination level at which the transistor TR4 conducts, the transistor TR4 is turned off. Therefore, the output voltage of the line 30 has the same value as that of the connection point 39, and this output voltage has the same value as the reference voltage by the operation of the control circuit 42. Therefore, even if the input voltage of the line 28 has a low value, the present switching regulator 29 can be started.

When the capacitor C4 of the time constant circuit 43 is charged by the current flowing through the resistor R3, the time t
12, the transistor TR4 conducts and the voltage dividing resistor R
The end opposite to the second connection point 39 is grounded. As a result, the output voltage V2 of the line 30 becomes as shown in Expression 1. V2 = Vr (R1 + R2) / R2 (1) Here, Vr is a reference voltage.

The time constant ΔT1 = R3 · C4 constituted by the resistor R3 and the capacitor C4 is selected to be a value exceeding the rise time of a circuit to be supplied with power from the line 30, for example, a circuit including the processing circuit 31 and the like. . Thus, the switching regulator 29 can be started stably. At time t13 when the power is turned off, the capacitor C
The charge of No. 4 is discharged by the resistor R4, and after the time t14, the transistor TR4 is turned off.

A configuration for reducing power consumption in a period during which an output signal is not derived in data storage device 1 will be described. The data output terminal TXD of the transmission / reception interface circuit UART32 from the processing circuit 31 via the data bus 33
And each output signal from the data request output terminal RTS is derived from the buffers Q3 and Q4 via the signal output lines 10 and 11, and is output to the signal input line 1 in the arithmetic processing unit 2.
4, 15 are given. In the arithmetic processing unit 2, load resistors 46 and 47 are connected to the signal input lines 14 and 15, respectively. The load resistors 46 and 47 are provided for receiving the input signal without distortion, and are provided on the data storage device 1 side which is the impedance of the communication cable including the lines 10, 11, 14, and 15 and the signal source. The resistance value is set in consideration of the resistance. A data output signal is derived from the data output terminal TXD. The output signal from the data request output terminal RTS synchronizes with the data processing device 2 on the receiving side when the data storage device 1 and the processing device 2 communicate with each other, whether the data is currently received or not. To derive a data request output signal for

In order to obtain the internal power, the data storage device 1 receives the input signals from the data input terminal RXD and the data request input terminal CTS via the lines 8 and 9 as described above, and obtains the power. ing. This data storage device 1
In order to derive and drive an output signal from the signal output lines 10 and 11, energy is required as in the case of input, and therefore, energy for driving internal circuit components can be allocated for this output. become unable. However, since the data storage device 1 stores and reads data in and from the memory 36, it is not necessary to simultaneously receive an input signal and transmit an output signal. Therefore, in the present invention, utilizing this fact, the signal output switching elements SW1 and SW2 are interposed in the signal output lines 10 and 11. In order that these switching elements SW1 and SW2 are not simultaneously turned on,
The processing circuit 31 supplies and controls a switching control signal via the buffers Q1 and Q2, and controls the output signal TX.
When D and RTS are not derived, these switching elements SW1 and SW2 are kept off at the same time.

FIG. 6 shows the operation of the processing circuit 31 when the data input signal is input from the arithmetic processing unit 2 to the data storage device 1 and stored in the memory 36 when the output signal is derived from the data request output terminal RTS. 5 is a flowchart for explaining FIG. When the operator presses the data input instruction key 48 provided on the key input means 35, the processing circuit 31 determines that the data should be input, and at step a1 in FIG. A signal for conducting the switch SW2, which has been turned on, is derived via the buffer Q2. In step a2, the processing circuit 31 derives a data request output signal of logic “1” from the data request output terminal RTS of the transmission / reception interface UART circuit 32 to the signal output line 11 via the buffer Q4 and the switching element SW2,
In the arithmetic processing unit 2, the signal is applied to the signal input line 15 and received by a processing circuit such as a microcomputer following the load resistor 47. Thereby, the arithmetic processing unit 2 receives the aforementioned data request output signal from the data storage device 1 and derives the data output signal from the line 12 to the line 8 of the data processing device 1 in response thereto. In step a3, data reception is checked.

The processing circuit 31 checks the input signal from the line 8 and determines whether or not data has been detected in step a4. When the data is received and detected, the process proceeds from step a3 to step a5, where the data request output terminal is set to logic "0" from the state where the data request output terminal is set to logic "1" in step a2, and the data request is stopped. At step a6, the received data input signal is calculated and internally processed.

In step a7, it is determined whether or not the data is the last data of the data input signal from the data input terminal RXD from the line 8. If it is determined that the data is the last data, the switching element SW is determined in step a8.
2 is interrupted by a control signal via the buffer Q2. The determination as to whether the data is the last data in step a6 may be made by the operator operating a key provided in the key input means 35, or when the data input signal is received in step a3 described above. From the above, a point in time at which a predetermined reception time of a series of data input signals determined by a timer has elapsed may be detected, and furthermore, the number of received bytes of the data input signal may become a predetermined value and a series of data input signals may be detected. This may be achieved by detecting when the signal has been received.

FIG. 7 shows a processing circuit 3 when a data output signal from the processing circuit 31 is derived from the signal output line 10 and the data output terminal TXD and applied to the arithmetic processing circuit 2.
3 is a flowchart for explaining the operation of FIG. The data output signal from the data storage device 1
From the data input terminal R in the arithmetic processing unit 2.
From the XD through a signal input line 14, the signal is supplied to a processing circuit realized by the microcomputer or the like. The load resistor 46 is connected between the signal input line 14 and the ground potential as described above.

The data output terminal TX of the data storage device 1
In deriving the data output signal from D, the operator uses a data output key 49 provided on the key input means 35.
Operate. As a result, the processing circuit 31 sets the buffer Q1
The switching element SW1 is switched from the cut-off state to the conductive state via step b1 in step b1. Processing circuit 31
Is the transmission / reception interface circuit U in step b2.
At the data request input terminal CTS of the ART 32, it is determined whether or not a data request input signal is given from the arithmetic processing unit 2 via the signal input line 9 and the buffer Q6. In step b3, the processing device 31 transmits the data request input signal CTS from the arithmetic processing device 2 to the transmission / reception interface circuit UAR via the line 9 and the buffer Q6.
If it is determined at T32 that the data has been received, that is, if it is determined that the data request input terminal CTS is logic “1”, the process proceeds to the next step b4, where the processing circuit 31
A data output signal is transmitted from the data output terminal TXD of the transmission / reception interface circuit UART32 via the buffer Q3, and further from the signal output line 10 via the switching element SW1.

When it is determined in step b5 that the data is the last data to be transmitted, in step b6, the processing device 31 shuts off the switching element SW1 by the control signal via the buffer Q1. In this way, by shutting off the switching element SW2 in step a8 in FIG. 6 and shutting off the switching element SW1 in step b6 in FIG. 7, a period during which no output signal is derived, that is, the transmission / reception interface circuit UART
Although the 32 output terminals RTS and TXD are maintained at +10 V or -10 V corresponding to one of the logical values, heat consumption of energy by the load resistors 46 and 47 in the arithmetic processing unit 2 is prevented. Thus, the power consumption of the data storage device 1 can be reduced.

The determination as to whether the data is the last data in step b5 in FIG. 7 may be performed in the same manner as in step a7 in FIG.

Further, according to the present invention, there is provided a configuration for reducing power consumption for erasing memory contents in flash memory 36 which is a nonvolatile memory. In the flash memory 36, all bits of the floating gate 52, which is a memory area, are written to one logical value, for example, logical "0" for erasing while changing the address of each bit.

FIG. 8 shows the lapse of time of the current consumed in the erasing operation when power is continuously supplied to the flash memory 36 to perform the erasing operation step. This first erase operation step is performed in a period of about 0.4 sec from the start of the erase operation shown in FIG. At this time, the current consumed by the flash memory 36 for the erasing operation is about 15 mA as shown in FIG. 8, which is relatively small.

Thereafter, the flash memory 36 performs an erasing step for removing the electric charge from the floating gate 52. This erasing step is performed for about 0.4 to 0.7 seconds after the start of the erasing operation in FIG. It is performed in. Since the erasing operation for removing the charge of the floating gate 52 is performed in units of several kilobytes in block units, a relatively large current is consumed. In FIG. 8, for example, the maximum value reaches about 35 mA. The sequential steps of such an erasing operation are stored in a sequence counter 53 built in the flash memory 36.

The sequence counter 53 provided inside the semiconductor chip in the flash memory 36 controls the sequence operation of the steps of the erase operation. Therefore, even if the erasing operation is temporarily interrupted, the stored value of the sequence counter 53 is retained, and when resuming, the steps of the erasing operation are continuously performed from there. That is, by giving the suspend command signal from the processing circuit 31 to the flash memory 36, the step of the erasing operation of the flash memory 36 can be interrupted, and then by giving the resume command signal from the processing circuit 31 to the flash memory 36. According to the stored contents of the sequence counter 53, the steps of the erase operation can be restarted, and the steps of the erase operation can be continuously performed.

In the flash memory 36, after the electric charge of the floating gate is released, as apparent from FIG.
A current for erasing A flows, and an erasing operation step is performed.

In the data storage device 1, the load current that can be supplied from the switching regulator 29 using the first to third capacitors C1 to C3 is at most 5 mA. Therefore, it is impossible to erase the stored contents of the flash memory 36 as it is. Therefore, in the present invention, erasing can be performed without supplying a current continuously for, for example, 1 second.

For erasing, capacitors C1 to C3
In addition, a configuration in which charge is accumulated for a relatively long time and discharged at once may be easily conceived. However, in such a configuration, in order to charge the capacitors C1 to C3 with a large charge and discharge all the charges at once to supply a large current, the capacitance of the capacitors C1 to C3 is increased. There is a need. In that case, miniaturization becomes impossible. Moreover, with such a large-capacity capacitor, FIG.
As shown in the equivalent circuit of the capacitor, the larger the capacitance C, the higher the resistance value R54 of the equivalent series resistor 54. 9 indicates a circuit that consumes power including the flash memory 36. Therefore, there is a problem that a large voltage drop occurs at the time of discharge, and the efficiency is greatly reduced. The voltage drop E of the capacitor due to the internal resistor 54 is
It is shown by Equation 2. E = IR54 (2)

Here, I in the equation 2 is the discharge current of the capacitor having the capacitance C shown in FIG. 9, and R54 is the resistance value of the equivalent series resistor 54. At the time of discharging, a large current flows, so that a large voltage drop E occurs. For example, when the capacitor is an electric double layer capacitor, the equivalent series resistance 5
4 is, for example, 20 Ω. Therefore, when a current of, for example, 35 mA flows through the flash memory 36 in the erase operation step, about 0.7 V (= 35 m
A × 20Ω), a large voltage drop E occurs. Therefore, the power supply voltage of the computer circuit led to line 30 from switching regulator 29 is, for example, 3.0.
At V, the efficiency will drop by about 23%.

In the present invention, in order to solve the above-mentioned problem, the flash memory 36 is erased in a time-division manner, each time w1 and w3 of the fragmentation operation of the stored contents is shortened, and the capacity of the capacitors C1 to C3 is reduced. Even if it is small, the stored contents of the flash memory 36 can be erased, and the size can be reduced. In the flash memory 36, the erase operation, the memory write operation, the read operation, etc.
It is controlled by the control circuit 55. The control circuit 55 performs an address specification of the memory area 51 in units of blocks, a control of an operation of removing the charge of the floating gate 52, a counting operation of the sequence counter 53, and the like for erasing the stored contents. To achieve.

The processing circuit 31 counts the time from the timer 56 by the counter 57 and performs the operation shown in FIG.
As a result, as shown in FIG. 11, the operation of erasing the stored contents of flash memory 36 and the standby operation without performing the erasing operation are repeated, and the duty ratio is changed to the value of the erasing operation step of flash memory 36 shown in FIG. The time corresponding to the duty ratio is set in the counter 57 in accordance with the current required for the erasing operation over time.

FIG. 11A shows the lapse of time of current consumption in the erasing operation of the flash memory 36, and this time is expanded on a time axis as compared with FIG. FIG. 11 (2)
FIG. 4 is a diagram showing a current supply state for an erasing operation of the flash memory 36 by the processing circuit 31. As shown in FIG. 11, the time w1 for performing the operation of erasing the stored contents of the flash memory 36 is relatively short, and the standby time w2
, The erasing operation of the flash memory 36 can be performed even if the capacitances of the capacitors C1 to C3 are reduced. Moreover, the capacitors C1 to C3 having such a small capacitance are connected to the equivalent series resistance 54.
(See FIG. 9 above), thus reducing the voltage drop and improving efficiency.

In one embodiment of the present invention, the erasing operation of the flash memory 36 is performed for a predetermined period of time w1, w
3, these times w1 and w3 are, for example, about 10 msec, and the waiting times w2, w4 depend on the current required for the erase operation, for example, 100 to 20.
The value is set within a range of values less than 0 msec in accordance with a current value necessary for the erasing operation of the flash memory 36, and is counted by the counter 57. Thus, the flash memory 36
During the execution of the erase operation step in which the current required for the erase operation is small, the duty ratio w1 / (w1 + w2) between the erase time w1 and the standby time w2 is selected to be large, for example, 10 /
(10 + 100), and the duty ratio is selected to be small during execution of the step of the erasing operation with large current consumption, for example, 10 / (10 + 200).

Referring again to FIG. 10, when the operation of erasing the stored contents of flash memory 36 is started in step c1, the current consumption required for erasing flash memory 36 over time in FIG.
1 is stored in advance in a memory provided in the device 1. The erasing times w1 and w3 are, for example, 10 msec and fixed as described above. During the standby times w2 and w4, the erasing operation of the flash memory 36 is not performed. At this time, the capacitors C1 to C3 are charged by the input signals via the signal input lines 8 and 9.

In step c2, the flash memory 36
The standby time w2 corresponding to the current consumption is set in the counter 57. In step c3, the output of the timer 56 that performs the aging operation after the start of the erasing operation is set to 1 every fixed time.
Decrement by one. When the count value of the counter 57 becomes zero in step c4, the erasing operation is stopped in step c5. If the erase operation has not been completed for all the stored contents of the flash memory 36 in step c6, the process further proceeds to step c7.
The standby time w2 is set in the counter 57. In the next step c8, the counter 57 is decremented by a predetermined time. In step c9, when the stored content of the counter 57 becomes zero and the preset standby time w2 has elapsed, in step c10, the erasing operation of the flash memory 36 is restarted.

Although FIG. 10 has been described with reference to the erasing time w1 and the waiting time w2, the same applies to the erasing time w3 and the waiting time w4 in FIG. By changing the duty ratio in this way,
The load current on the signal input lines 8, 9 can be made constant at a predetermined value suitable for receiving the input signal without distortion. Therefore, the signal input line 8,
9, a function of eliminating distortion of the received input signal due to the load resistance can be achieved without connecting the load resistance.

FIG. 12 is a simplified plan view of data storage device 1. For example, a D-SUB 25-pin connector section 5 is fixed to one side of a flat, substantially rectangular parallelepiped housing 4. All the components shown in FIG. 1 are housed in the housing 4. The housing 4 is provided with liquid crystal display means 34 and input means 35 such as keys. The key input means 35 is for inputting information for controlling the operation of the processing circuit 31.
8,49. The display means 34 displays the processing contents of the processing circuit 31 and the like, for example, displays the contents of input signals and output signals.

According to another concept of the present invention, the configuration for changing the duty ratio in order to perform the erasing operation of the flash memory 36 with a small-capacity power supply is only implemented in connection with the data storage device 1. However, the present invention can be implemented in other configurations. For example, in addition to the configuration in which the power of the input signal is charged to the capacitors C1 to C3, the present invention can be implemented in a wide range in connection with other small-capacity power supplies.

[0074]

According to the first aspect of the present invention, the power supplied to the processing circuit for controlling the store operation of the memory can be obtained from the input signal transmitted to the signal input line. There is no need to provide an external power supply. Therefore, by providing an input signal to the signal input line, the stored contents of the memory can be stored for a long period of time.

According to the second aspect of the present invention, the input signal is:
For example, it has a waveform that changes over both polarities above and below a reference potential, which is a ground potential, stores charges of one polarity in the first capacitor C1 via one diode D1, and charges of the other polarity to the other diode D3. , And is stored in the second capacitor C2. The charge of the second capacitor C2 is inverted by the polarity conversion circuit and
3, and can be charged, whereby power can be obtained according to the positive and negative voltage changes of the input signal.

According to the third aspect of the present invention, the first and second switching elements TR1 and TR2 are alternately turned on / off by the output of the oscillation circuit, and the third capacitor C2 is inverted by inverting the charge of the second capacitor C2. It can be stored in C3. The specific configuration of the polarity conversion circuit has a relatively simple configuration, is highly efficient, and is advantageous for implementing the present invention.

According to the present invention, it is possible to use a step-down type chopper type switching regulator having a high efficiency and a simple structure, and thus to reliably obtain power for a processing circuit by a weak input signal. it can.

According to the fifth aspect of the present invention, the step-down chopper type switching regulator is provided with a power-on switching element TR4 and a time constant circuit to reduce the inrush current at the time of startup by the processing circuit and the oscillation circuit. It is possible to make the switching regulator as stable as possible with as little as possible.

According to the sixth aspect of the present invention, the signal output switching elements SW1 and SW2 are interposed in the signal output line and are kept off except when the output signal from the processing circuit is derived. Thus, power consumption can be reduced.

Further, in the present invention, each of the write and read operations of the memory is not performed at the same time. Therefore, even in the configuration in which the signal output lines for data output and data request output are provided as described above, Only one of the signal output switching elements SW1 and SW2 for each signal output line is turned on, and a large current consumption is prevented from flowing at the same time.
Thus, the operations of the processing circuit and the memory can be performed stably.

According to the seventh aspect of the present invention, it is possible to prevent the power consumption in performing the erasing operation of the stored contents of the flash memory from being required in a short time, and to perform the erasing operation in a time-division manner. First to third capacitors C1 to C3
The erase operation can be performed while charging is performed. In this way, the erasing operation of the nonvolatile memory, which is a flash memory, is temporarily suspended, and after a waiting period, the erasing operation is resumed. As a result, the erasing time can be apparently shortened as compared with the case where all the stored contents are continuously erased. Thus, the charge / discharge time of the capacitor per unit time can be shortened. Therefore, the capacity of the capacitor can be reduced, and a capacitor having a low equivalent series resistance can be used.

Further, according to the present invention, the duty ratio for performing the erasing operation of the flash memory is changed, so that the average current flowing through the signal input line can be made constant. Thus, the function of eliminating the distortion of the input signal by using the load resistance of the original input signal can be achieved by the power supply circuit.

According to the eighth aspect of the present invention, the cable can be eliminated by fixing and integrating the connector with the housing. This eliminates the need to consider the installation location of the data storage device, and solves the problem of installation location. Furthermore, the effect of eliminating the need for an external power supply, which is an important feature of the present invention, can be effectively utilized.

[Brief description of the drawings]

FIG. 1 is an electric circuit diagram showing an entire configuration of an embodiment of the present invention.

FIG. 2 is a terminal RX on lines 8 to 15 shown in FIG. 1;
FIG. 4 is a waveform chart for explaining signal levels of D, CTS, TXD, and RTS.

FIG. 3 is a diagram showing a switching state of transistors TR1 and TR2.

FIG. 4 is an electric circuit diagram showing a specific configuration of a step-down chopper switching regulator 29.

5 is a switching regulator 29 shown in FIG.
It is a figure for explaining operation of.

FIG. 6 is a flowchart illustrating an operation of a processing circuit 31 for reducing power consumption in the data storage device 1.

FIG. 7 is a flowchart for explaining an operation of the processing circuit 31 when a data output signal is derived from the signal output line 10 and the data output terminal TXD from the processing circuit 31 and applied to the arithmetic processing circuit 2;

FIG. 8 is a diagram showing a lapse of time of a current consumed in the erasing operation when power is continuously supplied to the flash memory and an erasing operation is performed.

FIG. 9 is an equivalent circuit diagram showing that a voltage drop occurs due to the internal resistance when the power of the capacitor C is consumed by the load 55;

FIG. 10 is a flowchart for explaining an operation of the processing circuit 31 showing an operation of supplying / cutting off a current supplied to the flash memory 36 during an erasing operation of the flash memory 36;

FIG. 11A shows the lapse of current consumption in the erasing operation of the flash memory 36, and FIG.
FIG. 4 is a diagram showing a current supply state for an erasing operation of the flash memory 36 by the processing circuit 31.

FIG. 12 is a simplified plan view of the data storage device 1.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Data storage device 2 Arithmetic processing unit 3 Connector 4 Housing 5, 7 Connector part 8, 9, 14, 15 Signal input line 10, 11, 12, 13 Signal output line 16, 17 Buffer 18, 19 Internal resistance 23 Power supply circuit 24 Voltage polarity conversion circuit 27 Oscillation circuit 29 Step-down chopper switching regulator 31 Processing circuit 32 UART 33 Data bus 34 Liquid crystal display means 35 Key input means 36 Flash memory 38 Voltage dividing circuit 40 Comparison circuit 41 Reference voltage source 42 Control circuit 43 Time constant Circuit 52 Floating gate 53 Sequence counter 56 Timer 57 Counter

Claims (8)

[Claims] 1. Diodes D1 and D3 connected to a signal input line to which an input signal is applied, capacitors C1 and C2 charged by current flowing through the diodes D1 and D3, and an input signal from a signal input line. A data storage device comprising: a memory for storing; a processing circuit for storing an input signal in the memory; and a power supply circuit for energizing the processing circuit by outputs of the capacitors C1 and C2. 2. The input signal has a waveform that varies between a positive polarity and a negative polarity with respect to a reference potential. The diodes D1 and D3 are connected to a signal input line with a pair of diodes D1 and D2, respectively, having opposite polarities. , D
And a first capacitor C1 connected between the output of one diode D1 and a reference potential.
1 and a second capacitor C2 connected between the output of the other diode D3 and the reference potential. The power supply circuit inverts the polarity of the output of the third capacitor C3 and the output of the second capacitor C2. 2. The data storage device according to claim 1, further comprising: a polarity conversion circuit that supplies an output of the second capacitor C2 to the third capacitor C3 to charge the third capacitor C3. 3. The polarity conversion circuit is connected between an output of the first capacitor C1 and a reference potential, and is connected in series with third and fourth diodes D5 and D5.
6, a first switching element TR1 having one terminal connected to the output of the second capacitor C2, and one terminal connected to the other terminal of the first switching element TR1 opposite to the second capacitor C2, The second switching element TR2 having the other terminal connected to the reference potential, and the first and second switching elements TR1 and TR2 are turned on so that the other is cut off when one is turned on and the other is cut off when the other is turned on. And an oscillating circuit for controlling off / off, one terminal of the third capacitor C3 is connected to a connection point of the third and fourth diodes D5 and D6, and the other terminal of the third capacitor C3 is connected to the first switching element TR1. The other terminal and the second switching element TR2
3. The data storage device according to claim 2, wherein the oscillation circuit is connected to a connection point with the one terminal, and the oscillation circuit is energized by outputs of the first and third capacitors C <b> 1 and C <b> 3. 4. A step-down chopper switching regulator is interposed between the output of the first and third capacitors C1 and C3 and the processing circuit. The step-down chopper switching regulator comprises: (a) a switching transistor TR3; (B) an inductance element L1 connected to the switching transistor TR3; (c) a capacitor C5 to which the output of the inductance element L1 is applied; and (d) a control terminal of the switching transistor TR3 in response to the output voltage of the inductance element L1. When the output voltage is lower than a predetermined reference voltage, the duty ratio is changed so that the ratio of the conduction period of the switching transistor TR3 becomes longer. When higher than voltage Data storage device according to claim 2 or 3 further characterized in that a control circuit for the rate of the conduction period of the switching transistor TR3 changes the duty to be shorter. 5. A step-down chopper switching regulator, wherein the output voltage is divided by a voltage dividing circuit composed of voltage dividing resistors R1 and R2 and input to a control circuit, and the power supply switching element TR4 is connected in series with the voltage dividing circuit. Is connected, has a time constant longer than the rise time when the voltage of the processing circuit is turned on, and outputs the outputs of the first and third capacitors C1 and C3.
5. The data storage device according to claim 4, further comprising: a time constant circuit that changes the power-on switching element TR4 from a cut-off state to a conductive state with a delay by the time constant. 6. A signal output switching element for outputting an output signal from a processing circuit.
2, the output signal output from the processing circuit to the signal output line is:
The signal processing circuit has a waveform that changes over a positive polarity and a negative polarity with respect to a reference voltage, and the processing circuit keeps the signal output switching elements SW1 and SW2 shut off except when the output signal is derived. The data storage device according to one of claims 1 to 5. 7. The memory is a flash memory, and in order to erase stored contents, all bits of a memory area are written to one logical value while changing the address of each bit. Erasing operations are sequentially performed. The erasing operation steps are stored in a sequence counter built in the memory, and the current consumption required for executing the erasing operation of the memory is determined by the progress of the erasing operation steps. And the erase operation can be interrupted. When the erase operation is resumed, the erase operation step is continuously performed according to the stored contents of the sequence counter. The duty ratio w1 / (w of the erase time w1 and the standby time w2)
7. The data storage device according to claim 1, wherein the duty ratio w3 / (w3 + w4) is selected to be small during execution of the step of the erasing operation which consumes a large amount of current. . 8. A configuration in which a connector is detachably connected to a signal input line and a signal output line, the connector is fixed, and includes diodes D1 and D3, capacitors C1 and C2, a memory, a processing circuit, and a power supply circuit. A housing housing the components; a liquid crystal display provided on the housing for displaying the processing content of the processing circuit; and an input means provided on the housing for inputting an upper part for controlling the operation of the processing circuit. Claim 1
8. The data storage device according to one of claims 7 to 7.