JPH1173232A - Current limiting circuit and voltage regulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To monitor the collector/emitter potential of a control transistor, to limit the generation of a base current increasing phenomenon generated in the base of a control transistor Q1 in a low input voltage period when the collector/emitter potential is less than a prescribed voltage, and to lengthen a life by escaping the current consumption load of a power source due to base increasing currents. SOLUTION: A current limiting circuit for limiting base currents IB of a control transistor Q1 for controlling load currents has a circuit constitution in which a collector/emitter potential difference VCE of a control transistor Q1 is monitored, base currents IB running through the control transistor Q1 in a low input voltage period are continuously limited when the collector/emitter potential difference VCE is less than a prescribed potential, the decrease of DC current amplification ratio hFE of the control transistor Q1 is limited, the collector/emitter potential difference VCE of the control transistor Q1 is held to be more than a constant value, and the generation of a base current increasing phenomenon generated in the base of the control transistor Q1 is limited.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and, more particularly, to a current limiting circuit for limiting a base current of a control transistor for controlling a load current, and a constant voltage power supply for maintaining a constant output voltage supplied to the load. A voltage regulator.

[0002]

2. Description of the Related Art FIG. 9 is a circuit diagram for explaining a conventional current limiting circuit.

A conventional current limiting circuit of this type is disclosed, for example, in Japanese Patent Application Laid-Open No. 5-217717 (title of current: current limiting circuit, applicant: MITSUMI ELECTRIC CO., LTD., Filing date: 19)
(See FIGS. 9 and 10 on January 30, 1992).

[0004] That is, as shown in FIG.
an output voltage detection circuit 4 for detecting the difference between the base current of the p-transistor AQ1 and the load current ARL by the transistors AQ6 and AQ7 and the operational amplifier A2;
Transistor AQ4 according to the detection signal detected by
Is controlled to control the pnp transistor AQ
The current limiting circuit 3 limits one base current.

The output voltage detection circuit 4 is connected to the power supply 1 (input voltage Vi) and comprises a constant current source OC1, a Zener diode D1, resistors AR1 and AR2, an operational amplifier A1 constituting a differential amplifier circuit, and an npn transistor AQ4. It had been.

The output voltage detection circuit 4 having such a circuit configuration
, The constant current source OC1 and the Zener diode D1
Generates a reference voltage, which is input to the inverting input terminal of the operational amplifier A1. Also, the output voltage Voutut, the resistance AR
1. The detection signal attenuated by AR2 is the operational amplifier A1
Is input to the non-inverting input terminal.

[0007] The operational amplifier A1 outputs a signal corresponding to the difference between the reference voltage and the detection voltage, and supplies the signal to the base of the transistor AQ4. The emitter of the transistor AQ4 is connected to the base of the transistor AQ2.
Is a multi-collector transistor AAQ1
(Control pnp transistor AQ1).

The current limiting circuit 3 includes a power supply 1 (input voltage V
i), and a pnp transistor AQ2 for current detection,
Operational amplifier A2 constituting a comparator, control pnp
It comprises a transistor AQ1 and a constant current source OC2. The npn transistors AQ6 and AQ7 are diode-connected and connected to the non-inverting input terminal of the operational amplifier A2 with their respective collectors connected. In such a circuit configuration, the pnp transistor AQ2 controls the base current of the control pnp transistor AQ1 according to the signal supplied from the output voltage detection circuit 4.

[0009]

FIG. 10 is a graph for explaining a base increase current generated at the base of the control transistor of FIG.

However, in such a conventional current limiting circuit, when the input voltage Vi is low and the input voltage is low, the control p.
Since the potential difference VCE between the collector and the emitter of the np transistor AQ1 decreases, the control pn
The DC current gain of the p-transistor AQ1 decreases, and a sufficient load current AIL (collector current) is supplied to the load A
There was a situation where it was not possible to supply RL. In a conventional current limiting circuit, such a control pnp transistor A
Load current AIL due to the decrease in DC current gain of Q1
In order to avoid a decrease in the (collector current) supply capability, compensation control has been performed to increase the base current IB of the control pnp transistor AQ1. When such a compensation control is executed, the base current IB exhibits a triangular waveform characteristic (called a base increase current) as shown in FIG. There is a problem that the burden on the user increases. In particular, when a battery is used as the power supply 1,
There is a problem that the consumption current required for the compensation control is taken out of the battery, so that the consumption of the battery is expedited.

An object of the present invention is to solve such a conventional problem. First, in a current limiting circuit for limiting a base current of a control transistor for controlling a load current, the collector of the control transistor is controlled. The potential difference between the emitters is monitored, and the base current flowing through the control transistor is continuously limited during the low input voltage period in which the potential difference between the collector and the emitter is equal to or less than a predetermined voltage, thereby reducing the DC current gain of the control transistor. The voltage difference between the input voltage and the output voltage from the power supply is reduced by the circuit configuration that limits the potential difference between the collector and the emitter of the control transistor so as to limit the generation of the base increase current generated at the base of the control transistor. Even when the input voltage is small, the potential difference between the collector and the emitter of the control transistor is low. Avoids would become and is an object to avoid a decrease in DC current gain of the control transistor to provide a current limiting circuit capable of supplying a sufficient load current to a load.

Furthermore, as a result of avoiding a decrease in the DC current gain of the control transistor, it is possible to avoid a decrease in the load current supply capability, and it is not necessary to perform compensation control for increasing the base current of the control transistor. A current limiting circuit that can avoid the occurrence of a base increase current in the base current, thereby avoiding an increase in power consumption due to the occurrence of the base increase current, and an increase in the load on the power supply due to the base increase current. It is intended to provide. In particular, it is an object of the present invention to provide a current limiting circuit capable of avoiding an increase in current consumption due to an increased base current when a battery is used as a power source and extending the life of the battery.

Second, in a voltage regulator which is a constant voltage power supply for maintaining a constant output voltage supplied to a load, an output voltage setting for generating an output voltage according to the magnitude of the current when the current is applied A resistor network, a control transistor for applying a control current to the output voltage setting resistor network to control the voltage of the output node of the output voltage setting resistor network and the output voltage supplied to the load to a constant voltage value, and control. A current limiting circuit for limiting a base current of the transistor;
A reference power supply that generates a reference voltage using a current source, and a voltage difference between a reference voltage from the reference power supply and an output node voltage is detected to generate an error signal based on the voltage difference, and the error signal is fed back to the control transistor. Amplifier having a feedback loop that promotes constant voltage control for keeping the output voltage supplied to the load constant, and control for limiting the error signal output from the error amplifier or the base current output from the third MOSFET A fourth MOSFET for selectively transmitting a signal to the base of the control transistor, wherein the fourth MOSFET is connected to the third MOSFET during a low input voltage period.
The control signal output from the FET is selected and transmitted to the control transistor to promote the control of the base current in the control transistor, and the error signal from the error amplifier is selected and transmitted to the control transistor during periods other than the low input voltage period. The circuit configuration that promotes constant voltage control in the transistor allows the base current flowing through the control transistor to be continuously limited even at a low input voltage when the voltage difference between the input voltage from the power supply and the output voltage is small, and Limits the decrease in DC current gain and controls the collector of the transistor.
The potential difference between the emitters is kept at a certain level or more to limit the generation of the base increase current generated at the base of the control transistor. As a result, the potential difference between the collector and the emitter of the control transistor is prevented from being reduced, and the control is performed. It is an object of the present invention to provide a voltage regulator capable of supplying a sufficient load current to a load while avoiding a decrease in a DC current gain of a transistor.

Furthermore, as a result of avoiding a decrease in the DC current gain of the control transistor, it is possible to avoid a decrease in the load current supply capability, and it is not necessary to perform compensation control for increasing the base current of the control transistor. A current limiting circuit that can avoid the occurrence of a base increase current in the base current, thereby avoiding an increase in power consumption due to the occurrence of the base increase current, and an increase in the load on the power supply due to the base increase current. It is intended to provide. In particular, it is an object of the present invention to provide a voltage regulator capable of avoiding an increase in current consumption due to an increased base current when a battery is used as a power supply and extending the life of the battery.

[0015]

According to a first aspect of the present invention, in a current limiting circuit for limiting a base current IB of a control transistor Q1 for controlling a load current, a potential difference VCE between a collector and an emitter of the control transistor Q1 is controlled. The control transistor Q1 is monitored at a low input voltage when the collector-emitter potential difference VCE becomes lower than a predetermined voltage.
Is a current limiting circuit 10 having a circuit configuration for limiting a base current IB flowing through the circuit.

According to the first aspect of the present invention, the conventional compensation control for increasing the base current IB of the control transistor Q1 is used even at a low input voltage when the collector-emitter potential difference VCE is small. Therefore, the occurrence of the base current increase phenomenon in the base current IB of the control transistor Q1 can be avoided at an arbitrary timing at a low input voltage. As a result, an increase in power consumption during circuit operation due to the generation of the base increase current in the base current IB can be avoided at an arbitrary timing at a low input voltage, and the current consumption burden of the power supply due to the base increase current can be prevented. Increase can be avoided at an arbitrary timing at the time of a low input voltage. In particular, when the battery 22 is used as a power source, an increase in current consumption due to the base increase current can be avoided at an arbitrary timing at a low input voltage, and unnecessary life of the battery 22 can be avoided to extend the life. It has the effect of becoming

According to a second aspect of the present invention, there is provided a current limiting circuit for limiting a base current IB of a control transistor Q1 for controlling a load current, wherein a potential difference VCE between a collector and an emitter of the control transistor Q1 is monitored.
A current limiting circuit 10 having a circuit configuration for continuously limiting a base current IB flowing through the control transistor Q1 during a low input voltage period in which the emitter potential difference VCE is equal to or lower than a predetermined voltage.

According to the second aspect of the present invention, the collector-emitter potential difference VCE of the control transistor Q1 continues to decrease even during the low input voltage period in which the collector-emitter potential difference VCE is small. Supply of a sufficient load current to the load 24 by continuously avoiding a decrease in the DC current gain hFE of the control transistor Q1 caused by the collector-emitter potential difference VCE within the low input voltage period. It has the effect of being able to do so.

Further, as described above, the decrease in the DC current gain hFE of the control transistor Q1 caused by the collector-emitter potential difference VCE can be continuously avoided within the low input voltage period, so that the load current supply It is possible to continuously prevent the performance from being lowered during the low input voltage period, and to use the control transistor Q1 without using the conventional compensation control for increasing the base current IB of the control transistor Q1.
Of the base current IB can be continuously avoided within the low input voltage period. As a result, an increase in power consumption during circuit operation due to the occurrence of the base increase current in the base current IB can be continuously avoided within the low input voltage period, and the current consumption of the power supply caused by the base increase current can be reduced. The effect of this is that the increase in can be continuously avoided within the low input voltage period. In particular, when the battery 22 is used as a power supply, an increase in current consumption due to the base increase current is continuously avoided within the low input voltage period, and unnecessary consumption of the battery 22 can be avoided to extend the life. It has the effect of becoming

The invention described in claim 3 is the first or second invention.
In the current limiting circuit 10, the emitter of the control transistor Q1 is connected to the input voltage Vi, and the collector is connected to the output voltage Voutut to supply a load current to the load 24, and the input voltage Vi and the output voltage Voutut Is a current limiting circuit 10 having a circuit configuration for monitoring the potential difference of the base current IB to limit the base current IB.

According to the invention described in claim 3, according to claim 1 of the present invention,
Or, the same effect as the effect described in 2 can be obtained.

According to a fourth aspect of the present invention, in a current limiting circuit for limiting a base current IB of a control transistor Q1 for controlling a load current, a potential difference VCE between a collector and an emitter of the control transistor Q1 is monitored.
At a low input voltage when the potential difference VCE between the emitters becomes equal to or less than a predetermined voltage, the DC current amplification factor hFE of the control transistor Q1 is reduced.
Is a current limiting circuit 10 having a circuit configuration for limiting the reduction of the current.

According to the fourth aspect of the present invention, even when the collector-emitter potential difference VCE is small and the input voltage is low, a decrease in the DC current gain hFE of the control transistor Q1 can be limited, and the DC current gain can be reduced. An increase in base current, which is caused by a decrease in hFE, can be avoided at an arbitrary timing at a low input voltage. As a result, an increase in power consumption during circuit operation due to the generation of the base increase current in the base current IB can be avoided at an arbitrary timing at a low input voltage, and the current consumption burden of the power supply due to the base increase current can be prevented. Increase can be avoided at an arbitrary timing at the time of a low input voltage. In particular, when the battery 22 is used as a power supply, an increase in current consumption due to the base increase current is avoided at an arbitrary timing when the input voltage is low, and the battery 22
There is an effect that the service life can be prolonged by avoiding unnecessary consumption.

According to a fifth aspect of the present invention, there is provided a current limiting circuit for limiting a base current IB of a control transistor Q1 for controlling a load current, wherein a potential difference VCE between a collector and an emitter of the control transistor Q1 is monitored.
A current limiting circuit 10 having a circuit configuration for continuously limiting a decrease in the DC current gain hFE of the control transistor Q1 during a low input voltage period in which the emitter-to-emitter potential difference VCE is equal to or lower than a predetermined voltage.

According to the fifth aspect of the present invention, the DC amplification factor hFE of the control transistor Q1 is maintained even during the low input voltage period in which the collector-emitter potential difference VCE is small.
This is advantageous in that a sufficient load current can be supplied to the load 24 by continuously avoiding a decrease in the load 24 during the low input voltage period.

Further, as described above, a decrease in the DC current gain hFE of the control transistor Q1 caused by the collector-emitter potential difference VCE can be continuously avoided during the low input voltage period. It is possible to continuously prevent the performance from being lowered during the low input voltage period, and to use the control transistor Q1 without using the conventional compensation control for increasing the base current IB of the control transistor Q1.
Of the base current IB can be continuously avoided within the low input voltage period. As a result, an increase in power consumption during circuit operation due to the occurrence of the base increase current in the base current IB can be continuously avoided within the low input voltage period, and the current consumption of the power supply caused by the base increase current can be reduced. The effect of this is that the increase in can be continuously avoided within the low input voltage period. In particular, when the battery 22 is used as a power supply, an increase in current consumption due to the base increase current is continuously avoided within the low input voltage period, and unnecessary consumption of the battery 22 can be avoided to extend the life. It has the effect of becoming

The invention described in claim 6 is the invention according to claim 3 or 4
In the current limiting circuit 10, the emitter of the control transistor Q1 is connected to the input voltage Vi, and the collector is connected to the output voltage Voutut to supply a load current to the load 24, and the input voltage Vi and the output voltage Voutut Is a current limiting circuit 10 having a circuit configuration for monitoring a potential difference of the DC current amplification factor hFE to limit a decrease in the DC current amplification factor hFE.

According to the invention described in claim 6, according to claim 3,
Or, the same effect as the effect described in 4 can be obtained.

According to a seventh aspect of the present invention, in a current limiting circuit for limiting a base current IB of a control transistor Q1 for controlling a load current, a potential difference VCE between a collector and an emitter of the control transistor Q1 is monitored.
A current limiter having a circuit configuration for limiting a decrease in a DC current amplification factor hFE caused by a decrease in the collector-emitter potential difference VCE of the control transistor Q1 at a low input voltage when the emitter potential difference VCE becomes equal to or less than a predetermined voltage. Circuit 10.

According to the seventh aspect of the present invention, even at a low input voltage when the collector-emitter potential difference VCE is equal to or less than a predetermined voltage, the decrease in the DC current amplification factor hFE is limited to reduce the base current IB. Can be avoided at an arbitrary timing when the input voltage is low. As a result, an increase in power consumption during circuit operation due to the generation of the base increase current in the base current IB can be avoided at an arbitrary timing at a low input voltage, and the current consumption burden of the power supply due to the base increase current can be prevented. Increase can be avoided at an arbitrary timing at the time of a low input voltage. In particular, when the battery 22 is used as a power source, an increase in current consumption due to the base increase current can be avoided at an arbitrary timing at a low input voltage, and unnecessary life of the battery 22 can be avoided to extend the life. It has the effect of becoming

According to an eighth aspect of the present invention, there is provided a current limiting circuit for limiting a base current IB of a control transistor Q1 for controlling a load current, wherein a potential difference VCE between a collector and an emitter of the control transistor Q1 is monitored.
During the low input voltage period in which the emitter potential difference VCE is equal to or lower than the predetermined voltage, the decrease in the DC current amplification factor hFE caused by the decrease in the collector-emitter potential difference VCE of the control transistor Q1 is continuously limited. This is a current limiting circuit 10 having a circuit configuration.

According to the present invention, the collector-emitter potential difference VCE of the control transistor Q1 is low even during the low input voltage period in which the collector-emitter potential difference VCE is equal to or lower than the predetermined voltage. And that the DC current amplification factor hFE of the control transistor Q1 caused by the collector-emitter potential difference VCE is continuously reduced during the low input voltage period. There is an effect that a current can be supplied to the load 24.

Further, as described above, the decrease in the DC current amplification factor hFE of the control transistor Q1 caused by the collector-emitter potential difference VCE can be continuously avoided during the low input voltage period. It is possible to continuously prevent the performance from being lowered during the low input voltage period, and to use the control transistor Q1 without using the conventional compensation control for increasing the base current IB of the control transistor Q1.
Of the base current IB can be continuously avoided within the low input voltage period. As a result, an increase in power consumption during circuit operation due to the occurrence of the base increase current in the base current IB can be continuously avoided within the low input voltage period, and the current consumption of the power supply caused by the base increase current can be reduced. The effect of this is that the increase in can be continuously avoided within the low input voltage period. In particular, when the battery 22 is used as a power supply, an increase in current consumption due to the base increase current is continuously avoided within the low input voltage period, and unnecessary consumption of the battery 22 can be avoided to extend the life. It has the effect of becoming

The ninth aspect of the present invention is the invention according to the seventh or eighth aspect.
In the current limiting circuit 10, the emitter of the control transistor Q1 is connected to the input voltage Vi, and the collector is connected to the output voltage Voutut to supply a load current to the load 24, and the input voltage Vi and the output voltage Voutut Is a current limiting circuit 10 having a circuit configuration for monitoring a potential difference of the DC current amplification factor hFE to limit a decrease in the DC current amplification factor hFE.

According to the ninth aspect of the present invention, the seventh aspect is provided.
Or, the same effect as the effect described in 8 can be obtained.

According to a tenth aspect of the present invention, in a current limiting circuit for limiting a base current IB of a control transistor Q1 for controlling a load current, a collector-emitter potential difference VCE of the control transistor Q1 is monitored. A current limiting circuit 10 having a circuit configuration for maintaining the collector-emitter potential difference VCE between the collector and the emitter of the control transistor Q1 at a certain level or more at a low input voltage at which the potential difference VCE between the control transistors falls below a predetermined voltage.

According to the tenth aspect of the present invention, even when the collector-emitter potential difference VCE is lower than a predetermined voltage at a low input voltage, the collector-emitter potential difference VCE is maintained at a certain level or more for control. A reduction in the DC current amplification factor hFE of the transistor Q1 is avoided at an arbitrary timing at a low input voltage, and the occurrence of a base current increase phenomenon in the base current IB caused by the reduction in the DC current amplification factor hFE is reduced. This can be avoided at an arbitrary timing during voltage application. As a result, an increase in power consumption during circuit operation due to the generation of the base increase current in the base current IB can be avoided at an arbitrary timing at a low input voltage, and the current consumption burden of the power supply due to the base increase current can be prevented. Increase can be avoided at an arbitrary timing at the time of a low input voltage. In particular, when the battery 22 is used as a power source, an increase in current consumption due to the base increase current can be avoided at an arbitrary timing at a low input voltage, and unnecessary life of the battery 22 can be avoided to extend the life. It has the effect of becoming

According to an eleventh aspect of the present invention, in a current limiting circuit for limiting a base current IB of a control transistor Q1 for controlling a load current, a collector-emitter potential difference VCE of the control transistor Q1 is monitored. A current limiting circuit 10 having a circuit configuration for continuously maintaining the collector-emitter potential difference VCE of the control transistor Q1 at a constant level or more during a low input voltage period in which the potential difference VCE is equal to or lower than a predetermined voltage.

According to the eleventh aspect of the present invention, even during the low input voltage period in which the collector-emitter potential difference VCE is equal to or lower than the predetermined voltage, the collector-emitter potential difference VCE is maintained at a certain level or more. Control transistor Q
(1) The decrease in the DC current amplification factor hFE is continuously avoided within the low input voltage period, and the occurrence of the base current increase phenomenon in the base current IB caused by the decrease in the DC current amplification factor hFE is reduced. It can be avoided continuously within the period. As a result, an increase in power consumption during circuit operation due to the occurrence of the base increase current in the base current IB can be continuously avoided within the low input voltage period, and the current consumption of the power supply caused by the base increase current can be reduced. The effect of this is that the increase in can be continuously avoided within the low input voltage period. In particular, when the battery 22 is used as a power supply, an increase in current consumption due to the base increase current is continuously avoided within the low input voltage period, and unnecessary consumption of the battery 22 can be avoided to extend the life. It has the effect of becoming

According to a twelfth aspect of the present invention, in the current limiting circuit of the tenth or eleventh aspect, the emitter of the control transistor Q1 is connected to the input voltage Vi and the collector is connected to the output voltage Voutut. Load current 2
4 is a current limiting circuit 10 having a circuit configuration for monitoring the potential difference between the input voltage Vi and the output voltage Voutut to maintain the collector-emitter potential difference VCE.

According to the twelfth aspect of the present invention, in addition to the effect of the tenth or eleventh aspect, even when the potential difference between the input voltage Vi and the output voltage Voutut is small, the potential difference between the collector and the emitter is small. By keeping VCE above a certain level, the DC current gain hFE of the control transistor Q1 is continuously prevented from lowering during the low input voltage period, and the DC current gain hFE is reduced.
Of the base current IB caused by the decrease of the base current IB can be continuously avoided within the low input voltage period. Thereby, the base current IB
In the low input voltage period, the increase in power consumption during circuit operation due to the occurrence of the base increase current can be continuously avoided, and the increase in the current consumption burden of the power supply due to the base increase current can be reduced. There is an effect that it can be avoided continuously within the period. In particular, when the battery 22 is used as a power supply, an increase in current consumption due to the base increase current is continuously avoided within the low input voltage period, and unnecessary consumption of the battery 22 can be avoided to extend the life. It has the effect of becoming

According to a thirteenth aspect of the present invention, in a current limiting circuit for limiting a base current IB of a control transistor Q1 for controlling a load current, a collector-emitter potential difference VCE of the control transistor Q1 is monitored. A current limiting circuit 10 having a circuit configuration for limiting the occurrence of a base current increase phenomenon that occurs at the base of the control transistor Q1 at the time of a low input voltage at which the potential difference VCE becomes equal to or lower than a predetermined voltage.

According to the thirteenth aspect of the present invention, even at a low input voltage when the collector-emitter potential difference VCE becomes equal to or less than a predetermined voltage, a circuit operation caused by the occurrence of the base increase current in the base current IB. Increase of power consumption at the time of low input voltage can be avoided at an arbitrary timing at a low input voltage, and an increase in current consumption burden of a power supply due to an increased base current can be avoided at an arbitrary timing at a low input voltage. This has the effect. In particular, when the battery 22 is used as a power source, an increase in current consumption due to the base increase current can be avoided at an arbitrary timing at a low input voltage, and unnecessary life of the battery 22 can be avoided to extend the life. It has the effect of becoming

According to a fourteenth aspect of the present invention, in a current limiting circuit for limiting a base current IB of a control transistor Q1 for controlling a load current, a collector-emitter potential difference VCE of the control transistor Q1 is monitored. A current limiting circuit 10 having a circuit configuration for continuously limiting the occurrence of a base current increase phenomenon occurring at the base of the control transistor Q1 during a low input voltage period in which the potential difference VCE is less than or equal to a predetermined voltage.

According to the fourteenth aspect of the present invention, even at a low input voltage when the collector-emitter potential difference VCE becomes equal to or less than a predetermined voltage, a circuit operation caused by the occurrence of the base increase current in the base current IB. Increase in power consumption during the low input voltage period,
This has the effect that the increase in the current consumption burden of the power supply caused by the base increase current can be continuously avoided within the low input voltage period. In particular, when the battery 22 is used as the power supply, the increase in the current consumption due to the base increase current is continuously avoided within the low input voltage period so that the battery 22
There is an effect that the service life can be prolonged by avoiding unnecessary consumption.

According to a fifteenth aspect of the present invention, in the current limiting circuit of the thirteenth or fourteenth aspect, the emitter of the control transistor Q1 is connected to the input voltage Vi, and the collector is connected to the output voltage Voutut. To the load 24, and the input voltage Vi and the output voltage Voutut
A current limiting circuit 10 having a circuit configuration for monitoring a potential difference between the current limiting circuit and the base current increasing phenomenon.

According to the fifteenth aspect, an effect similar to that of the thirteenth or fourteenth aspect is obtained.

According to a sixteenth aspect of the present invention, in the current limiting circuit 10 according to any one of the thirteenth to thirteenth aspects, the base increasing current is controlled by the control transistor Q1.
The current limiting circuit 10 is a base current IB resulting from a decrease in the collector-emitter potential difference VCE.

According to the sixteenth aspect of the present invention, the same effect as any one of the thirteenth to fifteenth aspects can be obtained.

According to a seventeenth aspect of the present invention, in the current limiting circuit 10 according to any one of the first to sixteenth aspects, the input voltage Vi applied to the control transistor Q1 is monitored to monitor the input voltage Vi. A first MOSFET that is activated during a low input voltage period in which the input voltage Vi is equal to or higher than a predetermined threshold voltage and transmits the activated input voltage Vi to the next stage
M1 and a second MOSFET which is activated in accordance with the degree of activation of the first MOSFET M1 to detect the output voltage Voutut, and transmits the detected output voltage Voutut to the next stage.
The current limiting circuit 10 includes an ETM2 and a third MOSFET M3 activated according to the degree of activation of the second MOSFET M2.

According to the seventeenth aspect of the present invention, in addition to the effects of any one of the first to sixteenth aspects, the control transistor Q1 is controlled during the low input voltage period in which the collector-emitter potential difference VCE is small. Even if the collector-emitter potential difference VCE is low, the fourth M
OSFET M4 is the base current IB of control transistor Q1
, The decrease in the DC current gain hFE of the control transistor Q1, which is a cause of the decrease in the base current IB, is continuously avoided during the low input voltage period, and a sufficient load current is applied to the load 24. This has the effect of being able to supply.

Further, as described above, the decrease in the DC current amplification factor hFE of the control transistor Q1 caused by the collector-emitter potential difference VCE can be continuously avoided within the low input voltage period, so that the load current supply It is possible to continuously prevent the performance from being lowered during the low input voltage period, and to use the control transistor Q1 without using the conventional compensation control for increasing the base current IB of the control transistor Q1.
Of the base current IB can be continuously avoided within the low input voltage period. As a result, an increase in power consumption during circuit operation due to the occurrence of the base increase current in the base current IB can be continuously avoided within the low input voltage period, and the current consumption of the power supply caused by the base increase current can be reduced. The effect of this is that the increase in can be continuously avoided within the low input voltage period. In particular, when the battery 22 is used as a power supply, an increase in current consumption due to the base increase current is continuously avoided within the low input voltage period, and unnecessary consumption of the battery 22 can be avoided to extend the life. It has the effect of becoming

The invention according to claim 18 is the current limiting circuit 10 according to claim 17, wherein the first MOSFET
TM1 is a p-channel MOSFET having a circuit configuration in which the gate and the drain are connected to each other, the second current source Q3 is connected to the gate of the second MOSFET M2, and the source is connected to the input voltage Vi. The input voltage Vi applied to the transistor Q1 is monitored and activated during a low input voltage period in which the monitored input voltage Vi is equal to or higher than the gate threshold, and the activated input voltage Vi is applied to the gate of the second MOSFET M2. Transmitting the second MOS
The FET M2 is a p-channel MOSFET with a gate connected to the drain of the first MOSFET M1, a source connected to the output voltage Voutut, and a drain connected in parallel to the third current source Q4 and the gate of the third MOSFET M3. The input voltage Vi from the first MOSFET M1 is activated during a low input voltage period in which the input voltage Vi is equal to or higher than a gate threshold, and transmits the output voltage Voutut transmitted from the first MOSFET M1 to the gate of the third MOSFET M3. n-channel MO
An SFET whose gate is the second MOSFET M2
Connected to the base of the control transistor Q1, and activated in accordance with the degree of activation of the second MOSFET M2.
3 is a current limiting circuit 10.

According to the eighteenth aspect of the invention, in addition to the effect of the seventeenth aspect, the collector-emitter potential difference VCE of the control transistor Q1 is reduced during the low input voltage period in which the collector-emitter potential difference VCE is small. Even when the voltage has become low, the first MOSFET M1 monitors the input voltage Vi applied to the control transistor Q1, and the input voltage Vi from the first MOSFET M1 becomes the second MOSFET.
The second MOSFET M2 transmits the output voltage Voutut transmitted from the first MOSFET M1 to the gate of the third MOSFET M3 during the low input voltage period which is equal to or higher than the gate threshold Vthp2 of TM2, and the fourth MOSFET M4 described below limits the base current IB of the control transistor Q1. Therefore, a sufficient load current can be supplied to the load 24 by continuously avoiding a decrease in the DC current amplification factor hFE of the control transistor Q1 which contributes to a decrease in the base current IB within the low input voltage period. It has the effect of becoming.

Further, as described above, the decrease in the DC current gain hFE of the control transistor Q1 caused by the collector-emitter potential difference VCE can be continuously avoided during the low input voltage period, so that the load current supply It is possible to continuously prevent the performance from being lowered during the low input voltage period, and to use the control transistor Q1 without using the conventional compensation control for increasing the base current IB of the control transistor Q1.
Of the base current IB can be continuously avoided within the low input voltage period. As a result, an increase in power consumption during circuit operation due to the occurrence of the base increase current in the base current IB can be continuously avoided within the low input voltage period, and the current consumption of the power supply caused by the base increase current can be reduced. The effect of this is that the increase in can be continuously avoided within the low input voltage period. In particular, when the battery 22 is used as a power supply, an increase in current consumption due to the base increase current is continuously avoided within the low input voltage period, and unnecessary consumption of the battery 22 can be avoided to extend the life. It has the effect of becoming

According to a nineteenth aspect of the present invention, in the current limiting circuit 10 according to the eighteenth aspect, the second MOSFE
TM2 is back-biased and p-channel MOSF
The current limiting circuit 10 has a circuit configuration in which the back gate of ET is biased to the input voltage Vi.

According to the nineteenth aspect, in addition to the effect of the eighteenth aspect, by biasing the back gate of the second MOSFET M2 to the input voltage Vi,
The possibility that external noise is superimposed on the gate threshold value Vthp2 of the second MOSFET M2 can be reduced, and the phenomenon that the second MOSFET M2 is erroneously activated due to external noise can be avoided. As a result, the first MOSF
The low input voltage period in which the input voltage Vi from the ETM1 is equal to or higher than the gate threshold value Vthp2 of the second MOSFET M2 is accurately identified without being affected by external noise, activated, and the output voltage Voutut transmitted from the first MOSFET M1 is converted into the external noise. 3rd MOSFE without being affected by
This has the effect of enabling transmission to the TM3 gate.

According to a twentieth aspect of the present invention, in the voltage regulator using the current limiting circuit according to any one of the first to nineteenth aspects, the output voltage Voutut supplied to the load is kept constant. In the voltage regulator 20, which is a constant voltage power supply, when a current is given, an output voltage Voutut according to the magnitude of the current is given.
, And a control current is applied to the output voltage setting resistors R1 and R2 to supply the output node voltage Vfb and load 24 of the output voltage setting resistors R1 and R2. The control transistor Q1 for controlling the supplied output voltage Voutut to a constant voltage value, the current limiting circuit 10 for limiting a base current IB of the control transistor Q1, and a reference voltage Vref using a first current source Q2. , A voltage difference between a reference voltage Vref from the reference power supply 21 and the output node voltage, and an error signal based on the voltage difference is generated, and the error signal is generated by the control transistor Q1. And an error amplifier Q5 having a feedback loop for promoting constant voltage control for maintaining the output voltage Voutut supplied to the load 24 constant. A regulator 20.

According to the twentieth aspect of the present invention, in addition to the effect of any one of the first to nineteenth aspects, a low input voltage period in which the collector-emitter potential difference VCE is equal to or lower than a predetermined voltage. Inside the control transistor Q
1 is continuously avoided from decreasing the collector-emitter potential difference VCE, and the decrease in the DC current amplification factor hFE of the control transistor Q1 caused by the collector-emitter potential difference VCE is reduced during the low input voltage period. Thus, there is an effect that a sufficient load current can be supplied to the load 24 by avoiding the load continuously.

Further, as described above, the decrease in the DC current gain hFE of the control transistor Q1 caused by the collector-emitter potential difference VCE can be continuously avoided within the low input voltage period. It is possible to continuously prevent the performance from being lowered during the low input voltage period, and to use the control transistor Q1 without using the conventional compensation control for increasing the base current IB of the control transistor Q1.
Of the base current IB can be continuously avoided within the low input voltage period. As a result, an increase in power consumption during circuit operation due to the occurrence of the base increase current in the base current IB can be continuously avoided within the low input voltage period, and the current consumption of the power supply caused by the base increase current can be reduced. The effect of this is that the increase in can be continuously avoided within the low input voltage period. In particular, when the battery 22 is used as a power supply, an increase in current consumption due to the base increase current is continuously avoided within the low input voltage period, and unnecessary consumption of the battery 22 can be avoided to extend the life. It has the effect of becoming

The invention according to claim 21 is the voltage regulator 20 according to claim 20, wherein the error signal output from the error amplifier Q5 or the third
A control signal output from MOSFET M3 for limiting the base current IB is selectively applied to the control transistor Q3.
A voltage regulator 20 having a fourth MOSFET M4 for transmitting to the base of the first.

According to the twenty-first aspect of the present invention, in addition to the effect of the twentieth aspect, even in a low input voltage period in which the collector-emitter potential difference VCE is equal to or less than a predetermined voltage, The control transistor Q3 is controlled based on a control signal output from the MOSFET M3 to continuously prevent the potential difference VCE between the collector and the emitter of the control transistor Q1 from being reduced, and the control transistor generated due to the potential difference VCE between the collector and the emitter. There is an effect that a sufficient load current can be supplied to the load 24 by continuously avoiding a decrease in the DC current amplification factor hFE of Q1 during the low input voltage period.

Further, as described above, the decrease in the DC current amplification factor hFE of the control transistor Q1 caused by the collector-emitter potential difference VCE is controlled based on the control signal output from the third MOSFET M3 to reduce the low input voltage. As a result, the reduction of the load current supply capability can be continuously avoided during the low input voltage period, and the occurrence of the base current increase phenomenon in the base current IB of the control transistor Q1 can be prevented. Control based on the control signal output from the three MOSFET M3 enables continuous avoidance during a low input voltage period. As a result, an increase in power consumption during circuit operation due to the occurrence of the base increase current in the base current IB can be continuously avoided within the low input voltage period, and the current consumption of the power supply caused by the base increase current can be reduced. The effect of this is that the increase in can be continuously avoided within the low input voltage period. In particular, when the battery 22 is used as a power supply, an increase in current consumption due to the base increase current is continuously avoided within the low input voltage period, and unnecessary consumption of the battery 22 can be avoided to extend the life. It has the effect of becoming

The invention according to claim 22 is the voltage regulator 20 according to claim 21, wherein the fourth
The MOSFET M4 is an n-channel MOSFET, and outputs the error signal from the error amplifier Q5 and the third signal.
The voltage regulator 20 has a gate connected to the control signal from the drain of the MOSFET M3 and a drain connected to the base of the control transistor Q1.

According to the invention described in claim 22, in addition to the effect described in claim 21, even in a low input voltage period in which the collector-emitter potential difference VCE is equal to or lower than a predetermined voltage, By controlling the base current IB of the control transistor Q1 based on the control signal transmitted from the 4MOSFET M4, the potential difference VCE between the collector and the emitter of the control transistor Q1 is continuously prevented from being reduced, and the There is an effect that a sufficient load current can be supplied to the load 24 by continuously avoiding a decrease in the DC current amplification factor hFE of the control transistor Q1 caused by the potential difference VCE within the low input voltage period.

Further, as described above, the control transistor Q1 is controlled based on the control signal transmitted from the fourth MOSFET M4.
By controlling the base current IB of the collector,
A reduction in the DC current gain hFE of the control transistor Q1 caused by the potential difference VCE between the emitters can be continuously avoided during the low input voltage period. As a result, the reduction of the load current supply capability continues during the low input voltage period. By controlling the base current IB of the control transistor Q1 based on the control signal transmitted from the fourth MOSFET M4, the base current IB of the control transistor Q1 can be avoided.
Can be continuously avoided within the low input voltage period. As a result, an increase in power consumption during circuit operation due to the occurrence of the base increase current in the base current IB can be continuously avoided within the low input voltage period, and the current consumption of the power supply caused by the base increase current can be reduced. The effect of this is that the increase in can be continuously avoided within the low input voltage period. In particular, when the battery 22 is used as a power supply, an increase in current consumption due to the base increase current is continuously avoided within the low input voltage period, and unnecessary consumption of the battery 22 can be avoided to extend the life. It has the effect of becoming

The invention according to claim 23 is the voltage regulator 20 according to claim 22, wherein the fourth
The MOSFET M4 is connected to the third MOS transistor during the low input voltage period.
The control signal output from the FET M3 is selected and transmitted to the control transistor Q1 to promote the control of limiting the base current IB in the control transistor Q1, and the error from the error amplifier Q5 is excluded except during the low input voltage period. A voltage regulator 20 having a circuit configuration for selecting a signal, transmitting the selected signal to the control transistor Q1, and promoting the constant voltage control in the control transistor Q1.

According to the twenty-third aspect, the same effect as that of the twenty-second aspect can be obtained.

[0069]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, an embodiment of a current limiting circuit according to the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram for explaining one embodiment of the current limiting circuit 10 of the present invention. FIG. 5 is a diagram for explaining the relationship between the voltage between the collector and the emitter of the control transistor Q1 and the DC current gain hFE,
FIG. 5A is a circuit diagram for explaining the connection between the input voltage Vdd and the output voltage Voutut of the control transistor Q1, and FIG. 5B is a circuit diagram showing the direct current in the control transistor Q1 of FIG. 5 is a graph for explaining the dependence of the current amplification factor hFE on the collector-emitter potential difference VCE (Vdd-Vout).

The current limiting circuit 10 shown in FIG. 1 has a control transistor Q for controlling the amount of load current supplied to the load.
A semiconductor device having a function of limiting a base increase current in one base current IB, wherein a potential difference VCE between a collector and an emitter of a control transistor Q1 is obtained by using a potential difference between an input voltage Vi and an output voltage Vout (FIG. 5A). For controlling the base increase current (see 5 (a)) flowing through the base B of the control transistor Q1 at a low input voltage when the collector-emitter potential difference VCE of the control transistor Q1 becomes equal to or less than a predetermined voltage. The circuit is the first MOSF
ETM1, second MOSFET M2, third MOSFET M
3 is characterized in that it is constructed using Hereinafter, the description will be continued on the assumption that a pnp bipolar transistor is used as the control transistor Q1.

In such a circuit configuration, the current limiting circuit 10 monitors the potential difference (Vdd-Vout) between the input voltage Vdd and the output voltage Voutut as described later, and
By controlling the gate potential of SFET M4, the base increase current in base current IB is limited.

In other words, as shown in FIG. 5A, the emitter of the control transistor Q1 is connected to the input voltage Vdd via the voltage input terminal T1, and the collector is connected to the output voltage Voutut.
When the load current is supplied to the load 24 by being connected to the voltage output terminal T2 which outputs the output voltage Vout, the current limiter 10 monitors the potential difference between the input voltage Vdd and the output voltage Voutut to 5 (b).
This limits the decrease in the DC current gain hFE (= IC / IB) as shown in FIG.

The first MOSFET M1 monitors the input voltage Vi applied to the emitter E of the control transistor Q1,
The input voltage Vi being monitored is activated during a low input voltage period equal to or higher than a predetermined threshold voltage, and the voltage (= Vg1) applied to the gate G at the time of the activation is set as the input voltage Vi and the second MOSFET M2 in the next stage is activated. To the gate G.

The gate potential Vg1 of the first MOSFET M1 is given by the following equation (1).

(Equation 1) Here, Vthp1 = gate threshold value of the first MOSFET M1.

More specifically, as shown in FIG. 1, the first MOSFET M1 is a p-channel MOSFET, and has a second current source Q3 and a second current source Q3 for supplying a constant current Iref2 with the gate G and the drain D connected. It has a circuit configuration in which it is connected to the gate G of the 2MOSFET M2 and the source S is connected to the input voltage Vi.

In such a circuit configuration, the input voltage V
If i is greater than the output voltage Vout (VI> VO), the first
Since the gate potential Vg1 of the MOSFET M1 is given by the above equation (1), the second MOSFET M2 and the third MOSFET
OSFET M3 becomes inactive.

The second MOSFET M2 is connected to the first MO of the preceding stage.
The SFET M1 is activated according to the degree of activation (= Vg1) to detect the output voltage Vout, and the detected output voltage Vout
Is transmitted to the gate G of the third MOSFET M3 at the next stage.

The gate potential Vg2 of the second MOSFET M2 is given by the following equation (2).

(Equation 2) Here, Vthp2 = gate threshold value of the second MOSFET M2.

More specifically, the second MOSFET M2 is a p-channel MOSFET, as shown in FIG. 1, in which the gate G is connected to the drain D of the first MOSFET M1, the source S is connected to the output voltage Vout, and the drain D
Supplies the constant current Iref3 with the third current source Q4 and the third MO.
It has a circuit configuration connected in parallel to the gate G of the SFET M3.

In such a circuit configuration, the input voltage V
If i is not different from the output voltage Vout (VI ≒ VO), the first M
Since the gate potential Vg2 (= Vg1) of the OSFET M1 is given by the above equation (2), the second MOSFET M2 is activated. In response, the gate potential of the third MOSFET M3 is raised to near the output voltage Vout, and the third MOSFET M3 is raised.
OSFET M3 is also activated.

Further, the second MOSFET M2 is back-biased, so that the back gate of the p-channel MOSFET is biased to the input voltage Vi.

First MOSFET M1 and Second MOSFET
Since the second MOSFET M2 and M2 are back-biased, the second MOSFET M2 is activated when the output voltage Voutut is equal to the back bias potential VBS and the input voltage is low.

As described above, by biasing the back gate of the second MOSFET M2 to the input voltage Vi,
The possibility that external noise is superimposed on the gate threshold value Vthp2 of the MOSFET M2 can be reduced, and the phenomenon that the second MOSFET M2 is erroneously activated due to the external noise can be avoided. As a result, the first MOSFET
A low input voltage period in which the input voltage Vi from M1 is equal to or higher than the gate threshold value Vthp2 of the second MOSFET M2 is accurately identified and activated without being affected by external noise, and is activated.
The output voltage Vout transmitted from the OSFET M1 can be accurately adjusted without being affected by external noise.
To the gate G.

The third MOSFET M3 is connected to the second MO
It has a circuit configuration that is deactivated according to the degree of activation (= Vg2) of the SFET M2 and limits the base increase current in the base current IB of the control transistor Q1.

More specifically, the third MOSFET M3 has n
A channel MOSFET wherein the gate G is a second MOS
It has a circuit configuration in which the drain D connected to the drain D of the FET M2 and outputting the output voltage Vout is connected to the base B of the control transistor Q1.

In such a circuit configuration, the input voltage V
When i is higher than the output voltage Vout (VI> VO), as described above, the third MOSFET M3 becomes inactive according to the gate potential Vg1 of the first MOSFET M1.

On the other hand, when the input voltage Vi does not differ from the output voltage Vout (VI ≒ VO), as described above, the first MOSF
Second MO activated by gate potential Vg2 of ETM1
The third MOSFET M3 is also activated according to the SFET M2.

That is, the base of the control transistor Q1 of the voltage regulator 20 described later is connected to the third MOSF
By connecting to the drain of ETM3, when the input voltage Vdd (= VI) of the voltage regulator 20 is not different from the output voltage Voutut (= VO) (Vdd ≒ Vout), the collector-emitter potential difference VC of the control transistor Q1 is obtained.
When E becomes close to zero V, the base increase current in the base current IB of the control transistor Q1 is limited by the third MO.
This can be performed using the SFET M3.

The current limiting circuit 10 having such a circuit configuration monitors the potential difference VCE (Vdd-Vout) between the collector and the emitter of the control transistor Q1, and monitors the collector-emitter potential.
During a low input voltage period in which the potential difference VCE (Vdd-Vout) between the emitters is almost zero, the control transistor Q
The occurrence of a base current increase phenomenon occurring in one base B can be continuously restricted.

More specifically, the emitter of the control transistor Q1 is connected to the input voltage Vdd via the voltage input terminal T1, and the collector is connected to the voltage output terminal T2 for outputting the output voltage Voutut to supply the load current to the load 24. Then, the potential difference between the input voltage Vdd and the output voltage Voutut is monitored to limit the occurrence of the base current increase phenomenon.

As a result, even at a low input voltage when Vdd ≒ Vout, the increase in power consumption during circuit operation due to the generation of the base increase current in the base current IB is continuously reduced within the low input voltage period. As a result, an increase in the current consumption burden of the power supply caused by the base increase current can be continuously avoided within the low input voltage period. In particular, when the battery 22 is used as a power supply, an increase in current consumption due to the base increase current is continuously avoided within the low input voltage period, and unnecessary consumption of the battery 22 can be avoided to extend the life. It has the effect of becoming

As described above, according to the current limiting circuit 10, the collector-emitter potential of the control transistor Q1 can be reduced during the low input voltage period in which the collector-emitter potential difference VCE is small.
Even when the emitter-to-emitter potential difference VCE becomes low, the first MOSFET M1 monitors the input voltage Vi applied to the control transistor Q1, and the input voltage Vi from the first MOSFET M1 becomes the gate threshold V of the second MOSFET M2.
During the low input voltage period equal to or greater than thp2, the second MOSFET M2
Transmits the output voltage Vout transmitted from the first MOSFET M1 to the gate G of the third MOSFET M3,
Since the FET M4 limits the base current IB of the control transistor Q1, the decrease in the DC current gain hFE of the control transistor Q1, which contributes to the decrease in the base current IB, is continuously avoided during the low input voltage period. Thus, a sufficient load current can be supplied to the load 24.

Further, as described above, it is possible to continuously avoid a decrease in the DC current gain hFE of the control transistor Q1 caused by the collector-emitter potential difference VCE within the low input voltage period. It is possible to continuously prevent the performance from being lowered during the low input voltage period, and to use the control transistor Q1 without using the conventional compensation control for increasing the base current IB of the control transistor Q1.
Of the base current IB can be continuously avoided within the low input voltage period.

Next, an embodiment of a voltage regulator according to the present invention will be described with reference to the drawings.

FIG. 2 is a circuit diagram for explaining one embodiment of the voltage regulator 20 of the present invention. FIG.
5 is a graph for explaining input / output characteristics of the voltage regulator 20 of FIG.

As described above, the current limiting circuit 10 shown in FIG. 2 operates in a constant voltage state (Vout shown in FIG. 6) from the ground terminal T3 to the voltage output terminal T2 connected to the ground potential GND.
= The constant-voltage control region of 3.000 V), the collector-emitter potential difference VCE of the control transistor Q1 for controlling the load current supplied (that is, the input voltage Vdd and the output voltage V
The potential difference from outut = Vdd-Vout) is monitored, and the collector-emitter potential difference VCE is equal to or less than a predetermined voltage (specifically,
The input voltage Vdd below the point P shown in FIG. 6 (especially, near the same potential) is within the low input voltage period (0 V to 0 V shown in FIG. 6).
At a point P (within the range of the input voltage Vdd corresponding to Vthp2> Vthp1), the base current IB flowing through the control transistor Q1 is continuously limited via the fourth MOSFET M4 during the low input voltage period.

The fourth MOSFET M4 shown in FIG. 2 selectively controls an error signal output from an error amplifier Q5 to be described later or a control signal for limiting the base increase current in the base current IB output from the third MOSFET M3. It is connected to transmit to the base B of Q1.

As shown in FIG. 3, a specific fourth MOSFET M4 is an n-channel MOSFET, and an error signal from an error amplifier Q5, which will be described later, and a third MOSFET M3.
And the control signal from the drain D is commonly connected to the gate G, and the drain D is connected to the base B of the control transistor Q1.

The fourth MOSF having such a circuit configuration
ETM4, as shown in FIG.
The control signal output from the MOSFET M3 is selected and transmitted to the control transistor Q1 to instruct the control of limiting the base increase current in the base current IB of the control transistor Q1, and to output the error signal from the error amplifier Q5 except during the low input voltage period. The voltage is selected and transmitted to the control transistor Q1, thereby instructing constant voltage control (voltage regulation) in the control transistor Q1.

By providing such a fourth MOSFET M4, the collector-emitter potential difference VCE (Vdd
−Vout), a reduction in the DC current gain hFE of the control transistor Q1 caused by the control transistor Q1 can be continuously avoided during the low input voltage period, so that a sufficient load current can be supplied to the load 24. .

Further, as described above, it is possible to continuously avoid the decrease in the DC current gain hFE of the control transistor Q1 caused by the collector-emitter potential difference VCE during the low input voltage period. It is possible to continuously prevent the performance from being lowered during the low input voltage period, and to use the control transistor Q1 without using the conventional compensation control for increasing the base current IB of the control transistor Q1.
Of the base current IB can be continuously avoided within the low input voltage period.

FIG. 3 is a circuit diagram in which the current limiting circuit 10 of FIG. 1 is applied to the voltage regulator 20 of FIG.

The voltage regulator 20 shown in FIG.
Is an output voltage Voutu supplied to a load 24 such as a mobile phone.
a constant-voltage power supply for maintaining t constant; output voltage setting resistor networks R1, R2, control transistor Q1, current limiting circuit 10, reference power supply 21, error amplifier Q5,
The fourth MOSFET M4 is mainly configured.

The output voltage setting resistor networks R 1 and R 2 are provided with an output voltage Voutut according to the magnitude of the current when the current is applied.
Is a circuit element that generates.

The control transistor Q1 supplies a control current to the output voltage setting resistance networks R1 and R2 to output the output nodes of the output voltage setting resistance networks R1 and R2 (the output voltage setting resistors R1 and R2).
It is a pnp transistor for controlling the voltage Vfb of the connection point (1 and the output voltage setting resistor R2) and the output voltage Voutut supplied to the load 24 to a constant voltage value.

As described above, the current limiting circuit 10 is a circuit for limiting the base increase current in the base current IB of the control transistor Q1.

The reference power supply 21 is a circuit that generates a reference voltage Vref based on the constant current Iref1 supplied from the first current source Q2.

The error amplifier Q5 is an operational amplifier,
By detecting a voltage difference between the reference voltage Vref input to the non-inverting input terminal from the reference power supply 21 and the output node voltage Vfb and generating an error signal based on the voltage difference, the error signal is fed back to the control transistor Q1. This is a circuit for instructing constant voltage control to keep the output voltage Voutut supplied to the load 24 constant. Such an error amplifier Q5
Has a feedback loop for inputting the output node voltage Vfb to the inverting input terminal.

As described above, the fourth MOSFET M4 outputs the error signal output from the error amplifier Q5 or the third MOSFET M4.
An n-channel MO for selectively transmitting a control signal for limiting the base increase current in the base current IB output from MOSFET M3 to base B of control transistor Q1
SFET.

Specifically, the fourth MOSFET M4 is the same as that shown in FIG.
As shown in the figure, the error signal from the error amplifier Q5 and the third M
The control signal from the drain D of the OSFET M3 is commonly connected to the gate G, and the drain D is connected to the base B of the control transistor Q1.

The fourth MOSF having such a circuit configuration
The ETM4 selects a control signal output from the third MOSFET M3 during the low input voltage period, transmits the control signal to the control transistor Q1, and instructs the control transistor Q1 to control the base increase current in the base current IB of the control transistor Q1, except for the low input voltage period The error signal from the error amplifier Q5 can be selected and transmitted to the control transistor Q1 to instruct the control transistor Q1 to perform constant voltage control.

Thus, even during the low input voltage period in which the collector-emitter potential difference VCE (Vdd-Vout) is substantially zero, the control transistor Q1 is controlled based on the control signal transmitted from the fourth MOSFET M4.
Of the control transistor Q1 by controlling the base current IB of the control transistor Q1.
Vout) is continuously reduced, and the decrease in the DC current gain hFE of the control transistor Q1 caused by the collector-emitter potential difference VCE (Vdd-Vout) is reduced within the low input voltage period. There is an effect that a sufficient load current can be supplied to the load 24 by avoiding the load continuously.

Further, as described above, the control transistor Q1 is controlled based on the control signal transmitted from the fourth MOSFET M4.
By controlling the base current IB of the collector,
A decrease in the DC current amplification factor hFE of the control transistor Q1 caused by the potential difference VCE (Vdd-Vout) between the emitters can be continuously avoided during the low input voltage period. The control transistor Q1 is controlled by controlling the base current IB of the control transistor Q1 based on the control signal transmitted from the fourth MOSFET M4.
Of the base current IB can be continuously avoided within the low input voltage period. As a result, an increase in power consumption during circuit operation due to the occurrence of the base increase current in the base current IB can be continuously avoided within the low input voltage period, and the current consumption of the power supply caused by the base increase current can be reduced. The effect of this is that the increase in can be continuously avoided within the low input voltage period. In particular, when the battery 22 is used as a power supply, an increase in current consumption due to the base increase current is continuously avoided within the low input voltage period, and unnecessary consumption of the battery 22 can be avoided to extend the life. It has the effect of becoming

In the circuit configuration shown in FIG. 3, the current limiting circuit 10 monitors the potential difference (Vdd-Vout) between the input voltage Vdd and the output voltage Voutut and controls the gate potential of the fourth MOSFET M4 to reduce the base current IB. Will be limited.

In other words, the emitter of the control transistor Q 1 is connected to the input voltage Vdd via the voltage input terminal T 1, and the collector is connected to the voltage output terminal T 2 for outputting the output voltage Voutut to supply the load current to the load 24. In this case, the current limiting circuit 10 outputs the input voltage Vdd and the output voltage Vou
The potential difference from tut is monitored to limit the decrease in the DC current gain hFE.

The current limiting circuit 10 is provided with a collector-emitter potential difference VCE (Vdd-Vo) of the control transistor Q1.
ut), and even at a low input voltage when Vdd 入 力 Vout, the collector-emitter potential difference VCE (Vdd-Vou) of the base increasing current tower W1 Q1 in the base current IB.
It is also possible to limit the decrease in the DC current gain hFE caused by the decrease in t).

As a result, even at the time of a low input voltage where Vdd 低下 Vout, the decrease of the DC current amplification factor hFE is limited to prevent the base current increase phenomenon from occurring in the base current IB at an arbitrary timing during the low input voltage. Can be avoided. As a result, an increase in power consumption during circuit operation due to the occurrence of the base increase current in the base current IB can be avoided at an arbitrary timing when the input voltage is low,
It is possible to prevent an increase in the current consumption burden of the power supply caused by the base increase current at an arbitrary timing at a low input voltage. In particular, when the battery 22 is used as a power source, an increase in current consumption due to the base increase current can be avoided at an arbitrary timing at a low input voltage, and unnecessary life of the battery 22 can be avoided to extend the life. It has the effect of becoming

The current limiting circuit 10 is provided with a collector-emitter potential difference VCE (Vdd-Vo) of the control transistor Q1.
ut) and monitor the collector-emitter potential difference VCE (V
(dd-Vout) is substantially zero in the low input voltage period (within the input voltage Vdd corresponding to the point P (Vthp2> Vthp1) shown in FIG. 6).
Collector-emitter potential difference VCE (Vdd-Vout)
Of the DC current amplification factor hFE, which is caused by the decrease of the DC current amplification factor, is continuously limited.

In this case, in the current limiting circuit 10, the emitter of the control transistor Q1 is connected to the input voltage Vdd via the voltage input terminal T1, and the collector is connected to the voltage output terminal T2 for outputting the output voltage Voutut, thereby controlling the load current. Load 2
4 to monitor the potential difference between the input voltage Vdd and the output voltage Voutut to limit the decrease in the DC current gain hFE.

As a result, even during the low input voltage period in which the potential difference VCE (Vdd-Vout) between the collector and the emitter is substantially zero, the potential difference VCE (Vdd-Vout) between the collector and the emitter of the control transistor Q1 is obtained. Continually avoiding the low
A sufficient load current can be supplied to the load 24 by continuously avoiding a decrease in the DC current amplification factor hFE of the control transistor Q1 caused by the emitter-to-emitter potential difference VCE (Vdd-Vout) within the low input voltage period. It has the effect of becoming

Further, as described above, the decrease in the DC current gain hFE of the control transistor Q1 caused by the collector-emitter potential difference VCE (Vdd-Vout) can be continuously avoided within the low input voltage period. In addition, it is possible to continuously prevent a decrease in the load current supply capability within the low input voltage period, and to use the control transistor Q1 without using the conventional compensation control that increases the base current IB of the control transistor Q1. The occurrence of the base current increase phenomenon in the base current IB can be continuously avoided within the low input voltage period. As a result, an increase in power consumption during circuit operation due to the occurrence of the base increase current in the base current IB can be continuously avoided within the low input voltage period, and the current consumption of the power supply caused by the base increase current can be reduced. The effect of this is that the increase in can be continuously avoided within the low input voltage period. In particular, battery 2
When the battery 2 is used, an increase in current consumption due to the base increase current is continuously avoided within the low input voltage period, so that useless consumption of the battery 22 can be avoided and a long life can be achieved. To play.

The current limiting circuit 10 is provided with a collector-emitter potential difference VCE (Vdd-Vo) of the control transistor Q1.
ut) and monitor the collector-emitter potential difference VCE (V
(dd-Vout) is substantially zero in the low input voltage period (within the input voltage Vdd corresponding to the point P (Vthp2> Vthp1) shown in FIG. 6).
Collector-emitter potential difference VCE (Vdd-Vout)
Can be maintained at a certain level or more so that a base current of a certain level or more can be continuously obtained.

As a result, even during the low input voltage period in which the potential difference VCE (Vdd-Vout) between the collector and the emitter is almost zero, the potential difference VCE (Vdd-Vout) between the collector and the emitter can be maintained at a certain level or more. The DC current gain hFE of the control transistor Q1 is continuously avoided during the low input voltage period by maintaining the base current at a certain value or more so that the base current can be secured, and the DC current gain hFE is caused by the reduced DC current gain hFE. The occurrence of the base current increase phenomenon in the base current IB can be continuously avoided within the low input voltage period. As a result, an increase in power consumption during circuit operation due to the occurrence of the base increase current in the base current IB can be continuously avoided within the low input voltage period, and the current consumption of the power supply caused by the base increase current can be reduced. The effect of this is that the increase in can be continuously avoided within the low input voltage period. In particular, when the battery 22 is used as a power supply, an increase in current consumption due to the base increase current is continuously avoided within the low input voltage period, and unnecessary consumption of the battery 22 can be avoided to extend the life. It has the effect of becoming

It is apparent that the voltage regulator 20 having such a current limiting circuit 10 can be realized by a MOS integrated circuit. Further, the integrated voltage regulator 20 can be formed in a package form (a so-called battery pack) together with the battery 22. In such a battery pack, it is desirable to incorporate a charge control circuit.

FIG. 4 shows the voltage regulator 2 of FIG.
It is a block diagram for demonstrating the usage pattern of 0.

As shown in FIG. 4, the control transistor Q1 has an emitter connected to an input voltage Vdd applied from an externally connected battery 22 via a voltage input terminal T1, and a collector for outputting an output voltage Voutut. The load current Ic is supplied to the load 24 while being connected to the load 24 via the output terminal T2.

FIG. 7A is a graph for explaining the output characteristics of the voltage regulator 20 when the current limiting circuit 10 of FIG. 1 is not used, and FIG. 7B is a graph for explaining the current limiting circuit of FIG. When the control transistor Q is not used,
5 is a graph for explaining a base increase current generated in one base B. FIG. 8A shows the current limiting circuit 1 of FIG.
FIG. 8B is a graph for explaining output characteristics of the voltage regulator 20 when 0 is used, and FIG.
When the current limiting circuit 10 of FIG.
6 is a graph for explaining a limited base increase current in one base B.

In such a circuit configuration, in the voltage regulator 20, the input voltage Vdd is changed to the output voltage Voutut.
(Specifically, 3.000 V) (Vdd
> Vout, shaded area shown in FIG. 6), first MOSFET M1
Is given by the above equation (1), the second MOSFET M2 and the third MOSFET M3 become inactive.

The second MOSFET M2 is connected to the first MO of the preceding stage.
The output voltage Voutut (FIG. 7A or FIG. 8A) is activated in accordance with the degree of activation (= Vg1) of the SFET M1.
) Is detected, and the detected output voltage Voutut is transmitted to the gate G of the third MOSFET M3 at the next stage.

First MOSFET M1 and Second MOSFET
Since the second MOSFET M2 and M2 are back-biased, the second MOSFET M2 is activated when the output voltage Voutut is equal to the back bias potential VBS and the input voltage is low.

In the voltage regulator 20, the input voltage Vdd becomes equal to or lower than the output voltage Voutut.
When the gate threshold Vthp2 of TM2> the gate threshold Vthp1 of the first MOSFET M1 (Vdd ≦ Vout, 0 in FIG. 6)
V to the point P (within the range of the input voltage Vdd corresponding to Vthp2> Vthp1), and especially the input voltage Vdd is the output voltage Voutut.
When there is no difference from the first MOSFET (Vdd ≒ Vout), the first MOSFET M1
Since the gate potential Vg2 (= Vg1) is given by the above equation (2), the second MOSFET M2 is activated and the third MOSFET M3 is also activated.

As described above, by biasing the back gate of the second MOSFET M2 to the input voltage Vdd,
The possibility that external noise is superimposed on the gate threshold value Vthp2 of the MOSFET M2 can be reduced, and the phenomenon that the second MOSFET M2 is erroneously activated due to the external noise can be avoided. As a result, the first MOSFET
The low input voltage period in which the input voltage Vdd from M1 is equal to or higher than the gate threshold value Vthp2 of the second MOSFET M2 is accurately identified and activated without being affected by external noise, and is activated.
The output voltage Voutut transmitted from the OSFET M1 can be accurately adjusted without being affected by external noise.
The third gate G can be transmitted.

The input voltage Vdd of the third MOSFET M3 becomes equal to or lower than the output voltage Voutut, and the gate threshold Vthp2 of the second MOSFET M2> the gate threshold Vthp of the first MOSFET M1.
1 (Vdd ≦ Vout, 0V to point P (V
thp2> Vthp1), and especially when the input voltage Vdd does not differ from the output voltage Voutut (Vdd） Vout), the degree of activation of the second MOSFET M2 in the preceding stage (= Vg2) It has a circuit configuration that is inactivated accordingly to limit the base increase current in the base current IB of the control transistor Q1.

In such a circuit configuration, the input voltage V
When dd is larger than the output voltage Voutut (Vdd> Vou)
t) As described above, the third MOSFET M3 becomes inactive according to the gate potential Vg1 of the first MOSFET M1.

On the other hand, when the input voltage Vdd becomes equal to or lower than the output voltage Voutut and the gate threshold Vthp2 of the second MOSFET M2> the gate threshold Vthp1 of the first MOSFET M1 (Vd
d ≦ Vout, the input voltage Vdd corresponding to 0V to the point P (Vthp2> Vthp1) shown in FIG. 6 and the input voltage Vdd is not different from the output voltage Voutut (Vdd ≒ Vou)
t) As described above, the third MOSFET M3 is also activated according to the second MOSFET M2 activated by the gate potential Vg2 of the first MOSFET M1.

The fourth MOSFET M4 activated in response to the activation of the third MOSFET M3 receives the control signal output from the third MOSFET M3 from the error signal from the error amplifier Q5 and the control signal output from the third MOSFET M3. The control signal is transmitted to the control transistor Q1 to instruct the control of limiting the base increase current in the base current IB of the control transistor Q1, and the error signal from the error amplifier Q5 and the third MO
An error signal from the error amplifier Q5 is selected from the two control signals output from the SFET M3 and transmitted to the control transistor Q1 to instruct constant voltage control (voltage regulation) in the control transistor Q1.

By providing such a fourth MOSFET M4, the collector-emitter potential difference VCE (Vdd
−Vout), a reduction in the DC current gain hFE of the control transistor Q1 caused by the control transistor Q1 can be continuously avoided during the low input voltage period, so that a sufficient load current can be supplied to the load 24. .

Furthermore, as described above, the decrease in the DC current amplification factor hFE of the control transistor Q1 caused by the collector-emitter potential difference VCE can be continuously avoided within the low input voltage period. It is possible to continuously prevent the deterioration of the performance within the low input voltage period, and to use the base of the control transistor Q1 without using the conventional compensation control for increasing the base increase current in the base current IB of the control transistor Q1. The occurrence of the base current increase phenomenon in the base increase current in the current IB can be continuously avoided within the low input voltage period.

That is, the base of the control transistor Q1 of the voltage regulator 20 described later is connected to the third MOSF
By connecting to the drain of ETM3, when the input voltage Vdd (= Vdd) of the voltage regulator 20 does not differ from the output voltage Voutut (= Vout) (Vdd ≒ Vout), the potential difference VCE between the collector and the emitter of the control transistor Q1 is reduced. When the voltage approaches zero V, as shown in FIG. 8B, the base increase current in the base current IB of the control transistor Q1 can be limited by using the third MOSFET M3.

The current limiting circuit 10 having such a circuit configuration monitors the potential difference VCE (Vdd-Vout) between the collector and the emitter of the control transistor Q1, and monitors the collector-emitter potential.
During a low input voltage period in which the emitter-to-emitter potential difference VCE (Vdd-Vout) is substantially zero (in the range of 0 V to the input voltage Vdd corresponding to the point P (Vthp2> Vthp1) shown in FIG. 6), the control transistor The occurrence of a base current increase phenomenon as shown in FIG. 7B, which occurs in the base B of Q1, can be continuously restricted.

[0142]

According to the first aspect of the present invention, the conventional compensation control for increasing the base current of the control transistor is used even at a low input voltage where the potential difference between the collector and the emitter is small. Therefore, it is possible to avoid the occurrence of the base current increase phenomenon in the base current of the control transistor at an arbitrary timing when the input voltage is low. As a result, an increase in power consumption during circuit operation due to the occurrence of base increase current in the base current can be avoided at an arbitrary timing at a low input voltage, and an increase in the load on the power supply due to base increase current can be avoided. This can be avoided at an arbitrary timing when the input voltage is low. In particular, when a battery is used as a power supply, an increase in current consumption due to an increased base current can be avoided at an arbitrary timing at a low input voltage, and the life of the battery can be extended.

According to the second aspect of the present invention, the potential difference between the collector and the emitter of the control transistor is continuously reduced even during the low input voltage period where the potential difference between the collector and the emitter is small. And a decrease in the DC current amplification factor of the control transistor caused by the potential difference between the collector and the emitter can be continuously avoided within the low input voltage period, so that a sufficient load current can be supplied to the load. .

Further, as described above, the decrease in the DC current amplification factor of the control transistor caused by the potential difference between the collector and the emitter can be continuously avoided within the low input voltage period. The drop can be continuously avoided within the low input voltage period, and the occurrence of the base current increase phenomenon in the base current of the control transistor can be reduced without using the conventional compensation control that increases the base current of the control transistor. This can be avoided continuously during the low input voltage period. As a result, it is possible to continuously avoid an increase in power consumption during the circuit operation due to the occurrence of the base increase current in the base current during the low input voltage period, and to reduce the load on the power supply due to the base increase current. This can be avoided continuously during the low input voltage period.
In particular, when a battery is used as a power supply, an increase in current consumption due to a base increase current is continuously avoided within a low input voltage period, so that the battery life can be extended.

According to the third aspect of the present invention, the first aspect
Or, the same effect as the effect described in 2 can be obtained.

According to the fourth aspect of the present invention, even when the potential difference between the collector and the emitter is small and the input voltage is low, the decrease in the DC current gain of the control transistor can be limited, and the decrease in the DC current gain can be suppressed. Can be avoided at an arbitrary timing at the time of a low input voltage. As a result, an increase in power consumption during circuit operation due to the occurrence of base increase current in the base current can be avoided at an arbitrary timing at a low input voltage, and an increase in the load on the power supply due to base increase current can be avoided. This can be avoided at an arbitrary timing when the input voltage is low. In particular, when a battery is used as a power supply, an increase in current consumption due to an increased base current can be avoided at an arbitrary timing at a low input voltage, and the life of the battery can be extended.

According to the fifth aspect of the present invention, even in the low input voltage period where the potential difference between the collector and the emitter is small, the reduction of the DC current amplification factor of the control transistor is continuously performed in the low input voltage period. And a sufficient load current can be supplied to the load.

Further, as described above, a decrease in the DC current amplification factor of the control transistor caused by the potential difference between the collector and the emitter can be continuously avoided during the low input voltage period. The drop can be continuously avoided within the low input voltage period, and the occurrence of the base current increase phenomenon in the base current of the control transistor can be reduced without using the conventional compensation control that increases the base current of the control transistor. This can be avoided continuously during the low input voltage period. As a result, it is possible to continuously avoid an increase in power consumption during the circuit operation due to the occurrence of the base increase current in the base current during the low input voltage period, and to reduce the load on the power supply due to the base increase current. This can be avoided continuously during the low input voltage period.
In particular, when a battery is used as a power supply, an increase in current consumption due to a base increase current is continuously avoided within a low input voltage period, so that the battery life can be extended.

According to the invention described in claim 6, according to claim 3,
Or, the same effect as the effect described in 4 can be obtained.

According to the seventh aspect of the present invention, even at the time of a low input voltage in which the potential difference between the collector and the emitter has become equal to or less than the predetermined voltage, the decrease in the DC current amplification factor is limited to reduce the base current in the base current. The occurrence of the current increase phenomenon can be avoided at an arbitrary timing when the input voltage is low. As a result, an increase in power consumption during circuit operation due to the occurrence of base increase current in the base current can be avoided at an arbitrary timing at a low input voltage, and an increase in the load on the power supply due to base increase current can be avoided. This can be avoided at an arbitrary timing when the input voltage is low. In particular, when a battery is used as a power supply, an increase in current consumption due to an increased base current can be avoided at an arbitrary timing at a low input voltage, and the life of the battery can be extended.

According to the present invention, the potential difference between the collector and the emitter of the control transistor is reduced even during the low input voltage period in which the potential difference between the collector and the emitter is equal to or lower than the predetermined voltage. To prevent a decrease in the DC current gain of the control transistor caused by the potential difference between the collector and the emitter in the low input voltage period, thereby providing sufficient load current. Can be supplied to

Further, as described above, a decrease in the DC current amplification factor of the control transistor caused by the potential difference between the collector and the emitter can be continuously avoided within the low input voltage period, and as a result, the load current supply capability is reduced. The drop can be continuously avoided within the low input voltage period, and the occurrence of the base current increase phenomenon in the base current of the control transistor can be reduced without using the conventional compensation control that increases the base current of the control transistor. This can be avoided continuously during the low input voltage period. As a result, it is possible to continuously avoid an increase in power consumption during the circuit operation due to the occurrence of the base increase current in the base current during the low input voltage period, and to reduce the load on the power supply due to the base increase current. This can be avoided continuously during the low input voltage period.
In particular, when a battery is used as a power supply, an increase in current consumption due to a base increase current is continuously avoided within a low input voltage period, so that the battery life can be extended.

According to the ninth aspect of the present invention, the seventh aspect is provided.
Or, the same effect as the effect described in 8 can be obtained.

According to the tenth aspect of the present invention, even at the time of a low input voltage in which the potential difference between the collector and the emitter has become equal to or less than the predetermined voltage, the potential difference between the collector and the emitter is maintained and controlled at a certain level or more. Avoid the reduction of the DC current gain of the transistor at any timing at low input voltage,
The base current increase phenomenon in the base current, which is caused by the decrease in the DC current amplification factor, can be avoided at an arbitrary timing when the input voltage is low. As a result, an increase in power consumption during circuit operation due to the occurrence of base increase current in the base current can be avoided at an arbitrary timing at a low input voltage, and an increase in the load on the power supply due to base increase current can be avoided. This can be avoided at an arbitrary timing when the input voltage is low. In particular, when a battery is used as a power supply, an increase in current consumption due to an increased base current can be avoided at an arbitrary timing at a low input voltage, and the life of the battery can be extended.

According to the eleventh aspect of the present invention, the potential difference between the collector and the emitter is maintained at a certain level or more even during the low input voltage period in which the potential difference between the collector and the emitter is equal to or less than the predetermined voltage. The DC current gain of the control transistor is continuously prevented from decreasing during the low input voltage period, and the occurrence of the base current increase phenomenon in the base current caused by the decrease in the DC current amplification factor is prevented during the low input voltage period. It can be avoided continuously within. This allows
Increase in power consumption during circuit operation due to generation of base increase current in base current can be continuously avoided within the low input voltage period, and increase in power supply burden due to base increase current can be reduced at low input voltage. It can be avoided continuously within the period. In particular, when a battery is used as a power supply, an increase in current consumption due to a base increase current is continuously avoided within a low input voltage period, so that the battery life can be extended.

According to the twelfth aspect of the present invention, in addition to the effect of the tenth or eleventh aspect, even when the potential difference between the input voltage and the output voltage is small, the potential difference between the collector and the emitter is reduced. Maintain at a certain level or more to avoid the decrease in the DC current gain of the control transistor continuously during the low input voltage period, and the base current increase phenomenon occurs in the base current caused by the decrease in the DC current gain Can be continuously avoided within the low input voltage period. As a result, it is possible to continuously avoid an increase in power consumption during the circuit operation due to the occurrence of the base increase current in the base current during the low input voltage period, and to reduce the load on the power supply due to the base increase current. This can be avoided continuously during the low input voltage period. In particular, when a battery is used as a power supply, an increase in current consumption due to a base increase current is continuously avoided within a low input voltage period, so that the battery life can be extended.

According to the thirteenth aspect of the present invention, even at a low input voltage when the potential difference between the collector and the emitter becomes equal to or less than a predetermined voltage, a circuit operation caused by the occurrence of the base increase current in the base current can be performed. Increase in power consumption can be avoided at any time when the input voltage is low,
An increase in the load on the power supply due to the base increase current can be avoided at an arbitrary timing when the input voltage is low. In particular, when a battery is used as a power supply, an increase in current consumption due to an increased base current can be avoided at an arbitrary timing at a low input voltage, and the life of the battery can be extended.

According to the fourteenth aspect of the present invention, even at the time of a low input voltage in which the potential difference between the collector and the emitter has become equal to or less than the predetermined voltage, the circuit operation attributable to the generation of the base increase current in the base current can be performed. Can be continuously avoided in the low input voltage period, and the increase in the load on the power supply due to the base increase current can be continuously avoided in the low input voltage period. In particular, when a battery is used as a power supply, an increase in current consumption due to a base increase current is continuously avoided within a low input voltage period, so that the battery life can be extended.

According to the fifteenth aspect, the same effect as the thirteenth or fourteenth aspect can be obtained.

According to the sixteenth aspect, an effect similar to the effect according to any one of the thirteenth to fifteenth aspects is obtained.

According to the seventeenth aspect of the present invention, in addition to the effect of any one of the first to sixteenth aspects, in addition to the effect of the collector transistor of the control transistor within a low input voltage period in which the potential difference between the collector and the emitter is small. -Even if the potential difference between the emitters becomes low, the third MOSFE
Since T limits the base current of the control transistor,
It is possible to supply a sufficient load current to the load by continuously avoiding a decrease in the DC current gain of the control transistor, which contributes to a decrease in the base current, within the low input voltage period.

Furthermore, as described above, the decrease in the DC current amplification factor of the control transistor caused by the potential difference between the collector and the emitter can be continuously avoided within the low input voltage period. The drop can be continuously avoided within the low input voltage period, and the occurrence of the base current increase phenomenon in the base current of the control transistor can be reduced without using the conventional compensation control that increases the base current of the control transistor. This can be avoided continuously during the low input voltage period. As a result, it is possible to continuously avoid an increase in power consumption during the circuit operation due to the occurrence of the base increase current in the base current during the low input voltage period, and to reduce the load on the power supply due to the base increase current. This can be avoided continuously during the low input voltage period.
In particular, when a battery is used as a power supply, an increase in current consumption due to a base increase current is continuously avoided within a low input voltage period, so that the battery life can be extended.

According to the eighteenth aspect of the invention, in addition to the effect of the seventeenth aspect, the potential difference between the collector and the emitter of the control transistor is reduced during the low input voltage period in which the potential difference between the collector and the emitter is small. Even in the case where the first MOSFET monitors the input voltage applied to the control transistor, the first MOSFET monitors the input voltage during the low input voltage period when the input voltage from the first MOSFET is equal to or higher than the gate threshold of the second MOSFET.
Is transmitted to the gate of the third MOSFET, and the third MOSFET limits the base current of the control transistor. A sufficient load current can be supplied to the load by avoiding it continuously during the low input voltage period.

Furthermore, as described above, the decrease in the DC current amplification factor of the control transistor caused by the potential difference between the collector and the emitter can be continuously avoided within the low input voltage period. The drop can be continuously avoided within the low input voltage period, and the occurrence of the base current increase phenomenon in the base current of the control transistor can be reduced without using the conventional compensation control that increases the base current of the control transistor. This can be avoided continuously during the low input voltage period. As a result, it is possible to continuously avoid an increase in power consumption during the circuit operation due to the occurrence of the base increase current in the base current during the low input voltage period, and to reduce the load on the power supply due to the base increase current. This can be avoided continuously during the low input voltage period.
In particular, when a battery is used as a power supply, an increase in current consumption due to a base increase current is continuously avoided within a low input voltage period, so that the battery life can be extended.

According to the nineteenth aspect of the present invention, in addition to the effect of the eighteenth aspect, by biasing the back gate of the second MOSFET to the input voltage,
The possibility that external noise is superimposed on the gate threshold value of the SFET can be reduced, and the second MO can be reduced due to the external noise.
A phenomenon in which the SFET is activated by mistake can be avoided. As a result, a low input voltage period in which the input voltage from the first MOSFET is equal to or higher than the gate threshold of the second MOSFET is accurately identified and activated without being affected by external noise, and the output voltage transmitted from the first MOSFET is externally transmitted. Accurate third MOSF without being affected by noise
It can be transmitted to the ET gate.

According to the twentieth aspect of the present invention, in addition to the effects of the first aspect, in addition to the low input voltage period in which the potential difference between the collector and the emitter is equal to or less than a predetermined voltage. Even within the range, the potential difference between the collector and the emitter of the control transistor is continuously prevented from being reduced, and the decrease in the DC current gain of the control transistor caused by the potential difference between the collector and the emitter is prevented. A sufficient load current can be supplied to the load by avoiding it continuously during the low input voltage period.

Further, as described above, a decrease in the DC current amplification factor of the control transistor caused by the potential difference between the collector and the emitter can be continuously avoided during the low input voltage period. The drop can be continuously avoided within the low input voltage period, and the occurrence of the base current increase phenomenon in the base current of the control transistor can be reduced without using the conventional compensation control that increases the base current of the control transistor. This can be avoided continuously during the low input voltage period. As a result, it is possible to continuously avoid an increase in power consumption during the circuit operation due to the occurrence of the base increase current in the base current during the low input voltage period, and to reduce the load on the power supply due to the base increase current. This can be avoided continuously during the low input voltage period.
In particular, when a battery is used as a power supply, an increase in current consumption due to a base increase current is continuously avoided within a low input voltage period, so that the battery life can be extended.

According to the twenty-first aspect, in addition to the effect of the twentieth aspect, even in a low input voltage period in which the potential difference between the collector and the emitter is equal to or less than a predetermined voltage, Control is performed based on a control signal output from the 3MOSFET to continuously prevent the potential difference between the collector and the emitter of the control transistor from being reduced, and to reduce the potential difference between the control transistor and the control transistor caused by the potential difference between the collector and the emitter. It is possible to supply a sufficient load current to the load while continuously avoiding a decrease in the DC current amplification factor during the low input voltage period.

Further, as described above, the decrease in the DC current amplification factor of the control transistor caused by the potential difference between the collector and the emitter is controlled based on the control signal output from the third MOSFET, so that it can be controlled within the low input voltage period. As a result, the reduction of the load current supply capability can be continuously avoided within the low input voltage period, and the occurrence of the base current increase phenomenon in the base current of the control transistor is output from the third MOSFET. Control based on such a control signal, and can be avoided continuously within the low input voltage period. As a result, it is possible to continuously avoid an increase in power consumption during the circuit operation due to the occurrence of the base increase current in the base current during the low input voltage period, and to reduce the load on the power supply due to the base increase current. This can be avoided continuously during the low input voltage period. In particular, when a battery is used as a power supply, an increase in current consumption due to a base increase current is continuously avoided within a low input voltage period, so that the battery life can be extended.

According to the twenty-second aspect of the present invention, in addition to the effect of the twenty-first aspect, even in a low input voltage period in which the potential difference between the collector and the emitter is equal to or less than a predetermined voltage, By controlling the base current of the control transistor based on the control signal transmitted from the 4MOSFET, the potential difference between the collector and the emitter of the control transistor is continuously avoided from being reduced, and the potential difference between the collector and the emitter is reduced. As a result, a decrease in the DC current amplification factor of the control transistor caused by the control transistor can be continuously avoided within the low input voltage period, and a sufficient load current can be supplied to the load.

Further, by controlling the base current of the control transistor based on the control signal transmitted from the fourth MOSFET in this manner, the DC current amplification factor of the control transistor caused by the potential difference between the collector and the emitter is obtained. Can be continuously avoided during the low input voltage period. As a result, the reduction of the load current supply capability can be continuously avoided during the low input voltage period.
By controlling the base current of the control transistor based on the control signal transmitted from the control transistor, the occurrence of the base current increase phenomenon in the base current of the control transistor can be continuously avoided within the low input voltage period. As a result, it is possible to continuously avoid an increase in power consumption during the circuit operation due to the occurrence of the base increase current in the base current during the low input voltage period, and to reduce the load on the power supply due to the base increase current. This can be avoided continuously during the low input voltage period. In particular, when a battery is used as a power supply, an increase in current consumption due to a base increase current is continuously avoided within a low input voltage period, so that the battery life can be extended.

According to the twenty-third aspect, the same effect as that of the twenty-second aspect can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating an embodiment of a current limiting circuit according to the present invention.

FIG. 2 is a circuit diagram for explaining an embodiment of the voltage regulator of the present invention.

FIG. 3 is a circuit diagram in which the current limiting circuit of FIG. 1 is applied to the voltage regulator of FIG.

FIG. 4 is a block diagram for explaining a usage mode of the voltage regulator of FIG. 3;

FIG. 5 is a diagram for explaining the relationship between the voltage between the collector and the emitter of the control transistor and the DC current amplification factor. FIG. 5 (a) is a diagram illustrating the connection between the input voltage and the output voltage of the control transistor. Is a circuit diagram for explaining
FIG. 5B is a graph for explaining the existence of the potential difference between the collector and the emitter of the DC current gain in the control transistor of FIG. 5A.

FIG. 6 is a graph for explaining input / output characteristics of the voltage regulator of FIG. 3;

7A is a graph for explaining the output characteristic of the voltage regulator when the current limiting circuit of FIG. 1 is not used, and FIG. 7B is a graph for explaining the current limiting circuit of FIG. 5 is a graph for explaining a base increase current generated at a base of a control transistor when not used.

8A is a graph for explaining output characteristics of a voltage regulator when the current limiting circuit of FIG. 1 is used, and FIG. 8B is a graph for explaining the current limiting circuit of FIG. 5 is a graph for explaining a limited base increase current at the base of a control transistor when used.

FIG. 9 is a circuit diagram for explaining a voltage regulator using a conventional current limiting circuit.

FIG. 10 is a graph illustrating a base increase current generated at a base of a control transistor of the voltage regulator of FIG. 9;

[Explanation of symbols]

GND: ground potential Iref1: first constant current Iref2: second constant current Iref3: third constant current R1, R2: resistor network for output voltage setting M1: first MOSFET (p-channel MOSFET) Vthp1: gate threshold of first MOSFET Vg1 ... Gate potential of first MOSFET M2 ... Second MOSFET (p-channel MOSFET) Vthp2 ... Gate threshold of second MOSFET Vg2 ... Gate potential of second MOSFET M3 ... Third MOSFET (n-channel MOSFET) M4 ... Fourth MOSFET (n-channel MOSFET) T1 ... Voltage input Terminal T2: Voltage output terminal T3: Ground terminal VI: Input voltage VO: Output voltage Vdd: Input voltage Vout: Output voltage Q1: Control transistor IB: Base current of control transistor IC: Collector current of control transistor hFE: DC of control transistor Current gain VCE… Potential difference between the collector and emitter of the control transistor Q2: First current source Q3: Second current source Q4: Third current source Q5: Error amplifier Vfb: Output node voltage Vref: Reference voltage 10: Current limiting circuit 20: Voltage regulator 21 ... Reference power supply 22 ... Battery 24 ... Load

Claims (23)

[Claims] In a current limiting circuit for limiting a base current of a control transistor for controlling a load current, a potential difference between a collector and an emitter of the control transistor is monitored, and a potential difference between the collector and the emitter becomes equal to or less than a predetermined voltage. A current limiting circuit having a circuit configuration for limiting a base current flowing through the control transistor at a low input voltage. 2. A current limiting circuit for limiting a base current of a control transistor for controlling a load current, wherein a potential difference between a collector and an emitter of the control transistor is monitored, and when a potential difference between the collector and the emitter falls below a predetermined voltage. A current limiting circuit having a circuit configuration for continuously limiting a base current flowing through the control transistor during a low input voltage period. 3. The control transistor has an emitter connected to the input voltage and a collector connected to the output voltage to supply a load current to the load, and monitors the potential difference between the input voltage and the output voltage to control the base current. 3. The current limiting circuit according to claim 1, further comprising a circuit configuration for limiting. 4. A current limiting circuit for limiting a base current of a control transistor for controlling a load current, wherein a potential difference between a collector and an emitter of the control transistor is monitored, and a potential difference between the collector and the emitter falls below a predetermined voltage. A current limiting circuit having a circuit configuration for limiting a decrease in a DC current gain of the control transistor at a low input voltage. 5. A current limiting circuit for limiting a base current of a control transistor for controlling a load current, wherein a potential difference between a collector and an emitter of the control transistor is monitored, and when a potential difference between the collector and the emitter falls below a predetermined voltage. A current limiting circuit having a circuit configuration for continuously limiting a decrease in the DC current gain of the control transistor during a low input voltage period. 6. The DC current amplifier according to claim 6, wherein an emitter of said control transistor is connected to an input voltage and a collector is connected to an output voltage to supply a load current to the load, and a potential difference between said input voltage and said output voltage is monitored. 5. The current limiting circuit according to claim 3, wherein the current limiting circuit has a circuit configuration for limiting a reduction in rate. 7. A current limiting circuit for limiting a base current of a control transistor for controlling a load current, wherein a potential difference between a collector and an emitter of the control transistor is monitored, and a potential difference between the collector and the emitter falls below a predetermined voltage. A current limiting circuit having a circuit configuration for limiting a decrease in a DC current amplification factor caused by a decrease in a potential difference between a collector and an emitter of the control transistor at a low input voltage. 8. A current limiting circuit for limiting a base current of a control transistor for controlling a load current, wherein a potential difference between a collector and an emitter of the control transistor is monitored, and when a potential difference between the collector and the emitter falls below a predetermined voltage. A current limiting circuit having a circuit configuration for continuously limiting a decrease in a DC current amplification factor caused by a decrease in a potential difference between a collector and an emitter of the control transistor during a low input voltage period. 9. The DC current amplifier according to claim 1, wherein an emitter of said control transistor is connected to an input voltage and a collector is connected to an output voltage to supply a load current to the load, and a potential difference between said input voltage and said output voltage is monitored. 9. The current limiting circuit according to claim 7, wherein the current limiting circuit has a circuit configuration for limiting a decrease in the rate. 10. A current limiting circuit for limiting a base current of a control transistor for controlling a load current, wherein a potential difference between a collector and an emitter of the control transistor is monitored, and a potential difference between the collector and the emitter becomes a predetermined voltage or less. A current limiting circuit having a circuit configuration for maintaining a potential difference between a collector and an emitter of the control transistor at a low input voltage or more. 11. A current limiting circuit for limiting a base current of a control transistor for controlling a load current, wherein a potential difference between a collector and an emitter of the control transistor is monitored, and when a potential difference between the collector and the emitter falls below a predetermined voltage. A current limiting circuit having a circuit configuration for continuously maintaining a potential difference between a collector and an emitter of the control transistor at a certain level or more during a low input voltage period. 12. The control transistor has an emitter connected to an input voltage and a collector connected to an output voltage to supply a load current to a load, and monitors a potential difference between the input voltage and the output voltage to control the collector-emitter. The current limiting circuit according to claim 10, further comprising a circuit configured to hold a potential difference between the current limiting circuit and the current limiting circuit. 13. A current limiting circuit for limiting a base current of a control transistor for controlling a load current, wherein a potential difference between a collector and an emitter of the control transistor is monitored, and a potential difference between the collector and the emitter falls below a predetermined voltage. A current limiting circuit having a circuit configuration for limiting generation of a base increase current generated at a base of the control transistor at a low input voltage. 14. A current limiting circuit for limiting a base current of a control transistor for controlling a load current, wherein a potential difference between a collector and an emitter of the control transistor is monitored, and when a potential difference between the collector and the emitter falls below a predetermined voltage. A current limiting circuit having a circuit configuration for continuously limiting generation of a base increase current generated at a base of the control transistor during a low input voltage period. 15. The control transistor has an emitter connected to an input voltage and a collector connected to an output voltage to supply a load current to a load, and monitors a potential difference between the input voltage and the output voltage to increase the base increasing current. 13. The circuit according to claim 13, further comprising: a circuit configured to limit the occurrence of an error.
5. The current limiting circuit according to 4. 16. The current limiting device according to claim 13, wherein the base increasing current is a base current resulting from a decrease in a potential difference between a collector and an emitter of the control transistor. circuit. 17. The input voltage applied to the control transistor is monitored and activated during a low input voltage period in which the monitored input voltage is equal to or higher than a predetermined threshold voltage. A first MOSFET for transmitting the output voltage to the next stage; a second MOSFET for being activated according to the degree of activation of the first MOSFET to detect the output voltage; and transmitting the detected output voltage to the next stage; 17. The current limiting circuit according to claim 1, further comprising a third MOSFET activated according to a degree of activation. 18. The first MOSFET is a p-channel MOSFET, and has a circuit configuration in which a gate is connected to a drain of a second current source and a source is connected to an input voltage while a gate and a drain are connected. Monitoring the input voltage applied to the control transistor, and is activated during a low input voltage period in which the monitored input voltage is equal to or higher than a gate threshold, and the input voltage at the time of activation is set to the gate of the second MOSFET. The second MOSFET is a p-channel MOSFET, the gate is connected to the drain of the first MOSFET, the source is connected to the output voltage, and the drain is connected in parallel to the third current source and the gate of the third MOSFET. A low input voltage having an input voltage from the first MOSFET equal to or higher than a gate threshold. The activated output voltage transmitted from the 1MOSFET period the 3M
The third MOSFET is an n-channel MOSFET, the gate is connected to the drain of the second MOSFET, the drain is connected to the base of the control transistor, and the third MOSFET is connected to the base of the control transistor according to the degree of activation of the second MOSFET. 18. The current limiting circuit according to claim 17, further comprising: a third MOSFET activated by a current. 19. The current limiting circuit according to claim 18, wherein the second MOSFET has a circuit configuration in which a back bias connection is made, and a back gate of the p-channel MOSFET is biased to an input voltage. 20. A voltage regulator, which is a constant voltage power supply that keeps an output voltage supplied to a load constant, the output voltage setting for generating an output voltage according to the magnitude of the current when the current is applied. A resistor network, and the control transistor for applying a control current to the output voltage setting resistor network to control a voltage of an output node of the output voltage setting resistor network and an output voltage supplied to a load to a constant voltage value. A current limiting circuit for limiting a base current of the control transistor; a reference power supply for generating a reference voltage using a first current source; and detecting a voltage difference between a reference voltage from the reference power supply and the output node voltage. And generates an error signal based on the voltage difference, and feeds back the error signal to the control transistor to maintain a constant output voltage supplied to the load. Claims 1 to 19, characterized in that it has a differential amplifier having a feedback loop to prompt the constant voltage control that
A voltage regulator using the current limiting circuit according to any one of the above. 21. A semiconductor device comprising a fourth MOSFET for selectively transmitting the error signal output from the error amplifier or a control signal for limiting the base current output from the third MOSFET to a base of the control transistor. The voltage regulator according to claim 20, wherein: 22. The fourth MOSFET is an n-channel MOSFET, wherein the error signal from the error amplifier and the control signal from the drain of the third MOSFET are commonly connected to a gate, and the drain is the control signal. The voltage regulator according to claim 21, wherein the voltage regulator is connected to a base of the transistor. 23. The fourth MOSFET selects the control signal output from the third MOSFET during a low input voltage period, transmits the selected control signal to the control transistor, and prompts the control transistor to control the base current in the control transistor. 23. The circuit according to claim 22, further comprising a circuit configuration for selecting the error signal from the error amplifier during a period other than the low input voltage period, transmitting the error signal to the control transistor, and promoting the constant voltage control in the control transistor. Voltage regulator.