JPH1168859A - Error correction balance code transmission reception system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the transmission efficiency and a mark rate when same data are transmitted by keeping the mark rate close to 50%. SOLUTION: A transmitter side generates pluralities of kinds of data by bit operation so that a ratio of number of bits 'Os' to number of bits '1s' configuring pluralities of transmission data differs from each other, and pluralities of kinds of the generated data are alternatively transmitted. In this case, operation information denoting the conduction of the bit operation is added to each of pluralities of kinds of the generated data through the bit operation. A receiver side restores the data to a state before the bit operation based on the operation information added to the data received from the transmitter. Thus, the error correction code whose mark rate is close to 50% where 'Os' and 'Is' of transmission data are well-balanced with less deterioration in the transmission efficiency is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction balanced code transmission / reception system, and more particularly to a transmission / reception system for performing error correction while maintaining a mark ratio close to 50% by balancing transmission data "0" and "1". .

[0002]

2. Description of the Related Art FIG.
9 is a code format of an error correction code that maintains the balance shown in Japanese Patent Application Laid-Open No. 9-29904. Bose-Chaudhur code as a film correction code
i hocquenchemCode (hereinafter referred to as “BCH code”), and B having a code length n = 23 and an information length k = 12.
This is an example using CH (23, 12). Of the information length of 12 bits, 4 bits indicated by B in the figure are previously set to a pattern of “0101”, and the remaining 8 bits of “A” are used as information. Since "B" is a known value,
Instead of transmitting, the receiving side makes up for it, reducing the number of transmission bits. Generating polynomial G (X) = 1 + X + X 5 + X 6 + X 7 + X 9 +
Constituting a code to generate check bits C by X ^11.

Here, the code weight of the BCH (23.12) code is shown in FIG. The weight is the number of “1” in the code. The weight “0” is included in the BCH (23, 12) code,
There is an unbalanced code of "23". However, since “B” is not “0000” or “1111”, the weights “0” and “23” do not actually appear. Accordingly, the weight of the BCH (23, 12) is changed from "7" to "16", the mark ratio is concentrated to 30 to 70%, and a balanced error correction code can be obtained. As described above, in order to concentrate the mark rate to near 50%, an error code having an inter-code distance close to half of the code length is used in the related art.

[0004]

In the prior art described above, the inter-code distance is reduced to half of the code length in order to make the mark ratio close to 50%. Therefore, there is a disadvantage that the number of check bits increases and the data transmission efficiency decreases.

[0005] Further, in the above-mentioned prior art, the mark ratio at the time of transmitting the same continuous data is not taken into consideration. Therefore, when data with a poor mark rate is continuously transmitted, the mark rate is continued, and there is a disadvantage that the mark rate in that period deteriorates.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks of the prior art, and has an object to reduce the mark rate to 5%.
An object of the present invention is to provide an error-correction balanced code transmission / reception system capable of improving transmission efficiency and a mark rate during transmission of the same data while maintaining the transmission ratio at around 0%.

[0007]

SUMMARY OF THE INVENTION A transmitter according to the present invention comprises:
Bit ratio operating means for generating a plurality of types of data by performing bit operations on transmission data to be transmitted such that the ratio of the number of “0” bits to the number of “1” bits constituting the transmission data is different from each other; Selection means for alternatively transmitting the plurality of types of generated data. Further, operation information indicating that a bit operation has been performed by the bit ratio operation unit is added to each of the plurality of types of data generated by the bit operation of the bit ratio operation unit.

[0008] The receiver according to the present invention is characterized in that the receiver includes means for returning the data to a state before the bit operation based on the operation information added to the data received from the transmitter.

The error correction balanced code transmission / reception system according to the present invention performs bit operations on transmission data to be transmitted so that the ratio of the number of bits “0” to the number of “1” constituting the transmission data is different from each other. A transmitter including bit ratio operating means for performing the above operation to generate a plurality of types of data, and selecting means for selectively transmitting the generated plurality of types of data; and A receiver including means for returning the data to a state before the bit operation based on the operation information.

In short, in this transmission / reception system, a plurality of types of patterns having different combinations of error-correction-coded “0” and “1” are prepared as transmission data, and “0” and “0” of already transmitted data are prepared. From the balance with "1", data to be transmitted next is selected from a plurality of prepared patterns and transmitted.

More specifically, the transmitter side adds a bit (8 in FIG. 1) indicating whether the data is inverted to the transmission data (1 in FIG. 1), and inverts the transmission data. (4 in FIG. 1), means for adding a check bit for error correction to transmission data (2 in FIG. 1), and means for counting the balance between "0" and "1" of transmission data (FIG. 1). 1) 3) and means (5 in FIG. 1) for selecting data to be transmitted next from the balance of data already transmitted. Further, the receiver side has a means for correcting an error in the received transmission data (6 in FIG. 1) and a means for confirming whether or not the data has been inverted and, if so, means for inverting the bit (FIG. 1). 11).

As described above, since a bit indicating whether or not data is inverted is added to data to be transmitted, a conventional error correction code can be used, and deterioration of transmission efficiency can be reduced. Further, data is transmitted such that the mark ratio approaches 50% in accordance with the balance of already transmitted data (data transmitted immediately before or earlier), so that a balanced error correction code can be obtained. .

[0013]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of an error correction balanced code transmission / reception system according to a first embodiment of the present invention. FIG. 1 (a) is a configuration of a transmitter and FIG. 1 (b).
Indicates the configuration of the receiver.

Referring first to FIG. 1A, the transmitter comprises:
A combiner 1 for combining transmission data 7 and an inverted bit 8 (“I”) indicating whether the data is inverted.
, A bit inversion circuit 4 for inverting bits, an error correction code generation circuit 2 for generating an error correction code, and “0” and “1” constituting transmission data including check bits for error correction. And a balance comparing circuit 5 for comparing and selecting the next data to be transmitted next from the already transmitted data.

On the other hand, referring to FIG.
An error correction circuit 6 for correcting an error of transmitted data;
An inversion processing circuit 11 for inverting the data if the data is inverted by looking at the contents of the inversion bit 8.

Next, the operation of the transmission / reception system according to the first embodiment of the present invention will be described in detail with reference to FIGS.

FIG. 2 shows the format of the code of the transmission data. In the figure, “D” is data,
“I” is an inverted bit, and “C1” and “C2” are check bits generated for error correction. In addition, "/
"D" and "/ I" respectively indicate that the bits are inverted.

First, the operation of the transmitter will be described. The transmission data 7 is synthesized by the inverting bit 8 indicating whether or not the data to be transmitted is inverted and the synthesizer 1. The result of this synthesis is in the format as shown in the synthesizer output in FIG. The inverted bit "I" is one bit as shown in FIG. The output of the synthesizer 1 is divided into the following two systems.

First, in the first system, a check bit for performing error correction by the error correction code generation circuit 2 is generated and added to the data shown in the error correction code generation circuit input of the system of FIG. I do. The output of the error correction code generation circuit 2 has a format as shown in the error correction code generation circuit output of the system of FIG. That is, a format in which the data “D” and the inverted bit “I” are combined is obtained.

Then, the ratio (ratio) of "0" and "1" of the output of the error correction code generation circuit 2 to the balance counting circuit 3
Count with. The data and the counting result in the balance counting circuit 3 are output to the balance comparing circuit 5.

On the other hand, in the second system, the output of the synthesizer 1 is bit-inverted by the bit inversion circuit 4. As a result, both the data and the inversion bit are inverted as shown in the error correction code generation circuit input of the system in FIG. After the bit inversion, the error correction code generation circuit 2 generates and adds a check bit for performing error correction.

The output of the error correction code generation circuit 2 has a format as shown in the error correction code generation circuit output of the system of FIG. That is, the data "/ D"
And an inverted bit “/ I”.

Then, the ratio between "0" and "1" of the output of the error correction code generation circuit 2 is counted by the balance counting circuit 3. The data and the counting result in the balance counting circuit 3 are output to the balance comparing circuit 5.

The balance comparing circuit 5 stores the balance of the data transmitted immediately before. When the ratio of “0” of the data transmitted immediately before is large, the balance between the above systems and the data obtained from the systems is compared, and the data of the system with the larger ratio of “1” is transmitted. If the ratio of “1” in the data transmitted immediately before is large, on the contrary, the data of the system with the larger ratio of “0” is transmitted.

Although the balance comparing circuit 5 compares the balance of the data transmitted immediately before, the data to be transmitted next may be selected in a state several bytes before the transmitted data.

Next, the operation of the receiver will be described. The data transmitted from the above-mentioned transmitter is received by the receiver.
This data is input to the error correction circuit 6, and if there is an error in the data, the error is corrected. Also, the check bits C1 and C2 are removed. The output of the error correction circuit 6 has the format shown in the output of the error correction circuit in FIG.

Here, there are two types of formats as follows. That is, the data that has passed through the transmitter system has a format in which the data “D” and the inverted bit “I” are combined, in which the data and the inverted bit are not inverted. On the other hand, data that has passed through the transmitter system has a format in which data “/ D” and inverted bit “/ I” are combined, in which the data and the inverted bit are inverted.

When the inversion bit 8 is inverted ("/ I"), the inversion processing circuit 11 inverts all bits and restores the original transmission data. If the inversion bit is not inverted ("I"), the bit inversion operation is not performed. That is, the inverted bit 8 indicates whether the bit operation has been performed.

Further, the inverted bit 8 is removed to obtain the original transmission data. In the inversion circuit 4, all bits are inverted, but an operation of inverting a specific bit may be performed. In that case, the inversion processing circuit 11 inverts the bit corresponding to the bit inverted by the inversion circuit 4.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a block diagram showing a configuration of an error correction balanced code transmission / reception system according to a second embodiment of the present invention, and shows a configuration of a transmitter. In the transmission / reception system according to the second embodiment, the number of inverted bits 8 is increased to 2 bits.

Referring to FIG. 3, a transmitter includes a combiner 1 for combining transmission data and a data inversion bit, and bit inversion circuits 4a, 4b, and 4c for inverting bits.
Code generation circuit 2 for generating an error correction code
A balance counting circuit 3 for counting the balance between "0" and "1" of transmission data including a check bit for error correction, and a balance between data already transmitted and data to be transmitted next. And a balance comparing circuit 5 for comparing and selecting.

It is assumed that a receiver not shown in the figure has the same configuration as that of FIG.

Next, the operation of the transmitting / receiving system according to the second embodiment of the present invention will be described in detail with reference to FIGS.

FIG. 4 shows the format of the code of the transmission data. In the figure, “D” is data and is divided into “D1” and “D2”. “I” is an inverted bit and is divided into “I1” and “I2”.
“C” is a check bit. "/ D1", "/ D
"2", "/ I1", and "/ I2" indicate that the bits are inverted, respectively.

First, the operation of the transmitter will be described. The transmission data 7 is synthesized by the inverting bit 8 indicating whether or not the data to be transmitted is inverted and the synthesizer 1. Here, data “D” is divided into two groups “D1” and “D1”.
2 ". Then, an inverted bit indicating whether the data “D2” is inverted is set to “I1” and the data “D2”
2 is inverted to “I”
2 ". This format is shown in the combiner output of FIG.

The output of the synthesizer 1 is divided into four systems. In the first system, the error correction code generation circuit 2 generates and adds a check bit for performing error correction without operating the output of the synthesizer 1. The output of the error correction code generation circuit 2 has a format as shown in the error correction code generation circuit output of the system of FIG. The ratio between “0” and “1” of the output of the error correction code generation circuit 2 is counted by the balance counting circuit 3. The data and the counting result are output to the balance comparison circuit 5.

In the second system, the output of the synthesizer 1 is converted into data "D2" and an inverted bit "I2" by a bit inversion circuit 4a.
Is bit-inverted. As a result, as shown in the error correction code generation circuit input of the system of FIG.
2 "and the inverted bit" I2 "obtain inverted data.

After bit inversion, the error correction code generation circuit 2 generates and adds a check bit for correcting an error. The output of the error correction code generation circuit 2 has a format as shown in the error correction code generation circuit output of the system of FIG. The ratio between “0” and “1” of the output of the error correction code generation circuit 2 is counted by the balance counting circuit 3. The data and the count result are output to the balance comparison circuit 5.

In the third system, the output of the synthesizer 1 is converted into data "D1" and an inverted bit "I1" by a bit inversion circuit 4b.
Is bit-inverted. As a result, as shown in the input of the error correction code generation circuit of the system of FIG. 4, data obtained by inverting the data “D1” and the inverted bit “I1” is obtained.

After the bit inversion, the error correction code generation circuit 2 generates and adds a check bit for correcting an error. The output of the error correction code generation circuit 2 has a format as shown in the error correction code generation circuit output of the system of FIG. The ratio between “0” and “1” of the output of the error correction code generation circuit 2 is counted by the balance counting circuit 3. The data and the count result are output to the balance comparison circuit 5.

In the fourth system, the output of the synthesizer 1 is converted into data "D1" and data "D2" by the bit inversion circuit 4c.
And the inverted bit “I1” and the inverted bit “I2” are bit-inverted. As a result, as shown in the error correction code generation circuit input of the system of FIG.
, Data “D2”, inverted bit “I1”, and inverted bit “I2” to obtain inverted data.

After the bit inversion, the error correction code generation circuit 2 generates and adds a check bit for correcting an error. The output of the error correction code generation circuit 2 has a format as shown in the error correction code generation circuit output of the system of FIG. The ratio between “0” and “1” of the output of the error correction code generation circuit 2 is counted by the balance counting circuit 3. The data and the count result are output to the balance comparison circuit 5. The balance comparison circuit 5 stores the balance of the data transmitted immediately before. The balance of the data transmitted immediately before is compared with the balance of the data obtained from each of the above systems, systems, systems and systems, and the data of the system with the best balance is selected and transmitted.

Although the balance comparing circuit 5 compares the balance with the data transmitted immediately before, the data to be transmitted next may be selected from a state several bytes before the transmitted data.

The operation of the receiver will be described. The difference from the first embodiment is the operation of the inversion processing circuit 11. The inversion processing circuit 11 checks the inverted bits “I1” and “I2”. If the inverted bit “I1” is inverted, the data “D1” and the inverted bit “I1” are inverted. If the inverted bit “I2” is inverted, the data “D2” and the inverted bit “I2” are inverted. Further, the inversion bit can be removed and the original transmission data can be restored as shown in the output of the inversion processing circuit in FIG. Although the inversion circuit 4 inverts all bits, it may perform an operation of inverting a specific bit. In this case, the inversion processing circuit “I1” inverts the bit corresponding to the bit inverted by the inversion circuit 4.

Here, the internal configuration of the balance comparison circuit and the bit inversion circuit in FIGS. 1 and 3 will be described. FIG. 5 is a block diagram showing an example of the internal configuration of the balance comparison circuit, and the same parts as those in FIGS. 1 and 3 are denoted by the same reference numerals.

Referring to FIG. 5, the balance comparison circuit 5
Is configured to include a data selection circuit 51 for selecting and outputting data output from each balance counting circuit 3 and a transmission data balance counting circuit 52 for controlling selection conditions in the data selection circuit 51.

In such a configuration, the balance counting circuit 3
Then, the ratio between “0” and “1” of the input data is counted. For example, the number of “0” and “1” constituting data
And the number of each. And (the number of "1")-
(The number of “0”) is calculated, and the calculation result is output to the balance comparison circuit 5. The result of this operation is “0” if the number of “0” and “1” are equal, a positive value if the number of “1” is large, and a negative value if the number of “0” is large.

The balance comparing circuit 5 counts the number of "0" and the number of "1" of the transmission data 9 respectively. And
The calculation of (number of “1”) − (number of “0”) is performed by the transmission data balance counting circuit 52. In the data selection circuit 51,
The operation result of comparing the number of “0” and “1” in the balance counting circuit input to the balance comparison circuit 5 and the “0” of the transmission data obtained by the transmission data balance counting circuit 52
And an operation result obtained by comparing the number of “1” with the number of “1”.

The same addition operation is performed on the operation result obtained by comparing the numbers “0” and “1” inputted from the respective balance counting circuits 3. Then, in order to obtain transmission data in which “0” and “1” are balanced, the data selection circuit 51 selects the one whose addition operation result is closest to “0”,
Output as transmission data 9. The output transmission data 9 is input to the transmission data balance counting circuit 52 again. Then, "0" and "1" are counted to determine data to be transmitted next, and the same operation as described above is repeated to obtain transmission data.

Here, the transmission data balance counting circuit 52
Then, the number of “0” and “1” of one data transmitted immediately before is counted, and the calculation of (the number of “1”) − (the number of “0”) is performed. Used for control.

Also, "0" and "1" are set at longer time intervals.
In order to control so as to maintain the balance with the transmission data balance counting circuit 52, not only the immediately preceding data but also the calculation result of the balance of the transmitted data is sequentially added to the transmission data balance counting circuit. And the like, and the result may be input to the data selection circuit 51.

FIG. 6 is a block diagram showing an example of the internal configuration of the bit inversion circuit, and the same parts as those in FIGS. 1 and 3 are denoted by the same reference numerals.

Referring to the figure, the bit inversion circuit 4
A bit inversion table 41 for presetting the position of the bit to be inverted, and a bit inversion table 4
An exclusive OR operation circuit 42 that performs an exclusive OR operation on the bit set to 1 and the corresponding bit of the input data.

In such a configuration, "1" is set at the position of the bit to be inverted in the bit inversion table 41. The exclusive OR operation circuit 42 performs an exclusive OR operation of the bit inversion table 41 and the input data.
Obtain data with the desired bit inverted. And FIG.
When it is desired to invert all bits like the bit inversion circuit 4 in FIG. 3 or the bit inversion circuit 3 in FIG. 3, data of all “1” is set in the bit inversion table 41.

When it is desired to invert the latter half of the data as in the bit inverting circuit 1 in FIG. 3, data in which the latter half bit to be inverted is set to "1" is set in the bit inversion table 41. When the first half of the data is to be inverted, as in the bit inversion circuit 2, data in which the first half of the bit to be inverted is set to “1” is set in the bit inversion table 41.

As described above, in this transmission / reception system, an inverted bit is provided in order to maintain balance, and one data is converted into a plurality of data to transmit the optimum data. Therefore, as the number of inverted bits increases, the transmission efficiency decreases, but the effect of maintaining the balance increases. The number of inversion bits is determined by an error correction coding scheme to be used and a target mark rate. Therefore, there is an effect that the deterioration of the transmission efficiency is reduced, the transmission data “0” and “1” are balanced, the mark ratio is around 50%, and an error correction code is obtained.

In the present system, a plurality of data with different mark ratios are prepared for the same data, and the transmission data is selected so that the mark ratio is set to 50%. For this reason, even in the transmission of the same data continuously, the balance between the data “0” and “1” is maintained, and the mark ratio is reduced to 50.
%.

The present invention can take the following aspects in connection with the description of the claims.

(1) The selecting means includes counting means for counting the number of "0" and the number of "1" constituting each of the plurality of types of data, and "0" according to the counting result.
7. The transmitter according to claim 6, wherein data whose difference between the number of "1" and the number of "1" is closest to zero is selected.

(2) The transmitter according to any one of claims 1 to 6, wherein the bit ratio operation means generates data on which a bit operation is performed and data on which the bit operation is not performed.

(3) Inverting bit adding means for adding an inverting bit for determining whether data to be transmitted is inverted, inverting means for inverting data to which the inverting bit has been added, and this inverting means Check bit adding means for adding a check bit for performing error correction of the data to the subsequent data; and a difference between the number of "0" and the number of "1" constituting the data after the addition of the check bit is zero. Selecting means for selecting the transmission data closest to the transmission data, and transmitting the selected transmission data.

(4) A receiver comprising means for returning data to a state before inversion based on an inversion bit added to data received from the transmitter of (3).

(5) A transmission / reception system comprising the transmitter of (3) and the receiver of (4).

[0065]

As described above, according to the present invention, a plurality of types of bits are operated by performing bit operations so that the ratio of the number of "0" bits to the number of "1" bits constituting data to be transmitted is different from each other. By generating data and selecting and transmitting a data having a difference between the number of “0” and the number of “1” which is closest to zero among the plurality of types of data, the transmission efficiency is reduced. There are effects that the data "0" and "1" are balanced, the mark ratio is close to 50%, and an error correction code is obtained. Then, even in the transmission of the same data continuously, there is an effect that the balance between "0" and "1" of the data can be maintained and the mark ratio can be set to around 50%.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an error correction balanced code transmission / reception system according to a first embodiment of the present invention. FIG. 1 (a) shows a configuration of a transmitter, and FIG. 1 (b) shows a configuration of a receiver. Is shown.

2 is a diagram showing a data format in the error correction balanced code transmission / reception system of FIG. 1; FIG. 2 (a) shows a data format on a transmitter side; FIG. 2 (b) shows a data format on a receiver side;

FIG. 3 is a block diagram showing a configuration of an error correction balanced code transmission / reception system according to a second embodiment of the present invention.

4 is a diagram showing a data format in the error correction balanced code transmission / reception system of FIG. 3, wherein FIG. 4 (a) shows a data format on a transmitter side and FIG. 4 (b) shows a data format on a receiver side.

FIG. 5 is a block diagram illustrating a configuration example of a balance comparison circuit in FIGS. 1 and 3;

FIG. 6 is a block diagram illustrating a configuration example of a bit inversion circuit in FIGS. 1 and 3;

FIG. 7 is a diagram illustrating a code format of an error correction code that is balanced by a conventional technique.

FIG. 8 is a diagram illustrating code weights of a BCH (23, 12) code.

[Explanation of symbols]

 Reference Signs List 1 synthesizer 2 error correction code generation circuit 3 balance counting circuit 4, 4a, 4b, 4c bit inversion circuit 5 balance comparison circuit 6 error correction circuit 7 transmission data 8 inversion bit 9 transmission data 10 reception data

Claims (8)

[Claims] 1. A plurality of types of data are generated by performing bit operations on transmission data to be transmitted so that the ratio of the number of “0” bits to the number of “1” bits constituting the transmission data is different from each other. A transmitter comprising: a bit ratio operating means; and a selecting means for selectively transmitting the plurality of types of generated data. 2. An operation information adding unit for adding operation information indicating that bit operation by the bit ratio operation unit has been performed to each of a plurality of types of data generated by the bit operation of the bit ratio operation unit. The transmitter of claim 1, comprising: 3. The transmitter according to claim 2, wherein the operation information adding unit adds operation information to a specific portion of the data after the bit operation. 4. An apparatus according to claim 1, further comprising an error correction code adding means for adding an error correction code for performing error correction on the data to which the operation information has been added by the operation information adding means. A transmitter according to any one of claims 1 to 3. 5. The transmitter according to claim 2, wherein the operation information is an inversion bit indicating whether data is inverted. 6. The selecting means selects one of a plurality of types of data generated by the bit ratio operating means, wherein the difference between the number of “0” and the number of “1” constituting the data is closest to zero. The transmitter according to claim 1, wherein the transmitter is selected. 7. A means for returning data to a state before bit operation based on the operation information added to the data received from the transmitter according to any one of claims 2 to 6. Receiver. 8. A transmission / reception system comprising: the transmitter according to claim 2; and the receiver according to claim 7.