JPH1168517A - Digital filter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital filter that can suppress the increase of a scale of an arithmetic circuit. SOLUTION: An addition processing 21 of a multiplication result of a multiplication processing 26 is performed with digital data Din inputted at a specified frequency. A multiplication processing 22 for multiplying a coefficient (a0) to the result of the addition processing 21 is performed. A delay processing 23 for one data period is performed with the result of the addition processing, and a multiplication processing is executed for delayed digital data. In this multiplication processing, a coefficient (c) is multiplied and a multiplication processing 24 is performed and for that result, coefficients (a2) and (b2) are each multiplied and multiplication processings 25 and 26 are executed. By executing the multiplication processing 24 on the coefficient (c) and the multiplication processing 25 on the coefficient (a), a similar result to the case in which a multiplication processing of a coefficient (c×a2=a1) is obtained. Also, by executing the multiplication processing 24 on the coefficient (c) and the multiplication processing 26 on a coefficient (b2) a result similar the case in which a multiplication processing of a coefficient (c×b2=b1) is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital filter for performing algebraic arithmetic processing on digital data.

[0002]

2. Description of the Related Art FIG. 3 shows a configuration of a calculation process in a conventional digital filter. First, the digital data Din input at a predetermined cycle is multiplied by a multiplication process 3 described later.
The addition process 31 of 5 is performed. Next, a multiplication process 32 for multiplying the result of the addition process 31 by a predetermined coefficient a0
Is performed.

In addition, the addition result of the addition processing 31
Delay processing 33 for one data period is performed, and predetermined coefficients a1 and b1 are assigned to the delayed digital data.
Are multiplied 34 and 35 for multiplying by. Here, one data period matches the input cycle of the digital data Din.

The result of the multiplication process 32 and the multiplication process 3
4 is performed, and the result of the addition is output as digital data Dout having undergone a predetermined process.

[0005] The above processing is repeated every time new digital data Din is input to the digital filter at a predetermined cycle. According to such arithmetic processing, when the digital data Din is, for example, audio data, enhancement of a specific frequency band, phase adjustment, and the like can be realized.

[0006]

In the above digital filter, generally, a logical operation unit (ALU: Ar) is used.
It is composed of a combination of an ithmetic logic unit) and a memory, and each of the addition processes 31 and 36 and each of the multiplication processes 3
2, 34 and 35 are sequentially processed in a time-division manner. At this time, a register of a predetermined length is allocated in the ALU to store the coefficients a0, a1, and b1 in the multiplication processes 32, 34, and 35. However, in designing a digital filter, if there is a large difference in the number of digits between the coefficients a0, a1, and b1, the word length of the register for storing the coefficients a0, a1, and b1 becomes large. For example,
Coefficient a0 is 0.5, coefficient a1 is 0.0001, coefficient b1
Is -0.0001, these coefficients a0, a
In order to quantize 1 and b1 with a binary number, a total of 11 bits including 10 bits and 1 sign bit is required.

Further, as the word length of the register increases, the word length of the register for storing the multiplication result further increases. As a result, there is a problem that the circuit size of the ALU increases.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a digital filter capable of suppressing an increase in circuit scale.

[0009]

According to a first aspect of the present invention, there is provided a digital signal processing apparatus comprising: multiplying digital data input at a predetermined period by a predetermined coefficient to perform a calculation process; In a digital filter that outputs data, a first multiplication process that multiplies input digital data by a first coefficient, a delay process that delays input digital data for an integral multiple of an input period, and a delay process A second multiplication process for multiplying the obtained digital data by a second coefficient, a multiplication result of the first multiplication process and the second multiplication process
And an addition process of adding the multiplication result of the multiplication process of the above. One of the first multiplication process and the second multiplication process is to perform a multi-stage multiplication process continuously. .

According to a second aspect of the present invention, there is provided a third multiplication process for multiplying the delayed digital data by a third coefficient, and a third multiplication process for the input digital data.
And an addition process for adding a multiplication result of the multiplication process. The third multiplication process performs a multi-stage multiplication process continuously, and at least the first stage includes the second multiplication process. The gist is that the multiplication process is performed in common with the first stage of the multi-stage multiplication process.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment in which the present invention is embodied in a digital filter will be described below with reference to FIGS.

FIG. 1 shows a digital filter 10 as a digital signal processing circuit used for audio equipment and the like. The digital filter 10 emphasizes the frequency of a specific band or shifts the phase of the audio signal. The digital filter 10 includes a latch circuit 12, a RAM,
14. Logical operation unit (hereinafter simply referred to as ALU) 1
7 and an output circuit 20.

The latch circuit 12 is connected to the bus line 11 via a tri-state buffer 13. The latch circuit 12 holds the input digital data Din and outputs it to the bus line 11 via the tri-state buffer 13.

The input side of the RAM 14 is connected to the bus line 11 via a buffer 15, and the output side of the RAM 14 is connected to the bus line 11 via a tri-state buffer 16. The RAM 14 inputs and stores data on the bus line 11 via the buffer 15, and outputs the stored data to the bus line 11 via the tri-state buffer 16.

The input side of the ALU 17 is connected to the bus line 11, and the output side of the ALU 17 is connected to the bus line 11 via the tri-state buffer 18. ALU
Reference numeral 17 inputs data on the bus line 11 and executes a predetermined operation (multiplication and addition), and outputs the operation result to the bus line 11 via the tri-state buffer 18.

The output circuit 20 is connected to the bus line 11. The output circuit 20 receives data on the bus line 11 and outputs the data to the outside. The ground GND as a pull-down unit is connected to the bus line 11 via a tri-state buffer 19.

The tri-state buffers 13, 16, 1
The conduction of the circuits 8 and 19 is controlled based on control signals SG1 to SG4 supplied from a control circuit (not shown), and the conducted tristate buffers output the output data of the corresponding circuits to the bus line 11.

FIG. 2 shows the configuration of the arithmetic processing of the digital filter 10 in the present embodiment. First, the digital data Din is input at a predetermined cycle, and the ALU 17 performs an addition process 21 of a multiplication result of a multiplication process 26 described later. Next, the ALU 17 performs a first multiplication process 22 for multiplying the result of the addition process 21 by a coefficient a0 as a first coefficient.

Further, the addition result of the addition processing 21
The AM 14 performs a delay process 23 for one data period. That is, the addition result of the addition process 21 is temporarily stored in the RAM 14, and the immediately preceding digital data is read from the RAM 14. Here, one data period matches the input cycle of the digital data Din. Then, the ALU 17 performs a multiplication process on the delayed digital data. In this multiplication process, first, a multiplication process 24 for multiplying by a predetermined coefficient c is performed, and multiplication processes 25 and 26 for multiplying the result of the multiplication process by predetermined coefficients a2 and b2, respectively. In the present embodiment, the second multiplication process is configured by the multiplication processes 24 and 25, and the third multiplication process is configured by the multiplication processes 24 and 26. By successively performing the multiplication processing 24 of the coefficient c and the multiplication processing 25 of the coefficient a2, the same result as in the case of performing the multiplication processing of the coefficient (c × a2 = a1) can be obtained. Further, by continuously performing the multiplication processing 24 of the coefficient c and the multiplication processing 26 of the coefficient b2, the same result as in the case of performing the multiplication processing of the coefficient (c × b2 = b1) can be obtained.

Then, the multiplication processing 22 is performed by the ALU 17.
Is added to the result of the multiplication process 25, and the result of the addition is output via the output circuit 20 as digital data Dout having undergone a predetermined arithmetic process. Further, the ALU 17 performs an addition process 21 of the next new digital data and the result of the multiplication process 26.

The above processing is repeated each time new digital data Din is input at a predetermined cycle. In the digital filter 10 of the present embodiment, the multiplication process 2
Coefficients a0, c, a2 in 2, 24, 25, 26
A register of a predetermined length is allocated in the ALU 17 to store b2. The multiplication process for the immediately preceding digital data stored in the RAM 14 in the delay process 23 is a coefficient (c × a2 = a1) and a coefficient (c × b2 = b1), and these values are compared with the value of the coefficient a0. Are very small, the coefficients (c × a2 = a1) and (c × b
The word length of the register for storing 2 = b1) increases. However, in the present embodiment, the multiplication processing 24 of the coefficient c is performed.
And a multiplication process of coefficients a2 and b2. Therefore, the values of the coefficients c, a2, and b2 can be made larger than the values of (c × a2 = a1) and the coefficient (c × b2 = b1). Therefore, the word length of the register for storing the coefficients a0, c, a2, and b2 can be reduced. For example, the coefficient a0 is 0.5, the coefficient c is 0.01, the coefficient a2 is 0.01, and the coefficient b2 is -0.01. In order to quantize these coefficients a0, c, a2, and b2 in binary numbers,
It suffices if there are a total of 8 bits including 7 bits and 1 sign bit.

This embodiment has the following effects because it is configured as described above. In the present embodiment, when the value of a coefficient in the multiplication process is small, the coefficient is divided into a product of a plurality of coefficients larger than the value, and the multiplication process is sequentially performed with the plurality of coefficients. Therefore, the word length of the register for storing the coefficient of the multiplication process can be reduced, and an increase in the circuit size of the ALU 17 can be suppressed.

Further, the word length of the register for storing the multiplication result can be further reduced with the reduction in the word length of the register for storing the coefficient. As a result, an increase in the circuit size of the ALU 17 can be further suppressed.

The embodiment is not limited to the above, but may be modified as follows. In the above embodiment, the multiplication process is performed twice on the previous digital data stored in the RAM 14 in the delay process 23 continuously. However, the multiplication process is performed three or more times continuously. It may be performed.

In the above embodiment, the delay processing 23
Since the coefficient of the multiplication process for the previous digital data stored in the AM 14 is small, the multiplication process 24
And the coefficients a2 and b2 are divided into multiplication processes 25 and 26,
When the value of the coefficient a0 is small, the coefficient a0 may be divided into a product of a plurality of coefficients, and a plurality of (two or more) multiplication processes may be performed.

[0026]

As described in detail above, according to the present invention, when the value of a coefficient in the multiplication process is small, the coefficient is divided into a product of a plurality of coefficients larger than the value, and Are sequentially performed. Therefore, the word length of the register for storing the coefficient of the multiplication process can be reduced, and an increase in the circuit scale of the arithmetic circuit can be suppressed.

Further, as the word length of the register for storing the coefficient can be reduced, the word length of the register for storing the multiplication result can be further reduced. As a result, it is possible to further suppress an increase in the circuit scale of the arithmetic circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a digital filter according to an embodiment;

FIG. 2 is a configuration diagram illustrating a calculation process according to an embodiment;

FIG. 3 is a configuration diagram showing a conventional arithmetic processing.

[Explanation of symbols]

12 latch circuit, 14 RAM, 17 ALU, 20
... output circuits, 21, 27 ... addition processing, 22, 24, 2
5, 26 ... multiplication processing, 23 ... delay processing.

Claims (2)

[Claims] 1. A digital filter for multiplying digital data input at a constant cycle by a predetermined coefficient and outputting digital data subjected to arithmetic processing, wherein a first coefficient is applied to the input digital data. A first multiplication process for multiplying, a delay process for delaying input digital data for an integral multiple of an input period, a second multiplication process for multiplying the delayed digital data by a second coefficient, And an addition process for adding the multiplication result of the first multiplication process and the multiplication result of the second multiplication process. One of the first multiplication process and the second multiplication process includes:
A digital filter characterized by continuously performing multi-stage multiplication processing. 2. A third multiplication process for multiplying the delayed digital data by a third coefficient, and an addition process for adding a multiplication result of the third multiplication process to the input digital data. , The third multiplication process performs a multi-stage multiplication process continuously, and at least the first stage performs the first multi-stage multiplication process in the second multiplication process. The digital filter according to claim 1, wherein the digital filter is performed in common with the step.