JPH1168051A - Electrostatic breakdown protective element and semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent electrostatic breakdown of gate oxide film or generation of current filament by forming first and second semiconductor regions of second conductivity type, while spacing apart from each other, on a semiconductor substrate of first conductivity type and isolating the second semiconductor region from a third semiconductor region through a field oxide. SOLUTION: N type semiconductor regions 29, 31 are formed at a desired interval on the surface of a P type semiconductor substrate 30. The N type semiconductor region 29 is isolated from an N type semiconductor region 19 through a field oxide 24. Furthermore, a P type semiconductor region 18 for connecting the substrate 30 surely with a substrate voltage, a first electrode 26 connected with the N type semiconductor region 29, a second electrode 27 connected with the N type semiconductor region 19, and third electrode 28 connected with the P type semiconductor region 18 are arranged in the vicinity of the N type semiconductor region 31. P type semiconductor regions 20, 21 for stabilizing the threshold voltage between the N type semiconductor regions 29, 31 and the substrate 30 are also formed contiguously to the N type semiconductor regions 29, 31.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic discharge protection device and a semiconductor integrated device, and more particularly, to protecting a gate oxide film of an MIS type semiconductor device from an excessive voltage and reducing an electrostatic withstand voltage of a drain region. The present invention relates to an electrostatic discharge protection element that can be improved and a semiconductor integrated device having the same electrostatic discharge protection element on the same substrate.

[0002]

2. Description of the Related Art A semiconductor integrated circuit is excessively large, for example, from a human body and a mechanical device for assembling / transporting through a pin terminal of a package during a chip assembling process and a transporting of a package. a voltage and current and the like may be introduced into the package, electrostatic breakdown (ESD: El ectro- St atic D ischarge) by internal LSI circuit gate oxide film, can destroy the PN junction, etc. is there. Therefore, various circuits have been proposed as a combination of a polysilicon, a protection resistor formed by a diffusion layer, a MOS element in a diode form, and a clamp element formed by a parasitic MOS or the like as an electrostatic breakdown protection circuit.

[0003] An electrostatic discharge protection circuit proposed in Japanese Patent Application Laid-Open No. 3-283668 will be described below. As shown in FIG. 6, the protection circuit here mainly includes a protection resistor 12, a protection diode 13, and a protection MOS transistor 15 configured to have a high electrostatic breakdown voltage, and these elements are all the same. It is integrated on a semiconductor substrate.

When the internal circuit 10 is operating, the internal circuit 1 is connected to N2 of the protective MOS transistor 15.
0 and the power supply voltage, the protection MO
The resistance is lowered by turning on the S transistor 15, and the delay time between the protection resistance 12 between the input terminal 11 and the internal circuit 10 and the parasitic capacitance at N 2 can be minimized.

When the internal circuit 10 does not operate,
The protection MOS transistor 15 is off and the protection MO
Since the resistance of the S transistor 15 becomes almost infinite,
The resistance between the input terminal 11 and the internal circuit 10 is only the protection resistance 12 set to a predetermined size.
With the protection diode 13, the internal circuit 10 can be protected from a surge due to excessive static electricity.

The above-mentioned protection MOS transistor 15 can be formed with a structure as shown in FIG. That is, the P well region 6 is formed on the surface of the P type semiconductor substrate 1 having the field oxide film 8, and the side wall spacer 4 is formed on the P well region 6 via the gate oxide film 16.
Is formed, and the gate electrode 17 forms a transistor together with the source / drain region 9 formed in the P well region 6. Also,
A high concentration N-type semiconductor region 7 is formed near the field oxide film 8. In this device, device isolation is performed by a field oxide film 8 and a channel stopper (not shown), and a gate electrode is made of a polycrystalline silicon film doped with an N-type impurity to reduce resistance and a high melting point. It is formed of a silicide film of a metal or a composite film of a high melting point metal. The source / drain regions 9 are formed by doping an N-type impurity before forming the sidewall spacers 4 or by doping an N-type impurity having a high diffusion coefficient such as phosphorus after forming the sidewall spacers 4. ing.

According to such a structure, unlike the source / drain region having the LDD structure, a low-concentration semiconductor region is not formed in the source / drain region 9, so that the resistance value of the drain region 9 is reduced, and When static electricity is input to 9, the generation of Joule heat due to a surge current is suppressed, and gate destruction due to excessive Joule heat can be prevented. Further, even if a negative potential is applied to the drain region 9 by applying a power supply voltage to the N-type semiconductor region 7, the charges generated at this time are neutralized by the N-type semiconductor region 7.

FIG. 8 shows another example of the protection MOS transistor 15. In this device, an N-type semiconductor buried layer 3 is formed between a P-type semiconductor substrate 1 and a P-type well region 6, and within the N-type semiconductor buried layer 3,
7 has the same configuration as that of the element in FIG. 7 except that a high-concentration P-type semiconductor region 5 is formed near the type semiconductor region 7.

As described above, since the N-type semiconductor buried layer 3 is formed, the extension of the depletion layer from the drain region 9 is suppressed, so that the junction capacitance of the drain region 9 is increased and excessive static electricity is input. In this case, more charges due to the surge can be absorbed, and electrostatic breakdown can be prevented. When a negative potential surge is applied to the drain region 9 and a positive voltage is applied to the N-type semiconductor buried layer 3, charges are neutralized in the N-type semiconductor buried layer 3.

FIG. 9 shows another example of the protection MOS transistor 15. This element is composed of a P-well region 6 and a P-well region.
A P-type semiconductor buried layer 5 and an N-type semiconductor buried layer 2 are formed between the N-type semiconductor buried layer 3 and the N-type semiconductor buried layer 3. It is connected to the. The N-type semiconductor region 7
Is connected to a power supply voltage or a positive potential, and the P-type semiconductor buried layer 5 is connected to a substrate potential. The junction withstand voltage at the interface between the N-type semiconductor buried layers 3 and 7 and the P-type semiconductor buried layer 5 is set to a required value by adjusting the amount of impurities added to the P-type semiconductor buried layer 5.

As described above, by providing the protection circuit switching element of the semiconductor integrated circuit with the protection means against electrostatic breakdown, the electrostatic breakdown characteristics can be improved. However, when forming the above protection circuit, for example,
The process of forming the P-type semiconductor buried layer and the N-type semiconductor buried layer cannot be performed simultaneously with the normal PMOS and NMOS transistor manufacturing process, and must be added as an additional step, which causes an increase in LSI manufacturing cost. There is.

In addition to the use of such a protection MOS transistor, in the current wafer process, silicidation is performed for long-distance interconnections, and interconnection in a second-layer interconnection is performed using a gate material. A method of reducing connection resistance has been adopted. However, the reduction in the interconnect resistance in the second-layer wiring due to the silicidation is as follows.
This causes a reduction in the resistance of the drain region. In this state, when an excessive surge voltage is applied to the drain region, a current filament occurs in the drain region, and a partial breakdown occurs in a part of the drain region,
There is a problem that a sharp current flow and a temperature rise occur in this portion.

On the other hand, when salicidation is performed in a wafer process, a method of masking the drain region in the protection circuit and preventing salicidation only in the drain region has been proposed. In the method, a new mask is required, which leads to an increase in LSI manufacturing cost, which is a serious problem for LSI development.

Therefore, it is possible to prevent an electrostatic breakdown of a gate oxide film or the like due to an excessive surge voltage externally input to the protection circuit, prevent a current filament from being generated due to an excessive surge current, and reduce an excessive surge current. An electrostatic discharge protection circuit that can be quickly released
It is desired to manufacture the S transistor without adding an additional step to the manufacturing process.

[0015]

According to the present invention, a second conductive type first semiconductor region and a second conductive type second semiconductor formed at a predetermined interval on a surface of a first conductive type semiconductor substrate. Region, a field oxide film, and a second conductivity type third semiconductor region separated from the second conductivity type second semiconductor region by the field oxide film.
By providing a semiconductor region, there is provided an electrostatic discharge protection element composed of three or more types of bipolar transistors which parasitically occur inside the semiconductor substrate.

A gate insulating film formed on the first conductivity type semiconductor substrate; a gate electrode formed on the gate insulating film and having a sidewall spacer on a side wall; a field oxide film; A second conductivity type first semiconductor region formed on both sides of the gate electrode;
A semiconductor region, a second conductivity type third semiconductor region separated by the field oxide film from the second semiconductor region, and a region below the gate electrode and adjacent to the first or second semiconductor region. Fourth and fifth semiconductor regions of the first conductivity type, a sixth semiconductor region of the first conductivity type formed independently of the first to fifth semiconductor regions, and the first, third or sixth semiconductor region A first, a second, and a third electrode formed on the substrate; and a static transistor having three or more types of bipolar transistors parasitically generated inside the substrate by the substrate and the first, second, and third semiconductor regions. An electrical breakdown protection element is provided.

Further, the semiconductor device includes any one of the above electrostatic discharge protection elements formed on the same semiconductor substrate and at least a MOS transistor of the first conductivity type, and wherein the first, second and third semiconductor regions are formed of the MOS transistor. A semiconductor integrated device formed by the same process as a source / drain region of a transistor is provided.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An electrostatic discharge protection device according to the present invention mainly comprises a semiconductor substrate of a first conductivity type and a first semiconductor region of a second conductivity type formed on the surface of the substrate at a predetermined interval. And a second conductive type second semiconductor region, a field oxide film, and a second conductive type third semiconductor region separated from the second conductive type second semiconductor region by the field oxide film. The electrostatic discharge protection element having such a configuration is
Within the substrate, three or more types of bipolar transistors are generated parasitically by the substrate, the first to third semiconductor regions, and the like, and a high surge voltage and / or surge current due to static electricity is externally applied by utilizing the current driving capability of the bipolar transistor. Can be released.

Although the present invention has been described using P-type and N-type, when the first conductivity type is N-type and the second conductivity type is P-type, the first conductivity type is P-type. This includes both cases where the two conductivity types are N-type. The semiconductor substrate according to the present invention has one of a P-type and an N-type conductivity as usually used in a semiconductor device, and the entire surface of the semiconductor substrate may have any conductivity type. One or more P-type or N-type impurity regions (wells) may be formed in a desired region, and the electrostatic discharge protection element of the present invention may be formed in this impurity region.

In the electrostatic discharge protection device according to the present invention, at least three types of parasitic bipolar transistors are formed between the substrate and each semiconductor region by the N-type first to third semiconductor regions formed in the P-type substrate. It is composed. That is, the N-type third
Semiconductor region (collector) -substrate (base) -N-type second semiconductor region (emitter), N-type third semiconductor region (collector) -substrate (base) -N-type first semiconductor region (emitter), N-type second At least 3 of semiconductor region (collector) -substrate (base) -N-type first semiconductor region (emitter)
A kind of bipolar transistor is formed and constituted.

The field oxide film constituting the electrostatic discharge protection device of the present invention has a thickness of, for example, about 1500 to 7000 °, which is a known LOC.
It can be formed in a desired region by the OS method. When the element is finally formed, the field oxide film separates / insulates the second semiconductor region and the third semiconductor region, and may be formed at a position where the function is performed. is necessary. Further, since the field oxide film separates the second semiconductor region and the third semiconductor region as described above, the field oxide film is formed so that the second semiconductor region and the third semiconductor region are engaged with each other in a key shape. When they are arranged close to each other, they can have various shapes such as a plan view, a U-shape, and a polygon in order to realize such an arrangement.

In the present invention, the N-type first and second semiconductor regions are independently formed at a predetermined interval. The third semiconductor region is formed separately from the second semiconductor region via the field oxide film as described above. The size and junction depth of these semiconductor regions are not particularly limited, and can be appropriately adjusted depending on the size, drive capability, applied voltage, and the like of the finally obtained semiconductor integrated device. These semiconductor regions can be formed by introducing an impurity having a conductivity type of either P-type or N-type such as phosphorus, arsenic, or boron by a known method such as ion implantation. The ion implantation at this time may be formed using, for example, a mask having a desired opening,
An electrode layer or the like having a desired width may be formed in advance and formed using the electrode layer as a mask. The impurity concentration is not particularly limited as long as it can function as a collector, an emitter, or the like of a bipolar transistor that occurs parasitically. For example, the impurity concentration is 10 ²⁰ ions / c.
m ³ order.

The surfaces of the first to third semiconductor regions may be salicidated. When salicidation is performed as described above, the sheet resistance of each region can be reduced. Examples of the metal used for salicidation include refractory metals such as tungsten, titanium, and tantalum. Further, it is preferable that first to third electrodes are formed on the first to third semiconductor regions so as to be connected to various terminals and the like. These electrodes are formed of a conductive material that can be generally used for a wiring layer, a terminal, and the like in a semiconductor device or the like, and can be formed in a desired shape and size. For example, aluminum, copper, silver, platinum and the like can be mentioned. Further, among the semiconductor regions on which the electrodes are formed, the third semiconductor region is connected to the signal input terminal. The first semiconductor region is
It may be connected to a substrate voltage (GND) or a power supply voltage so that a high voltage or a high current applied by static electricity can be released to the outside, and it is particularly preferable to be connected to GND.

The semiconductor substrate (well) is also provided with a power source, a G
It is preferable that the P-type sixth semiconductor region is formed in the vicinity of the electrostatic discharge protection element, has the same conductivity type as the substrate (well), and is a high-concentration region. Is preferred. With this semiconductor region, the substrate (well) can be reliably connected to the substrate voltage. At this time, the P-type impurity concentration is set to 1 by boron or the like.
The order of 0 ²⁰ ions / cm ^{3 is} exemplified.

In the electrostatic discharge protection device of the present invention, an optimum circuit configuration is obtained by changing the connection method between the first to third semiconductor regions and the power supply voltage, substrate voltage, signal input terminal and the like. Can be. Further, in the present invention, a gate electrode having a sidewall spacer may be formed on the semiconductor substrate between the first and second semiconductor regions with a gate insulating film interposed therebetween. By using this gate electrode (sidewall spacer) as a mask when forming the first and second semiconductor regions at a predetermined interval, the formation positions of these regions can be strictly controlled. Further, when the gate electrode is connected to the substrate voltage, the leakage current of the electrostatic discharge protection device can be reduced, and a more effective electrostatic discharge protection device can be obtained.

In the present invention, the fourth and fifth semiconductor regions of the first conductivity type are formed between the first and second semiconductor regions and at positions adjacent to the first or second semiconductor regions. You may. These fourth and fifth semiconductor regions function to alleviate the electric field concentration at the ends of the first and second semiconductor regions, and are provided between the first semiconductor region and the substrate or between the second semiconductor region and the substrate. This is effective for stabilizing the threshold voltage. The fourth and fifth semiconductor regions are doped with impurities of the same conductivity type as the substrate, for example, 10 ¹⁸ io.
It is preferable to have a concentration on the order of ns / cm ³ . The fourth and fifth semiconductor regions can be formed in a self-aligned manner using the gate electrode as a mask when forming the gate electrode, for example.

The electrostatic discharge protection device having the above configuration is
Substantially the same process can be used to form the source / drain regions of the MOS transistor and the like. For example, in the case of a semiconductor integrated device having the electrostatic breakdown protection element of the present invention and at least an N-type MOS transistor on the same semiconductor substrate, the source / source of the MOS transistor
The first to third semiconductor regions can be formed by the same process as the ion implantation for forming the drain region.
In particular, in the present invention, when forming a gate insulating film, a gate electrode and the like, a gate insulating film of a MOS transistor,
In the same process as the formation of the gate electrode, etc., using the same material,
It can be formed similarly.

Hereinafter, embodiments of the semiconductor integrated device of the present invention will be described in detail. The semiconductor integrated device in this embodiment has the electrostatic discharge protection circuit shown in FIG. 1, and this electrostatic discharge protection circuit constitutes a punch-through device by combining a bipolar transistor and a parasitic resistance, which will be described later. This punch-through device snaps
By applying the back characteristic, an abnormal excessive voltage and excessive current flowing through the PAD from the outside are discharged and discharged to the outside, thereby protecting the LSI circuit from electrostatic breakdown.

As shown in FIG. 1, the electrostatic discharge protection circuit mainly includes N-type semiconductor regions 29 and 31 formed on the surface of a P-type semiconductor substrate 30 at a desired interval.
An N-type semiconductor region 19 insulated and separated from the N-type semiconductor region 29, a field oxide film 24 for insulating and separating the N-type semiconductor regions 29 and 19, and a substrate 30 P-type semiconductor region 18N that reliably connects to substrate voltage, first electrode 26 connected to type semiconductor region 29, and second electrode 27 connected to N-type semiconductor region 19
And a third electrode 28 connected to the P-type semiconductor region 18. The gate insulating film 2 is formed on the substrate 30.
5, a gate electrode 22 having a sidewall spacer 23 is formed. The gate electrode 22 is located below the sidewall spacer 24 and adjacent to the N-type semiconductor regions 29 and 31 respectively. P-type semiconductor regions 20 and 21 for stabilizing a threshold voltage between 30 and 30 are formed.

According to the electrostatic discharge protection circuit having such a configuration, the N-type semiconductor region 29, the substrate 30, and the N-type semiconductor region 31, and the N-type semiconductor region 31, the substrate 30,
The N-type semiconductor region 19 further allows the N-type semiconductor region 2
9, substrate 30, and N-type semiconductor region 19,
A PN bipolar transistor is formed parasitically (see FIG. 2B). Since these bipolar transistors are excellent in current driving capability, when an abnormal excessive voltage or excessive current is input from the outside into the LSI due to static electricity, the bipolar transistors are operated to quickly remove the excessive voltage. It can be discharged to the outside, and an abnormal excessive current can be discharged to the outside. Therefore, the gate oxide film breakdown of the internal circuit inside the LSI and P
N-junction breakdown can be prevented, and the electrostatic breakdown voltage of the LSI can be improved.

In the above electrostatic discharge protection circuit, even if, for example, the N-type semiconductor regions 19, 31 and the like are reduced in resistance by salicidation, these N-type semiconductor regions 19, 31
1 is better than the drain region of the MOS transistor.
A substrate 30 as a base, an n-type semiconductor region 31 as an emitter,
It operates as a parasitic bipolar transistor having the type semiconductor region 19 as a collector. Therefore, even if an abnormal excessive voltage or excessive current is input from the PAD, the bipolar transistor is turned on, so that an abnormal excessive current is released from the substrate 30 to the substrate voltage GND side through the P-type semiconductor region 18. Thus, it is possible to prevent the local destruction of the drain region due to the local concentration of pinpoint current caused by the generation of a current filament in the drain region, which has conventionally been a problem.

Further, the electrostatic discharge protection circuit having the above-described structure includes N-type semiconductor regions 19, 29, 31 and P
Forming the first semiconductor region 18 and forming the first, second and third electrodes 2
6, 27 and 28 are only formed, so that a normal CM
They can be formed at the same time without performing an additional step in the OS step, and increase in manufacturing cost can be suppressed. FIG. 2A is an equivalent circuit diagram illustrating how a parasitic bipolar transistor and a parasitic resistance constitute an electric circuit in the electrostatic breakdown protection circuit having the above-described structure. FIG. FIG. 3 shows where the parasitic bipolar transistor and the parasitic resistance in FIG. 2A are configured.

As shown in FIGS. 2A and 2B, in the electrostatic discharge protection circuit, the N-type semiconductor region 19 operates as a collector, the substrate 30 operates as a base, and the N-type semiconductor region 31 operates as an emitter. Bipolar transistor Q2, N-type semiconductor region 31 functions as a collector, substrate 30 functions as a base, N-type semiconductor region 29 operates as an emitter, and bipolar transistor Q1, N-type semiconductor region 19 functions as a collector, substrate 30 as a base, and N-type semiconductor region 29 as a base. Bipolar transistor Q3 operating as an emitter, N-type semiconductor region 29, N
It is composed of parasitic resistances R1, R2, R3 formed by optimizing the substrate resistance by changing the distance between the type semiconductor region 31 and the N-type semiconductor region 19.

In such an electrostatic breakdown protection circuit,
When a surge voltage is externally applied to the PAD due to static electricity, the N-type semiconductor region 19 operates as a collector of the parasitic bipolar transistors Q3 and Q2, as shown in the graph showing the snap-back characteristic of FIG. Until the breakdown voltage Vb is reached, the parasitic bipolar transistors Q2 and Q3 are off.

On the other hand, when the breakdown voltage Vb is exceeded, the collector junction formed between the N-type semiconductor region 19 and the substrate 30 breaks down, turning on the two bipolar transistors Q2 and Q3, and further turning on the bipolar transistors. Q1 is also turned on, and current starts to flow through these bipolar transistors Q1, Q2, Q3. Further, since this current flows through the parasitic resistances R2 and R3, the current flows between the collector and the emitter of the parasitic bipolar transistors Q2 and Q3, that is, the substrate 30 serving as the base region.
(This state shows a current-voltage characteristic between the breakdown voltage Vb and the switching voltage Vs shown in FIG. 3). The parasitic resistance is called a shunt resistance in the configuration of the punch-through device, and is a resistance necessary for maintaining the base potential. This resistance is very important for generating a snap-back characteristic.

That is, the bipolar transistors Q2, Q
3 is the base-emitter voltage (substrate 30
And N-type semiconductor region 31, substrate 30 and N-type semiconductor region 29
When the forward breakdown voltage reaches about 0.7 V, the minority carriers (electrons in FIG. 7) from the N-type semiconductor region 31 and the N-type semiconductor region 29 serving as the emitter regions of the parasitic bipolar transistors Q2 and Q3. Is started to be injected into the substrate 30 serving as the base region. At this time, due to the impact ionization in the depletion layer at the collectors of the bipolar transistors Q2 and Q3 due to minority carriers, the resistance R
2. Holes flow into R3, which become hole currents, further increasing the base potential, generating positive feedback, causing a sharp increase in minority carrier injection and current. This is the transition to the ON state, and this state indicates the negative resistance region from the first breakdown to the holding voltage Vh shown in FIG. 3, and at this time, the state is the negative resistance.

In the ON state, the base potential can be maintained in the forward bias only by the injection current of the minority carriers from the emitter. Therefore, the voltage applied to the PAD from the outside does not need to be further applied, and the negative resistance is not required. In order to maintain the state, the voltage apparently drops below the switching voltage, and a negative resistance region called a snap-back characteristic is formed.

At this time, when the parasitic bipolar transistor Q2 is turned on, a current also flows into the parasitic bipolar transistor Q1 connected thereto, and this Q1 is also turned on. When Q1 is turned on, the substrate 30 operates as a base, but the base potential is maintained by the parasitic resistance R1, and minority carriers are injected into the base from the N-type semiconductor region 29 which is an emitter. The region 31 serves as a collector in this case, and ionization collision occurs in a depletion layer at the collector junction. Therefore, a hole-electron pair is generated, and the hole flows out through the parasitic resistance R1. Therefore, due to the hole current caused by this hole,
The base potential of Q1 will further rise, and the current-
The voltage characteristic indicates positive feedback, and indicates the negative resistance characteristic described above.

Therefore, the current can flow rapidly in Q1 as well as in Q2 and Q3. Further, since Q1 and Q2 are connected in series, the substrate voltage GND passes through two paths such as Q3 and Q2 and Q1 connected in series.
An abnormal excessive current can be quickly discharged to the side, and the electrostatic discharge protection ability can be enhanced. The gate voltage Vg applied to the gate electrode shown in FIG. 1 can be connected to the substrate voltage GND to reduce the leakage current of the electrostatic discharge protection circuit. It will be more effective.

In the above-described electrostatic breakdown protection circuit, the surge current input from the outside is the same as the substrate voltage G
Although the structure is such that the light is emitted to the ND side, it can be emitted to the power supply voltage Vdd side instead of the substrate voltage GND by changing the connection method of each element. Further, since the P-type semiconductor region 18 is formed to connect the substrate 30 to the substrate voltage, by connecting this P-type semiconductor region to the substrate voltage, the P-type semiconductor region 18 shown in FIGS. The emitter and resistance of the parasitic bipolar transistor can be connected to the substrate voltage GND.

Next, the snap-back characteristic shown in FIG. 3 will be described. As described above, when the collector voltage is gradually applied to the punch-through device, breakdown occurs at the collector junction, and current starts to flow. The voltage that causes this breakdown is the breakdown voltage Vb. When the collector voltage is further applied beyond this voltage, the voltage reaches a fast breakdown voltage, generally called a switching voltage Vs.

When the switching voltage is reached, a negative resistance is generated, as described above, and the current-voltage characteristic exhibits a feedback characteristic. When the collector voltage is further applied beyond the switching voltage, impact ionization increases in the collector depletion layer and avalanche is generated, so that the current rapidly increases. This is a voltage called the holding voltage Vh.

In FIG. 3, the first and second breakdowns are described.
In the back characteristic, it is necessary that the second breakdown occurs at a higher voltage than the first breakdown. This is because if the second breakdown voltage is lower than the first breakdown voltage, the first breakdown is in the electrostatic breakdown mode, and electrostatic breakdown occurs in the first breakdown (2).
Discharging an abnormally large current to the GND side through the path is not realized). Therefore, when trying to perform electrostatic breakdown protection by the snap-back characteristic, it is necessary to design a protection circuit so that the second breakdown occurs at a higher voltage than the first breakdown. , It has been realized.

The process for implementing the above protection circuit is a deep submicron level miniaturization process.
In this process, the gate insulating film is becoming thinner and thinner, which causes a decrease in the gate oxide film breakdown voltage. Although the above-described snap-back characteristic is suitable for emitting an excessively large abnormal current, in a deep submicron level miniaturization process, the gate oxide film breakdown voltage Vox is lower than the PN junction breakdown voltage. Therefore, it is necessary to operate a punch-through device as an electrostatic protection element at a voltage equal to or lower than the gate oxide film breakdown voltage, and to quickly discharge and release an excessive abnormal voltage and abnormal current input from the PAD to the outside. However, at this time, the punch-through device as an electrostatic protection element is required to operate at a voltage higher than the power supply voltage and lower than the gate oxide film breakdown voltage.

This is for the following reason. That is, normally, an internal circuit operates when a power supply voltage is applied from the outside to the LSI. However, an input signal that can be input from the outside to the inside of the LSI through the PAD is also electrically connected to the LSI. Depending on specifications, power supply voltage Vcc ± 5% to 10% or power supply voltage Vcc ±
The amplitude voltage is specified as 0.1 Vcc or the like. Therefore, if a signal is input from the outside into the LSI through the PAD, and the electrostatic protection circuit operates at a voltage lower than the amplitude voltage of the signal input defined by the electrical specifications, the electrical When the power supply voltage is applied to the LSI according to the specifications and the LSI is operated in the normal operation mode, the input signal is discharged from the PAD to the outside through the substrate voltage GND, and the voltage and the current are applied to the inside of the LSI. Therefore, the LSI cannot be used in the normal operation mode.

To prevent this, as described above, the PAD
Does not operate when the signal voltage input into the LSI through the IC is less than or equal to the amplitude of the signal input defined by the electrical specifications, the voltage is higher than the power supply voltage defined by the electrical specifications, and the gate oxide film To operate at a voltage lower than the gate oxide film breakdown voltage,
That is, it is required to configure an electrostatic discharge protection circuit whose operating conditions are severely restricted.

At the deep submicron level,
The thickness of the gate oxide film is about 50 °, the withstand voltage of the oxide film is about 5 V, and the power supply voltage is about 2.5 V ± 10%. Very difficult. On the other hand, in the above electrostatic discharge protection circuit, the structure shown in FIG. 1 and FIGS.
By constructing a circuit configuration, it is possible to satisfy all the required severe operating conditions.

The ESD protection circuit of the present invention shown in FIG. 1 is a protection circuit suitable for a deep submicron level low voltage and a low gate oxide film breakdown voltage. The result of studying the protection circuit structure will be described with reference to FIG. At this time, the process conditions for device simulation
The gate oxide film 25 has a thickness of 50 °, the thickness of the polysilicon constituting the gate electrode 22 is 1500 °, and the gate length is 0.4 μm.
m, the distance between the N-type semiconductor region 19 and the N-type semiconductor region 31 was 0.4 μm, and the thickness of the field oxide film was 3500 °. The N-type semiconductor regions 19, 29 and 31 were formed by implanting arsenic ions and then annealing to diffuse them into the substrate. Further, the P-type semiconductor region 2
0 and 21 were formed by implanting boron ions into the gate electrode 22 in a self-aligning manner and diffusing the ions into the substrate by annealing.

As described above, in the process of the deep submicron level, the gate oxide film breakdown voltage is about 5 V and the power supply voltage is about 2.5 V ± 10%, but as shown in FIG. According to the device simulation of the electrostatic discharge protection circuit, the switching voltage is about 3.5.
V and the holding voltage are about 2.2V. Therefore,
Gate oxide film breakdown voltage of about 5 V or less, power supply voltage of 2.5 V
It can be seen that the snap-back characteristic is generated at a voltage of about ± 10% or more, and that the circuit is a good electrostatic discharge protection circuit in the deep submicron process.

The relationship between the first breakdown and the second breakdown required for the electrostatic breakdown protection circuit is shown in FIG. 4 from the tendency of the current-voltage characteristic with respect to the first breakdown. It can be seen that the voltage is higher than the first breakdown. As described above, the electrostatic discharge protection circuit according to the above embodiment satisfies the condition for preventing the electrostatic discharge damage in the breakdown, and as the electrostatic discharge protection circuit at the deep submicron process level,
Not only is it very effective, but it also has a very high electrostatic discharge protection capability.

Next, another embodiment of the semiconductor integrated device of the present invention will be described. In this embodiment, the structure of the semiconductor region itself is the same as that of the above embodiment, but the layout of the emitter region of the parasitic bipolar transistor is changed to improve the electrostatic discharge protection capability. is there. In the plan view shown in FIG. 5, the configuration is basically the same as that of the electrostatic discharge protection circuit of FIG. 1, but the layout patterns of the N-type semiconductor region 19 and the N-type semiconductor region 31 are engaged in a key shape. It is different from the above embodiment in that it is formed as described above.

Usually, in a bipolar transistor, the optimum current range in which the current gain β is maximized is related to the planar dimensions of the device, particularly the emitter area. In particular, at a high current, the emitter efficiency is reduced because a large amount of excess minority carriers are accumulated in the base, and the effective base specific resistance βb near the base-emitter junction is reduced. Also, due to the emitter concentration effect, the emitter end is biased more forward than the bottom of the emitter region, so that only the emitter end is electrically activated. Therefore, in order to prevent the base specific resistance βb from decreasing at a high current, it is necessary to increase the ratio between the emitter circumference and the emitter area as much as possible and to reduce the base spreading resistance.

In the layout of FIG. 5, the corners of the N-type semiconductor region 31 functioning as an emitter are eliminated, and the N-type semiconductor region 19 functioning as a collector is engaged with the N-type semiconductor region 31 in a key shape, so that the N-type semiconductor region 31 is formed in the base. Can be prevented from being concentrated, and the effective base specific resistance βb in the vicinity of the base-emitter junction can be prevented from decreasing. In addition, since the corners of the N-type semiconductor region 19 are eliminated, the electric field concentrated on the corners can be reduced, and there is also an effect of preventing electrostatic breakdown in the collector.

As described above, in this electrostatic discharge protection circuit, it is possible to effectively prevent electrostatic discharge at the deep submicron process level and to form an optimum pattern shape according to the wafer process. It is possible.

[0055]

According to the present invention, an electrostatic discharge protection element can be formed by utilizing three or more types of parasitic bipolar transistors generated inside a semiconductor substrate and first to third semiconductor regions. LSI from outside by static electricity
If abnormal excessive voltage or excessive current is input inside,
By operating the bipolar transistor, an excessive voltage can be rapidly discharged to the outside, and an abnormal excessive current can be discharged to the outside.

Further, in the miniaturization process at the deep submicron level, even if the gate insulating film is made thinner and the withstand voltage of the gate insulating film is lowered, it is possible to operate sufficiently at a voltage lower than the withstand voltage of the gate insulating film. Even when the power supply voltage is lowered, the overvoltage and / or the overcurrent due to static electricity do not operate unless the voltage is equal to or higher than the power supply voltage, which is effective in a low voltage process.

Accordingly, it is possible to obtain a highly reliable electrostatic breakdown protection element which prevents the breakdown of the gate oxide film and the PN junction of the internal circuit inside the LSI and improves the electrostatic breakdown withstand voltage of the LSI. Can be. First,
When the surfaces of the second and third semiconductor regions are salicidated, the sheet resistance of each region can be reduced, and a current filament due to a decrease in drain resistance is not generated, and the electrostatic discharge protection element is not generated. Can be improved.

Further, when the second semiconductor region and the third semiconductor region are arranged close to each other via a field oxide film so as to mesh with each other in a key shape, a semiconductor functioning as an emitter of a parasitic bipolar transistor is provided. Since the peripheral length of the region and the area ratio can be increased, a larger current can flow and an abnormally high current input from the outside into the LSI due to static electricity can be quickly discharged.

In the case where the electrostatic breakdown protection element further includes a first conductivity type MOS transistor on the same substrate as the semiconductor substrate on which the element is formed, the second and third semiconductor regions are formed as follows. Can be formed in the same process as the source / drain regions of the MOS transistor, so that there is no additional process for forming an electrostatic discharge protection element, an increase in LSI manufacturing cost can be suppressed, and a cost-effective static It is possible to obtain a destruction protection element, and eventually a semiconductor integrated device.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a configuration of an electrostatic discharge protection circuit in a semiconductor integrated device of the present invention.

FIG. 2A is an equivalent circuit diagram of a parasitic element that realizes the electrostatic discharge protection circuit of FIG. 1, and FIG. 2B is a schematic diagram showing a correspondence between the configuration of the electrostatic discharge protection circuit and the parasitic element. is there.

FIG. 3 shows the characteristics of a snap through device
4 is a graph showing a back characteristic.

FIG. 4 is a diagram showing drain current-voltage characteristics when device simulation is performed on the structure of the electrostatic discharge protection circuit of FIG.

FIG. 5 is a schematic plan view of a main part showing another embodiment of the electrostatic discharge protection circuit in the semiconductor integrated device of the present invention.

FIG. 6 is an equivalent circuit diagram of a conventional protection circuit using a protection MOS transistor having a high electrostatic breakdown voltage.

FIG. 7 is a schematic sectional view showing the structure of a conventional electrostatic discharge protection circuit.

FIG. 8 is a schematic sectional view showing another structure of the conventional electrostatic breakdown protection circuit.

FIG. 9 is a schematic sectional view showing still another structure of the conventional electrostatic discharge protection circuit.

[Explanation of symbols]

18, 20, 21 P-type semiconductor region (second conductivity type semiconductor region) 19, 29, 31 N-type semiconductor region (first conductivity type semiconductor region) 22 Gate electrode 23 Side wall spacer 24 Field oxide film 25 Gate-insulating film 26 First electrode 27 Second electrode 28 Third electrode 30 P-type semiconductor substrate (second conductivity type semiconductor substrate) Q1, Q2, Q3 NPN bipolar transistors R1, R2, R3 Parasitic resistance M1 NMOS transistor GND Substrate voltage Vh Snap-back characteristics Holding voltage Vb Breakdown voltage in snap-back characteristics Vs Switching voltage in snap-back characteristics Vox Oxide withstand voltage in deep submicron process Vcc Power supply voltage in deep submicron process

Claims (6)

[Claims] A second conductive type first semiconductor region and a second conductive type second semiconductor region formed at predetermined intervals on a surface of the first conductive type semiconductor substrate; a field oxide film; It is characterized by comprising three or more types of bipolar transistors that are parasitically generated inside the semiconductor substrate by having the second conductive type third semiconductor region separated from the second conductive type second semiconductor region by an oxide film. ESD protection element. 2. The electrostatic discharge protection device according to claim 1, wherein the surfaces of the first, second and third semiconductor regions are salicided. 3. The electrostatic discharge protection device according to claim 1, wherein the third semiconductor region is connected to a signal input terminal, and the first semiconductor region and the semiconductor substrate are connected to GND. 4. A gate insulating film formed on a first conductivity type semiconductor substrate, a gate electrode formed on the gate insulating film and having a sidewall spacer on a side wall, a field oxide film, A second conductivity type first semiconductor region and a second semiconductor region formed on both sides of the gate electrode; a second conductivity type third semiconductor region separated from the second semiconductor region and the field oxide film; Fourth and fifth semiconductor regions of the first conductivity type formed in a region below the gate electrode and adjacent to the first or second semiconductor region, and are formed independently of the first to fifth semiconductor regions. The first conductive type sixth semiconductor region and the first, third or sixth semiconductor region.
The first, second, and third layers respectively formed on the semiconductor region.
An electrostatic discharge protection element comprising an electrode and three or more types of bipolar transistors parasitically generated inside the substrate by the substrate, the first, second, and third semiconductor regions. 5. The second semiconductor region and the third semiconductor region,
7. The electrostatic discharge protection device according to claim 6, wherein the protection device is disposed close to the key oxide via the field oxide film. 6. The semiconductor device according to claim 1, which is formed on the same semiconductor substrate and has at least a first conductivity type MOS transistor.
And a semiconductor integrated device in which a third semiconductor region is formed in the same step as a source / drain region of the MOS transistor.