JPH1166887A - Semiconductor storage device and readout method therefor and storage medium stored with the method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make the redundant bit added to the information bit very short and to efficiently and exactly perform error correction by making error correc tion on the assumption that error occurs in response to the first transition in the case where it is judged that the number of bits corresponding to the condition that charge is accumulated in the charge accumulation layer or the condition that charge is extracted is odd. SOLUTION: An EEPROM has a memory means composed of plural memory cells arranged in a matrix form and a readout means which selects two specified memory cells from the memory means, detects the bits stored in each memory cell to form a data string and corrects any error to output it. When a memory cell of EEPROM is deteriorated, compared with the probability that the condition that charge is accumulated in the floating gate 5 transits to the condition that the charge is extracted, the probability opposite to it is overwhelmingly small. The error of the readout data string is corrected by making use of the property peculiar to this non-volatile semiconductor memory device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device for storing a data string in which information bits are added with the same redundant bits as the information bits, a read method, and a storage medium storing the read method. .

[0002]

2. Description of the Related Art Generally, in a semiconductor memory device including a nonvolatile semiconductor memory device, when storing data is written in a memory cell array, the error correction data is added as redundant bits. Then, when the stored data is read from the memory cell array, the presence or absence of an error in the content is checked, and when the error is found, the error is corrected and output as read data. Normally, in this error correction, it is necessary to satisfy the following equation (1) in order to add m-bit error correction data to n-bit storage data to enable correction of a t-bit error.

[0003]

(Equation 1)

According to the equation (1), for example, in order to perform the most frequently occurring 1-bit error correction, assuming that t = 1, the m-bit error correction data satisfying the following equation (2) is set as follows: Addition is required.

[0005]

(Equation 2)

According to the equation (2), performing one-bit error correction on one-bit storage data requires two or more bits of error correction data. To perform one-bit error correction, three or more bits of error correction data are required.

[0007]

As described above, in order to perform one-bit error correction on storage data, error correction data longer than the storage data is required. It must be said that the efficiency is extremely poor.

Japanese Patent Laid-Open Publication No. Hei 6-282992 discloses a nonvolatile semiconductor memory device in which a parity bit is stored in a memory cell together with storage information to increase the memory capacity and improve data reliability. However, since the added bit is a parity bit, it is possible to efficiently determine whether or not an error has occurred, but this nonvolatile semiconductor memory device cannot perform error correction.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory device, a reading method, and a storage medium in which a reading method is stored, in which redundant bits added to information bits are made extremely short and error correction is performed efficiently and accurately. That is.

[0010]

A semiconductor memory device according to the present invention has a charge storage layer and a gate electrode. By applying a predetermined voltage to the gate electrode, a charge is stored in or extracted from the charge storage layer. Write information bits,
A semiconductor memory device comprising a plurality of semiconductor memories for reading out the information bits by judging a charge accumulation state in the charge accumulation layer, wherein the same redundant bits as the information bits are added to the information bits. With respect to a data string, each bit constituting the data string is written and read in correspondence with each of the semiconductor memories, and when reading the data string, charges are accumulated in the charge storage layer. The probability that a second transition that changes from a state where electric charges are extracted to a state where electric charges are extracted is negligibly small compared to the probability that a first transition that changes from a state where the electric charge is extracted to a state where the electric charge is extracted will occur. In the data sequence, the number of bits corresponding to the state in which the charge is stored in the charge storage layer or the state in which the charge is extracted is an odd number. And if it is determined, performs error correction and regarded as an error occurs in response to the first transition.

In one embodiment of the semiconductor memory device according to the present invention, a third transition in which at least two bits of the data sequence change from a state in which charges are stored in the charge storage layer to a state in which charges are withdrawn is included. Is also negligible compared to the probability of occurrence of the first transition as in the case of the second transition, and charges are stored in the charge storage layer in the data sequence. If it is determined that the number of bits corresponding to the state or the state from which the charge has been extracted is an odd number, it is considered that an error has occurred in only one bit corresponding to the first transition, and error correction is performed. Do.

In one embodiment of the semiconductor memory device of the present invention, the semiconductor memory includes a floating gate as the charge storage layer and a control gate as the gate electrode.

In the semiconductor memory device of the present invention, a plurality of memory cells each having a charge storage layer and a gate electrode are arranged in a matrix, and an information bit having a predetermined value and the same redundant bit as the information bit are added. A storage unit in which each bit constituting a data string is stored in each of the memory cells, and a predetermined memory cell is selected from the storage unit, and the bit stored in each of the memory cells is selected. To form the data string, and store the charge from the state in which the charge is withdrawn compared to the probability that the first transition that changes from the state in which the charge is stored in the charge storage layer to the state in which the charge is withdrawn occurs. Utilizing the fact that the probability of the occurrence of the second transition to the changed state being negligible is negligible, and the charge is stored in the charge storage layer of each of the memory cells in the data string. Alternatively, when it is determined that the number of bits corresponding to the state in which the electric charge has been extracted is an odd number, it is considered that an error has occurred in response to the first transition, and error correction is performed and output is performed. Means.

In one embodiment of the semiconductor memory device according to the present invention, the read means changes at least two bits of the data sequence from a state where charges are stored in the charge storage layer to a state where the charges are extracted. The probability that the third transition occurs is also negligibly small compared to the probability of occurrence of the first transition similarly to the second transition. When it is determined that the number of bits corresponding to the state where the charge is accumulated or the state where the charge is removed is an odd number, it is considered that only one bit has an error corresponding to the first transition. Error correction.

In the semiconductor memory device according to the present invention, the memory cell has a semiconductor element in which a floating gate is provided as the charge storage layer and a control gate is provided as the gate electrode.

According to a read method of a semiconductor memory device of the present invention, a charge storage layer and a gate electrode are provided, and by applying a predetermined voltage to the gate electrode, charges are stored in or extracted from the charge storage layer to store information bits. Write,
A method for reading a semiconductor memory device comprising a plurality of semiconductor memories for reading out the information bits by determining an accumulation state of charges in the charge accumulation layer, wherein each of the semiconductor memories includes the information bits in the information bits. In the data string to which the same redundant bits are added, a predetermined one bit of each bit constituting the data string is stored. When the stored data string is read, the charge accumulation Probability that a second transition that changes from a state where charge is extracted to a state where charge is stored is generated compared to a probability that a first transition that changes from a state where charge is stored in the layer to a state where the charge is extracted occurs. Utilizing the fact that is negligibly small, the number of bits corresponding to the state in which the charge is stored in the charge storage layer or the state in which the charge is extracted in the data string is If it is determined that the few, performs error correction and regarded as an error occurs in response to the first transition.

In one embodiment of the reading method of the semiconductor memory device according to the present invention, the data string is changed from a state where charges are stored in the charge storage layer to a state where the charges are extracted for at least two bits of the data string. The probability that the transition 3 occurs is also negligibly small compared to the probability of the first transition as in the case of the second transition, and the charge is stored in the charge storage layer in the data sequence. If it is determined that the number of bits corresponding to the accumulated state or the state from which the electric charge has been extracted is an odd number, one bit corresponds to the first transition.
Error correction is performed on the assumption that an error has occurred only in the bits.

In one embodiment of the reading method of the semiconductor memory device according to the present invention, the semiconductor memory comprises a floating gate as the charge storage layer and a control gate as the gate electrode.

According to a method of reading a semiconductor memory device of the present invention, a charge storage layer and a gate electrode are provided. By applying a predetermined voltage to the gate electrode, charges are stored in or extracted from the charge storage layer, and information bits are extracted. Write,
A method for reading a semiconductor memory device including a plurality of semiconductor memories for reading the information bits by determining a charge storage state of the charge storage layer, wherein the charge is stored in the charge storage layer of the semiconductor memory. State
1 "; the state in which the charge has been extracted is" 0 "; and the semiconductor memory has a predetermined 1 of a predetermined number of bits constituting a data string in which the same redundant bits as the information bits are added to the information bits. Each bit is stored, each bit is read from each of the semiconductor memories, and the first step of forming the data string and the number of “0” or “1” in the data string are counted. A second step, a third step of determining the evenness of the counted number, and a fourth step of outputting the data string without correction when the third step determines that the number is even. And a fifth step of determining, in the third step, a different bit between the information bit and the redundant bit in the data string if it is determined to be an odd number; Among the bits determined in the fifth step, and a sixth step of outputting the corrected to "0" is toward the "1".

A read method of a semiconductor memory device according to the present invention has a charge storage layer and a gate electrode, and stores or extracts a charge in the charge storage layer by applying a predetermined voltage to the gate electrode to store information bits. Write,
A method for reading a semiconductor memory device including a plurality of semiconductor memories for reading the information bits by determining a charge storage state in the charge storage layer, wherein a state in which charges are stored in the charge storage layer is defined as " 1 "; the state in which the charge has been extracted is" 0 "; and the semiconductor memory has a predetermined 1 of a predetermined number of bits constituting a data string in which the same redundant bits as the information bits are added to the information bits. A first step of reading each bit from each of the semiconductor memories to form the data string; and "0" or "0" in the data string.
A second step of counting the number of 1 ", a third step of determining whether the counted number is even or odd, and correcting the data string if the third step determines that the number is even. And a fifth step of correcting and outputting the data string to "11" when it is determined that the data string is odd in the third step.

According to a read method of a semiconductor memory device of the present invention, a charge storage layer and a gate electrode are provided, and by applying a predetermined voltage to the gate electrode, charges are stored in or extracted from the charge storage layer to store information bits. Write,
A method for reading a semiconductor memory device including a plurality of semiconductor memories for reading the information bits by determining a charge storage state in the charge storage layer, wherein a state in which charges are stored in the charge storage layer is defined as " 1 ", the state where the charge is extracted is" 0 ", and the semiconductor memory forms a 4-bit data string in which the same two redundant bits as the information bits are added to the two information bits. A predetermined one bit of the bits to be stored, a first step of reading out the data string, a second step of counting the number of "1" in the data string, A third step of judging the number of odds and odds, and a fourth step of outputting the data string without correction when it is judged that the number is even in the third step; A fifth step of determining whether the number is one or three when it is determined in step 3 that the number is an odd number, and the data string is determined when the number is three in the fifth step. A sixth step of correcting the data to "1111" and outputting the data, and if it is determined that the number is one in the fifth step, the position is either an even position or an odd number when viewed from the most significant bit in the data string. A seventh step of determining whether the data string is a position, and when the seventh step determines that the data string is an even number position, the data string is set to "10".
An eighth step of correcting the output to 10 "and outputting
And a ninth step of correcting the data string to "0101" and outputting the corrected data string when it is determined that the data string is an odd-numbered position.

In one embodiment of the reading method of the semiconductor memory device according to the present invention, the semiconductor memory comprises a floating gate as the charge storage layer and a control gate as the gate electrode.

In the storage medium storing the read method of the semiconductor storage device of the present invention, the first to sixth steps constituting the above read method are stored so as to be readable by a computer.

In the storage medium storing the read method of the semiconductor memory device of the present invention, the first to fifth steps constituting the above read method are stored so as to be readable by a computer.

In the storage medium storing the read method of the semiconductor memory device of the present invention, the first to ninth steps constituting the above read method are stored so as to be readable by a computer.

[0026]

Normally, in a volatile semiconductor memory device such as a DRAM, a first transition from a state where electric charges are accumulated in a charge accumulation layer of each semiconductor memory to a state where the electric charges are drawn out,
The second transition that changes from the state in which the charge is extracted to the state in which the charge is stored occurs with almost equal probability. On the other hand, EEPRO
In a nonvolatile semiconductor memory device such as M, the probability that the second transition occurs will be negligibly small compared to the first transition. Furthermore, the probability of the occurrence of the third transition in which the state is changed from the state in which the charge is stored in the charge storage layer to the state in which the charge is extracted is the same as that of the second transition for two or more bits in the data string. In the present invention, the probability of occurrence of the first transition is so small that it can be ignored.

More specifically, the same redundant bits as those of the information bits are added to the information bits.
Writing and reading are performed using a data string having twice the number of bits. Then, when reading this data string,
An error occurring in the data sequence is regarded as having occurred in response to the first transition, and is preferably corrected in consideration of the third transition. That is, when the possibility of the second transition and the third transition is excluded and only the possibility of the first transition is considered, the electric charge is stored in the charge storage layer of each semiconductor memory among the bits constituting the data string. The accumulated state (for example, "
1 ”) or an odd number of bits (that is, the number of“ 1 ”or“ 0 ”) corresponding to the state where the charge is extracted (for example,“ 0 ”), an error occurs in the data string. Is determined, the bit corresponding to the first transition is corrected (in the above example, corrected from "0" to "1") and output.

As described above, in the present invention, a data string is created by adding the same redundant bits as the information bits to the information bits, and writing and reading are performed on the semiconductor memory device using the data strings. It is possible to easily and accurately perform error correction at the time of reading in consideration of only the transition of 1.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Some preferred embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) First, a first embodiment will be described. In the first embodiment, a binary (1 bit) information bit is stored in an EEPROM which is a nonvolatile semiconductor memory device capable of storing binary (= 1 bit) information in each memory cell. A data string (2 bits) in which binary (1 bit) redundant bits for error correction are added to
The case of performing writing and reading of (bit) will be exemplified. FIG. 1 is a schematic sectional view showing a main configuration of each memory cell constituting the EEPROM of the first embodiment,
FIG. 2 is a schematic diagram showing how an error occurs based on the transition probability, and FIG. 3 is a flowchart for performing error correction at the time of reading.

In the EEPROM of the first embodiment, a memory means in which a plurality of memory cells are arranged in a matrix, and two predetermined memory cells are selected from the memory means and stored in each memory cell. It has a reading means (not shown in the drawing similar to the overall structure of the storage means) for detecting a bit to form a data string, correcting and outputting an error as described later. ing.

Each memory cell constituting the storage means is shown in FIG.
As shown in FIG. 1, on a p-type silicon semiconductor substrate 1, phosphorus (P) or arsenic (A) is formed on a surface region of an element active region 2 defined by an element isolation structure such as a field oxide film.
a source 3 and a drain 4 which are a pair of impurity diffusion layers formed by ion implantation of n-type impurities such as s) and a channel region C between the source 3 and the drain 4 via a tunnel oxide film 7 A floating gate electrode 5 serving as a patterned electron capture layer; and a dielectric film 8 on the floating gate electrode 5.
And a control gate electrode 6 which is patterned through the control gate electrode 6.

Then, a predetermined voltage is applied to the selected memory cell from the write means to the source 3, drain 4, and control gate electrode 6, and the floating gate electrode 5
Or the charge is extracted from the floating gate electrode 5 to change the storage state.

In each memory cell, the state where charge is stored in the floating gate electrode 5 is “1”, and the floating gate electrode 5
Is defined as "0". This EEPROM has two memory cells M1, M
2 as one unit, writing a binary (“00”, “11”) data string and quaternary (“00”, “01”, “1”)
0 ”,“ 11 ”) can be read.
That is, in one unit, the storage data "0" and "1" are written to one memory cell M1 and defined as upper bits, and the same redundant bit as the storage data is corrected in the other memory cell M2. The data is defined as lower bits, and one of the data strings ("00", "11") is constituted by the two memory cells M1 and M2 forming one unit. On the other hand, at the time of reading, the data string ("00", "0") is considered in consideration of the case where an error occurs in the bits forming the data string as described later.
1 "," 10 "," 11 ") is possible,
If it is determined that there is an error, it is corrected and output as described later.

Here, when the memory cell is deteriorated due to repeated use of the EEPROM, data may be garbled in the memory cell. Compared to the probability of transition from the state where charges are accumulated in the floating gate electrode 5 to the state where charges are extracted, the probability of transition from the state where charges are extracted to the floating gate electrode 5 to the state where charges are accumulated is higher. Overwhelmingly small. That is, the transition probability from the state “1” to the state “0” is almost negligible compared to the transition probability from the state “1” to the state “0”. Furthermore, the probability that each bit stored in the two memory cells M1 and M2 causes data corruption, that is, the probability that both the upper bit and the lower bit of the data string transition from the state “1” to the state “0” also increases. , The probability that either the upper bit or the lower bit transitions from state “1” to state “0” is small enough to be almost ignored. In the first embodiment, E
By utilizing this property peculiar to a nonvolatile semiconductor memory device such as an EPROM, error correction of a read data string is performed.

Specifically, as shown in FIG. 2, the data string "11" at the time of writing is replaced with the data string "01" at the time of reading.
And the probability P1, P2 that the data is garbled into "10",
Probability P3, P that data string "00" at the time of writing is garbled into data string "01" or "10" at the time of reading
4. The probability P5 that the data string "11" at the time of writing is garbled into the data string "00" at the time of reading is extremely small and can be ignored.

Therefore, the read data string is "01".
Or, if "10", this data string has an error. This means that, considering that the information bits (upper bits) and the redundant bits (lower bits) written in one unit (two) of memory cells are the same, “0” or “1” in the data string is considered. "Is an odd number. The correct data string at this time is "11" from the nature of the transition probability.

FIG. 3 shows a reading method including error correction of a data string from an EEPROM utilizing the above-described characteristics.
This will be described with reference to FIG.

First, the bits stored in each memory cell are read out to form a 2-bit data string A (step S1).

Next, "0" in the read data string A
Alternatively, the number C1 of "1" is counted (step S2).

Next, it is determined whether the number C1 counted in step 4S2 is even or odd (step S3).

Next, when it is determined in step S3 that the number C1 is an even number, that is, the data string A is "00".
Alternatively, if the value is "11", there is no error in the data string A, and this data string A is output as it is (step S
4).

On the other hand, when it is determined in step S3 that the number C1 is an odd number, that is, the data string A is "01".
Or, when it is "10", the data string A is corrected to "11" and output (step S5).

As described above, the EEPR of the first embodiment
According to the OM, error correction cannot be performed unless at least two bits or more of redundant data are added to one information bit in the prior art, whereas one bit of redundant data is added to one information bit. Is added, error correction can be performed easily and reliably.

(Second Embodiment) Next, the second embodiment of the present invention
An embodiment will be described. In the second embodiment, an EE which is a nonvolatile semiconductor memory device capable of storing binary (= 1 bit) information in each memory cell
An example will be described in which a PROM is used to write and read a data string (4 bits) in which quaternary (2 bits) information bits are added with quaternary (2 bits) redundant bits for error correction. FIG. 4 is a schematic diagram showing how an error occurs based on the transition probability, and FIG. 5 is a flowchart for performing error correction at the time of reading. In addition,
The schematic configuration of each memory cell of the EEPROM of the second embodiment is the same as that of FIG. 1 of the first embodiment.

In each memory cell, the state where charge is stored in the floating gate electrode 5 is “1”, and the floating gate electrode 5
Is defined as "0". This EEPROM has four values (“0000”, “0”).
101 "," 1010 "," 1111 ") and write 16-value (" 0000 "," 0001 ","
0010 "," 0011 "," 0100 "," 010
1 "," 0110 "," 0111 "," 1000 ","
1001 "," 1010 "," 1011 "," 110 "
0 "," 1101 "," 1110 "," 1111 ").

That is, in the four memory cells M1 to M4 forming one unit, the storage data to be written to one memory cell M1 of the two memory cells M1 and M2 "
0 "and" 1 "are defined as the most significant bits, and the storage data" 0 "and" 1 "to be written into the other memory cell M2 are defined as the next two most significant bits. The quaternary information bits (“00”, “0”) are determined by the most significant bit and the second most significant bit stored in M1 and M2.
1 "," 10 "," 11 ").

Further, the remaining two memory cells M3, M4
Of these, the same bit as the storage data of the memory cell M1 is written into one memory cell M3, the same bit as the storage data of the memory cell M2 is written into the other memory cell M4, and the bit stored in the memory cell M3 is set to 3 The higher order bit (second lower order bit) and the bit stored in the memory cell M3 are defined as the least significant bit. In this case, the same high-order bit and the least-significant bit stored in the two memory cells M3 and M4 form the same redundant bit as the above-mentioned information bit.

The most significant bit to the least significant bit written to the memory cells M1 to M4 are quaternary (“00”).
00 "," 0101 "," 1010 "," 1111 ")
Is formed.

On the other hand, at the time of reading, 16 values ("0000", "0001", "0") are considered in consideration of the case where an error occurs in the bits constituting the data string as described later.
010 "," 0011 "," 0100 "," 010
1 "," 0110 "," 0111 "," 1000 ","
1001 "," 1010 "," 1011 "," 110 "
0 "," 1101 "," 1110 "," 1111 ") can be composed of each bit read from the memory cells M1 to M4. If it is determined that there is an error, it will be described later. And then output.

In the second embodiment, as in the first embodiment, the state "1" in which electric charges are extracted from the state "1" in which electric charges are stored in the floating gate electrode 5 of each memory cell is "0". The probability of transition from the state “0” in which charges are extracted to the floating gate electrode 5 to the state “1” in which charges are accumulated is significantly smaller than the probability of transition to “1”.
Probability that each of the bits stored in the two memory cells in the four memory cells M1 to M4 causes data corruption, that is, two or more bits in the data string transition from state “1” to state “0”. Utilizing that the probability is also small,
Error correction of the read data string is performed.

FIG. 4 shows a specific error correction method. Here, the data sequence "1111" at the time of writing is replaced with the data sequence "0111", "1011", "110" at the time of reading.
Probability P11, P1 of garbled data at 1 "," 1110 "
2, P13, P14, the data string at the time of writing "
The probabilities P15 and P16 of "1111" being garbled into "0101" or "1010" are extremely small and can be ignored.

Similarly, the data string "010" at the time of writing
In the case of “1”, the data string “000” can be read at the time of reading if the probability of data conversion from “0” to “1” is ignored.
Probability P17, P1 that data is garbled to "1" or "0100"
Only eight need be considered.

The data string "1010" at the time of writing
In the case of, if the probability of garbled data from “0” to “1” is ignored, the data string “0010” at the time of reading is obtained.
And only the probabilities P19 and P20 of garbled data to "1000" need to be considered.

Also, the data string "0000" at the time of writing
In this case, if the probability that data is garbled from “0” to “1” is ignored, there is no error and “000” is obtained at the time of reading.
0 "can be considered.

Therefore, the read data string is "011".
1 ”,“ 1011 ”, or“ 1101 ”
This data string will have an error. This means
Considering that the information bits (upper two bits) written to the memory cells M1 and M2 and the redundant bits (lower two bits) written to the memory cells M3 and M4 are the same, " This is equivalent to three 1 ". At this time, the correct data string is "1111" from the nature of the transition probability.

Similarly, the read data string is "000".
If the data string is one of 1 "and" 0100 ", there is an error in this data string, and the correct data string at this time is" 0101 "from the nature of the transition probability. And the read data string is “001”.
If it is either "0" or "1000", this data string has an error, and the correct data string at this time is "1010" from the nature of the transition probability.

From this, if the number of "1" in the data string is one, the data string has an error. In order to determine whether the correct data string is “0101” or “1010”, the position of “1” in the data string is searched from the LSB.
The data string may be corrected to “1010” or “0101” if it is an odd number position.

FIG. 5 shows a method of reading data from an EEPROM using the above-mentioned characteristics, including error correction of a data string.
This will be described with reference to FIG.

First, each bit stored in each of the memory cells M1 to M4 is read, and a 4-bit data string B is read.
(Step S11).

Next, "1" in the read data string B
Is counted (step S12).

Next, it is determined whether the number C2 counted in step S12 is even or odd (step S13).

Next, when it is determined in step S13 that the number C2 is an even number, that is, when the data string B is "00"
If it is 00 "," 0101 "," 1010 ", or" 1111 ", there is no error in the data string B, so this data string A is output as it is (step S14).

On the other hand, when it is determined in step S13 that the number C2 is an odd number, the number C2 is one or three.
One of the numbers is determined (step S15).

Next, when it is determined in step S15 that the number C2 is three, that is, the data string B is "01".
11 "," 1011, "," 1101 "," 111
If it is "0,", the data string B is corrected to "1111" and output (step S16).

On the other hand, if it is determined in step S15 that the number C2 is one, the position C3 of "1" in the data string B is searched (step S17).

Next, it is determined whether the position C3 searched in step S17 is an even position or an odd position counting from the least significant bit (step S18).

Next, in step S18, when it is determined that the position C3 is an even position, that is, when the data string B is "
If it is "0010" or "1000," the data string B is corrected to "1010" and output (step S1).
9).

On the other hand, if it is determined in step S18 that the position C3 is an odd position, that is, if the data string B is "
If it is "0001" or "0100,", the data string B is corrected to "0101" and output (step S2).
0).

As described above, the EEPR of the second embodiment
According to OM, error correction cannot be performed unless at least 3 bits or more of redundant data are added to 2 bits of information bits, whereas 2 bits of redundant data are added to 2 bits of information bits. Is added, error correction can be performed easily and reliably.

In the second embodiment, the data string is created by adding the same two redundant bits as the information bits to the two information bits, but the information bits are replaced with the two information bits. 2 with bit position reversed
A data string may be created by adding redundant bits, and writing and reading may be performed. in this case,
In reading from the EEPROM including error correction of the data string, the order of step S19 and step S20 is switched.

The program code itself for operating various devices so as to realize the functions of the writing method and the reading method described with reference to FIGS. 3 and 5 in the first and second embodiments. Means for supplying the program code to a computer, for example, a storage medium storing the program code belong to the scope of the present invention. As a storage medium for storing such a program code, for example, a floppy disk, hard disk, optical disk, magneto-optical disk, CD-ROM,
A magnetic tape, a nonvolatile memory card, a ROM, or the like can be used.

When the computer executes the supplied program code, not only the functions of the first and second embodiments are realized, but also the OS (operating system) in which the program code runs on the computer. Also, the present invention includes such a program code in a case where the functions of the first and second embodiments are realized in cooperation with other application software or the like.

Further, after the supplied program code is stored in the memory provided in the function expansion board of the computer or the function expansion unit connected to the computer, the function expansion board or the function expansion unit is specified based on the instruction of the program code. The present invention also includes a system in which a CPU or the like provided in the system performs part or all of the actual processing, and the processing realizes the functions of the first and second embodiments.

[0075]

According to the present invention, redundant bits added to information bits can be made extremely short, and error correction can be performed efficiently and accurately. Specifically, by adding the same error-correcting redundant bits as the information bits to the information bits, error correction can be performed easily and reliably.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view illustrating a main configuration of one memory cell included in an EEPROM according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram showing a state in which an error occurs based on a transition probability in the first embodiment of the present invention.

FIG. 3 is a flowchart for performing error correction at the time of reading in the first embodiment of the present invention.

FIG. 4 is a schematic diagram showing a state in which an error occurs based on a transition probability in a second embodiment of the present invention.

FIG. 5 is a flowchart for performing error correction at the time of reading in the second embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon semiconductor substrate 2 Element formation area 3 Source 4 Drain 5 Floating gate electrode 6 Control gate electrode 7 Tunnel oxide film 8 Dielectric film

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/788 29/792

Claims (16)

[Claims] A charge storage layer and a gate electrode, wherein a predetermined voltage is applied to the gate electrode to store or extract a charge in the charge storage layer to write an information bit; In a semiconductor memory device having a plurality of semiconductor memories for reading out the information bits by judging a charge accumulation state, a data string in which the same redundant bits as the information bits are added to the information bits, Each bit forming a column is written and read corresponding to each of the semiconductor memories. When reading the data sequence, a state where charges are extracted from a state where charges are stored in the charge storage layer. The second transition that changes from the state in which the charge is extracted to the state in which the charge is stored is smaller than the probability that the first transition that changes to Utilizing that the probability of generation is negligibly small, and it is determined that the number of bits corresponding to the state where charges are stored in the charge storage layer or the state where charges are extracted in the data string is an odd number A semiconductor memory device that performs error correction on the assumption that an error has occurred in response to the first transition. 2. The probability that a third transition, in which at least two bits of the data sequence change from a state in which charges are stored in the charge storage layer to a state in which the charges are drawn out, is also generated in the second sequence, Utilizing the fact that it is negligibly small compared to the probability of occurrence of the first transition as in the case of the transition, it corresponds to the state where charges are stored in the charge storage layer or the state where charges are extracted in the data sequence. When it is determined that the number of bits to be changed is an odd number, one bit corresponds to the first transition.
2. The semiconductor memory device according to claim 1, wherein error correction is performed on the assumption that an error has occurred only in the bit. 3. The semiconductor memory device according to claim 1, wherein said semiconductor memory is provided with a floating gate as said charge storage layer and a control gate as said gate electrode. 4. A plurality of memory cells each having a charge storage layer and a gate electrode are arranged in rows and columns, each of which forms a data string to which an information bit having a predetermined value and the same redundant bit as the information bit are added. A storage unit in which bits are respectively stored in the respective memory cells, a predetermined memory cell is selected from the storage units, the bit stored in the respective memory cells is detected, and the data is detected. A row is formed, and the state is changed from the state where the charges are extracted to the state where the charges are stored compared to the probability that the first transition that changes from the state where the charges are stored in the charge storage layer to the extracted state occurs. Utilizing the fact that the probability that the second transition will occur is negligibly small, the state where charges are stored in the charge storage layer of each memory cell or the charges are extracted in the data string Reading means for performing error correction and outputting when it is determined that an error has occurred in response to the first transition when it is determined that the number of bits corresponding to the state is an odd number A semiconductor memory device characterized by the above-mentioned. 5. The reading means according to claim 3, wherein at least two bits of the data string change from a state where charges are stored in the charge storage layer to a state where the charges are extracted.
The probability of occurrence of the transition is also negligibly small compared to the probability of occurrence of the first transition as in the case of the second transition, and charges are stored in the charge storage layer in the data string. If it is determined that the number of bits corresponding to the extracted state or the state from which the charge has been extracted is an odd number, it is considered that an error has occurred in only one bit in response to the first transition, and the error is determined. 5. The semiconductor memory device according to claim 4, wherein correction is performed. 6. The semiconductor memory device according to claim 4, wherein said memory cell has a semiconductor element provided with a floating gate as said charge storage layer and a control gate as said gate electrode. . 7. A charge storage layer and a gate electrode, wherein a predetermined voltage is applied to the gate electrode to store or extract a charge in the charge storage layer to write an information bit, and to write information bits in the charge storage layer. In a reading method of a semiconductor memory device including a plurality of semiconductor memories for reading out the information bits by judging a charge accumulation state, each semiconductor memory has the same redundant bits as the information bits added to the information bits A predetermined one bit of each bit constituting the data string is stored in the data string thus formed. When the stored data string is read, charges are accumulated in the charge storage layer. The probability that the first transition that changes from the state to the extracted state occurs to the second transition that changes from the state in which the charge is extracted to the state in which the charge is stored. Utilizing that the probability of occurrence of the transition is negligibly small, the number of bits corresponding to the state in which the charge is stored in the charge storage layer or the state in which the charge is extracted in the data string is an odd number. A method for reading a semiconductor memory device, comprising determining that an error has occurred in response to the first transition and performing error correction when the determination is made. 8. The probability that, for two or more bits of the data sequence, a third transition that changes from a state in which charges are stored in the charge storage layer to a state in which charges are extracted is also generated by the second transition. Utilizing the fact that it is negligibly small compared to the probability of occurrence of the first transition as in the case of the transition, it corresponds to the state where charges are stored in the charge storage layer or the state where charges are extracted in the data sequence. When it is determined that the number of bits to be changed is an odd number, one bit corresponds to the first transition.
8. The method according to claim 7, wherein the error correction is performed assuming that an error has occurred only in the bit. 9. The semiconductor memory device according to claim 7, wherein said semiconductor memory is provided with a floating gate as said charge storage layer and a control gate as said gate electrode. Read method. 10. A charge storage layer and a gate electrode, wherein a predetermined voltage is applied to the gate electrode to store or extract a charge in the charge storage layer to write an information bit. In a reading method of a semiconductor memory device including a plurality of semiconductor memories, each of which determines a charge storage state and reads the information bits, a state in which charges are stored in the charge storage layer of the semiconductor memory is “1”. The state in which the charge is extracted is set to “0”, and the semiconductor memory stores a predetermined one bit of each bit constituting a data string in which the same redundant bits as the information bits are added to the information bits. A first step of reading each of the bits from each of the semiconductor memories to form the data string; and A second step of counting the number of “0” or “1”, a third step of determining the evenness of the counted number, and a case where the third step determines that the number is even. A fourth step of outputting the data string without correction, and a step of judging a different bit between the information bit and the redundant bit in the data string when it is determined that the data string is odd. A semiconductor memory comprising: a fifth step; and, among the bits determined in the fifth step, a bit that is “0” is corrected to “1” and output. How to read the device. 11. A charge storage layer and a gate electrode, wherein a predetermined voltage is applied to the gate electrode to store or extract a charge in the charge storage layer to write an information bit. In a reading method of a semiconductor memory device having a plurality of semiconductor memories for reading the information bits by judging a charge accumulation state, a state in which charges are accumulated in the charge accumulation layer is set to “1”, and the charges are subtracted. The extracted state is set to “0”, and the semiconductor memory stores one predetermined bit among the bits forming a data string in which the same redundant bits as the information bits are added to the information bits. A first step of reading each of the bits from each of the semiconductor memories to form the data string; and “0” or “1” in the data string. A second step of counting the number of, and a third step of determining parity of counted the number, if it is determined that the even in the third step,
A fourth step of outputting the data string without correction, and when the third step is determined to be odd,
A fifth step of correcting the data string to "11" and outputting the corrected data string. 12. A charge storage layer and a gate electrode, wherein a predetermined voltage is applied to the gate electrode to store or extract a charge in the charge storage layer to write an information bit. In a reading method for a semiconductor memory device including a plurality of semiconductor memories for reading out the information bits by judging a charge accumulation state, a state in which charges are accumulated in the charge accumulation layer is set to “1”, and the charges are extracted. The state of the semiconductor memory is set to “0”, and the semiconductor memory includes a predetermined number of bits constituting a 4-bit data string in which the same two information bits are added to the two information bits. A first step of reading out the data string, and a second step of counting the number of “1” in the data string. A third step of determining parity of counted the number, if it is determined that the even in the third step,
A fourth step of outputting the data string without correction, and when the third step is determined to be odd,
A fifth step of determining whether the number is one or three, and a sixth step of correcting and outputting the data string to "1111" when it is determined that the number is three in the fifth step. A step for determining whether the position is an even position or an odd position when viewed from the most significant bit in the data string, when it is determined that the number is one in the fifth step; An eighth step of correcting the data string to "1010" when it is determined in the seventh step to be an even position and outputting the data string in an odd position in the seventh step; A ninth step of correcting the data string to “0101” and outputting the corrected data string. 13. The semiconductor memory according to claim 10, wherein a floating gate is provided as the charge storage layer, and a control gate is provided as the gate electrode. Reading method of the semiconductor memory device of the above. 14. A recording medium, wherein the first to sixth steps constituting the method for reading a semiconductor memory device according to claim 10 are stored so as to be readable by a computer. 15. A recording medium, wherein the first to fifth steps constituting the method of reading a semiconductor memory device according to claim 11 are stored so as to be readable by a computer. 16. A recording medium wherein the first to ninth steps constituting the method for reading a semiconductor memory device according to claim 12 are stored so as to be readable by a computer.