JPH1165923A - Arithmetic processing unit and memory access method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a processing capability by comparing a leading address with an address from a data pointer(DP) register, discriminating a page to be accessed from plural banks, and transferring data to a data register. SOLUTION: Banks 45 and 46 of an inside memory 47 store pages with prescribed data amounts stored in continuous addresses on a memory address space, and DP registers 30 and 31 store addresses on the memory address space. Data registers r0 and r1 transfer data between the inside memory 47 and an ALU 13 for operating an arithmetic processing. The leading addresses of the pages stored in the banks 45 and 46 are compared with addresses stored in DP registers 30 and 31, and whether or not pages to be accesses are present in the banks 45 and 46 is discriminated. When the pages to be accesses are present, the pages to be accessed are data-transferred from the banks 45 and 46 to the data register by using the addresses stored in the DP registers 30 and 31.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an arithmetic processing unit and a memory access method.

[0002]

2. Description of the Related Art Microprocessors can be classified according to a general design concept, for example, RISC (Reduced Insulated).
truction Set Computer) and CISC (Complex Instr
uctionSet Computer) type. By the way, the program execution time which determines the performance of the microprocessor alone is expressed by the following equation (1).

[0003]

## EQU1 ## Program execution time = number of executed instructions (IC) × average number of required clock cycles per instruction (CPI) × clock cycle time (CCT) (1)

The design concept of the RISC microprocessor is to make the CPI of the above equation (1) as close to 1 as possible by making full use of instruction pipeline processing. Therefore, in the RISC type microprocessor, from the viewpoint of simplifying the function of the instruction so as to be suitable for the instruction pipeline processing, the instruction has a fixed single length, and the instruction format is a register-register format (load / store architecture: The source operand of the operation instruction is a register operand only). In a RISC microprocessor, static code scheduling is performed by a compiler so that instruction pipeline processing is not delayed.

On the other hand, in the CISC type microprocessor, the function level of the instruction is increased to increase the I level of the above equation (1).
The design philosophy is to reduce C. Therefore, C
In an ISC-type microprocessor, instructions are of fixed length or variable length, and instruction formats include a register-memory format and a memory-memory format (a memory operand can be used as a source operand of an operation instruction). . That is, direct operation between the register and the memory is enabled.

By the way, the data on the memory is transferred to ALU (Ari
thmetic Logic Unit)
In a microprocessor of the type, at least two of a load instruction and a store instruction are required to perform a memory access. On the other hand, in a CISC type microprocessor, an instruction only for memory access is not required.
In a CISC type microprocessor, many bit fields are required in an instruction for specifying a memory address, and a variable length instruction is often employed as described above. However, when a variable length instruction is used, the decoding circuit tends to be complicated and large. Therefore, CI
At present, in the SC type microprocessor, in order to reduce the program execution time, the operation on the data on the memory is accelerated using a superscaler technique or an out-of-order technique.

A memory access method in a conventional RISC type and CISC type microprocessor will be described below. FIG. 26 shows a conventional RISC type and CI
FIG. 2 is a diagram for explaining general-purpose registers of an SC type microprocessor. As shown in FIG. 26, it is assumed that the conventional microprocessor is provided with, for example, 16 general-purpose register sets, and the 16 general-purpose registers are given names r0 to r15. When these registers are implemented in a processor architecture of a three-operand operation instruction set, a total of three ports of two read ports and one write port are required.

In the three-operand operation instruction, as shown in FIG. 27, three register specifiers of the ALU operation instruction can be specified. In FIG. 27, on the right side of “;”, a comment sentence for the instruction described on the left side of “;” is described. The instruction shown in FIG. 27 is “r2 ← r
3 + r4 ”. The registers r0 to r15 are used for general purpose and for temporarily holding the values. In a processor employing a load / store type architecture, a memory load / store
Load / load to general purpose registers to implement store
Execute the store instruction. There is no instruction to directly substitute the ALU. This type is often found in RISC type processors. As shown in FIG. 28, when processing the data on the memory, the load instruction “lwr
3,0 (r10) ". On the other hand, the CISC type processor stores the data on the memory as A
Some can be specified as an operand of an LU operation instruction. However, in that case, the memory buffer is directly used without using the general-purpose register.

Hereinafter, the pipeline processing of the conventional RISC type processor will be described. Many RISC processors have a five-stage or eight-stage pipeline structure. For example, as shown in FIG. 29, R3000 (trade name) of MIPS Co., Ltd.
h) Stage, DEC (Instruction Decode) stage,
ALU stage, MEM (Memory) stage and WB (W
rite Back) A five-stage pipeline is used. In this processor, an instruction is fetched (read) in the first IF stage and decoded in the second DEC stage. If the instruction specifies a general-purpose register as a source register, the instruction is decoded in the DEC stage, and then data is read from the general-purpose register. Next, an ALU operation instruction is executed in the third ALU stage. If the fetched instruction is not an ALU instruction, nothing is performed in the ALU stage, so that the data is output to the output port of the ALU as it is.

Next, in the fourth MEM stage, when the fetched instruction is a memory access instruction, a memory address for memory access is output to the memory unit to execute the memory access. Next, at the fifth stage,
For an instruction that designates a general-purpose register as a destination register, the operation result of the ALU is written back to the general-purpose register. If it is a memory read instruction (load instruction), it receives a value from the memory unit and writes it to a general-purpose register. As shown in FIG. 29, the processor employing the 5-stage pipeline, for example, in a clock cycle X, and WB stages of the code C _1, code C ₂ ME
And M stage, and ALU stage code C _3, and DEC stage code C _4, and the IF stage of the code C ₅ performed by multiplexing.

Since the load / store type instruction set architecture is adopted in the RISC processor as described above, the ALU operation instruction and the load / store instruction are separated and exist independently of each other. .
Therefore, in order to multiplex arbitrary instructions including these instructions, for example, it is convenient to adopt a five-stage pipeline structure shown in FIG. That is, the memory access instruction and other instructions can be executed simultaneously.
Since it is assumed that there is only one system (one set) of memory access paths, a memory read and a memory write are not executed simultaneously in the same MEM stage. In addition, if a memory access instruction and other instructions are handled independently, an unused pipeline stage occurs. For example, in a transfer instruction between registers, MEM
Stage functionality is not used. In the memory access instruction, the function of the ALU stage is not used. In addition,
The address generation operation for memory access is performed in another unit other than the ALU.

In the five-stage pipeline processing shown in FIG.
When the data on the memory is subjected to the ALU operation, a program is described, for example, as shown in FIG. FIG.
In the program shown in FIG. 1, first, the instruction “lw r2, 0
(R10) "loads the data on the memory address indicated by the register r10 into the register r2. next,
The instruction “addu r3, r2, r9” adds the values of the register r2 and the register r9, and assigns the result to the register r3. Next, the instruction “sw r3,0 (r1
1), the value of the register r3 is stored (rewritten) at the memory address indicated by the register r11. These operations are described by three instructions. Each instruction requires at least one clock cycle to execute, so executing three instructions requires three clock cycles. Actually, the memory read (loaded) data cannot be referred to by the instruction immediately after that, so another clock cycle is required.

[0013]

However, in media processing such as image processing and audio processing, it is necessary to repeatedly perform a predetermined ALU operation on data in a continuous memory address space. In this case, as shown in FIG. 31, it is necessary to further add an instruction “addi r10, 4” and an instruction “addi r11, 4” for updating the memory address to the program shown in FIG. As a result, at least five clock cycles are required to execute the program shown in FIG. 31, and there is a problem that the processing time becomes longer. In FIG. 31, the start address of the source data of the addition operation on the memory is set using the register r10, and the start address of the destination data is set using the register r11.

In the above-described five-stage pipeline processing in the conventional microprocessor, memory access is executed in the MEM stage, and the memory access path is one.
Since only the system is provided, memory read and memory write cannot be executed simultaneously. Therefore, it is necessary to create a program in which a memory read instruction and a memory write instruction are described independently, which has been a bottleneck when shortening the processing time. It is very important for a microprocessor to efficiently use limited register resources in system design.

The present invention has been made in view of the above-mentioned problems of the prior art, and provides an arithmetic processing device and a memory access method capable of improving processing performance. In addition, the present invention provides an arithmetic processing device and a memory access method that can efficiently use register resources and, in particular, can appropriately exhibit the functions of general-purpose registers.

[0016]

In order to achieve the above-mentioned object, an arithmetic processing unit according to the present invention comprises a plurality of pages each storing a predetermined amount of data stored at consecutive addresses in a memory address space. An internal memory having a bank, a data pointer register for storing an address in the memory address space, an arithmetic unit for performing arithmetic processing, and a data register for transferring data between the internal memory and the arithmetic unit. Storing a start address in the memory address space of the page stored in the plurality of banks, comparing the stored start address with an address stored in the data pointer register, and comparing the result of the comparison with the address stored in the data pointer register. Page presence / absence determination for determining whether there is a page to be accessed in any of the plurality of banks based on the plurality of banks And when the page to be accessed is present in any of the plurality of banks as a result of the determination, the data pointer register is provided between the bank in which the page to be accessed is stored and the data register. And control means for performing control to transfer data using the address stored in the memory.

In the arithmetic processing device according to the present invention, the page presence / absence determining means determines which of the plurality of banks of the internal memory contains a page to be accessed by the arithmetic means, and the determination is made. Based on the result, a single data register is selected and connected to a bank that stores a page to be accessed from a plurality of banks.

Further, the memory access method of the present invention includes a plurality of banks for respectively storing pages of a predetermined data amount stored at consecutive addresses in the memory address space from the arithmetic means via the data register. A memory access method for accessing an internal memory, wherein an address in the memory address space is stored in a data pointer register, and a head address in the memory address space of a page stored in the plurality of banks is stored. The stored head address is compared with the address stored in the data pointer register, and based on a result of the comparison, it is determined whether a page to be accessed exists in any of the plurality of banks. As a result of the determination, the page to be accessed exists in any of the plurality of banks. Case, between the bank and the data register page to be accessed is stored, and transfers data using the address stored in the data pointer register.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a microprocessor according to an embodiment of the present invention will be described. First Embodiment FIG. 1 is a configuration diagram of a microprocessor 1 of the present embodiment. The microprocessor 1 includes a general-purpose register module 11, a multiplexer (MUX) 12, 1 shown in FIG.
6, an ALU (Arithmetic Logic Unit) 13, an instruction page memory 35, a decoder 36, the DP registers 30 and 31 and the internal memory 47 shown in FIG. 2, and these are incorporated in one chip.
In the microprocessor 1, the following processing is performed based on the control signal S36 according to the decoding result of the decoder 36.

The general-purpose register module 11 has, for example, 16 32-bit registers r ₀ to r ₀ used for general purposes.
It is composed of a register set in r _15. The number of registers constituting the general-purpose register module 11 largely depends on the instruction set or the chip architecture, and is generally set in the range of 8 to 32. As shown in FIG. 1, the general-purpose register module 11 has seven ports W, RA, RB, MA, MB, DA, and DB. Here, port W is a write port and ALU
The data output from port AOUT of bus 13 is
3 and the general-purpose register module 1 via the port W
Written to 1. The ports MA and MB are connected to the memory banks 4 of the internal memory 47, respectively, as shown in FIG.
Ports between the buses 26 and 2 respectively.
7, data is transferred to and from the ports of the memory banks 45 and 46. It should be noted that the port R is provided outside the general-purpose register module 11 without providing the ports MA and MB.
A, RB, W may be switched to realize a connection with the memory banks 45, 46.

The ports RA and RB are read ports. Data read from the general-purpose register module 11 is output to the multiplexer 12 via the ports RA and RB and the buses 17 and 18. Further, the ports DA and DB are ports for performing bidirectional communication between the multiplexer 16 and the data registers r ₀ and r ₁ , respectively.

In the general-purpose register module 11, the ports W, RA, RB, MA, MB, DA, and DB can be used simultaneously. That is, general-purpose register module 1
1 can be executed independently of the read operation and the write operation.

In the microprocessor 1, the data registers r ₀ and r ₁ are used as buffers serving as interfaces for communicating with the memories via the buses 26 and 27, respectively. The register r ₂ ~r ₁₅ is used as a general-purpose register. In the microprocessor 1, for example, the internal memory 4 in the ALU 13
In the case of using the data stored in 7, the data is read out to the data register r ₀ via the bus 26, and then the data register r ₀ is accessed. At this time,
From the internal memory 47 via the bus 27, after reading the data into the data register r _1, may access the data register r _1. Further, the microprocessor 1, when writing data in the internal memory 47, after writing data to the data register r ₀ or r _1,
The written data is transferred to the internal memory 47 via the bus 26 or 27.

[0024] The data register r _0, r ₁ is the substantially the same topology and other registers r ₂ ~r _15, can also be used as well as general-purpose registers and register r ₂ ~r _15. Specifically, for example, the multiplexer 16
Selects the connection between the buses 21 and 22 and the ports DA and DB, the ports DA and DB
Performs the same function as RB, and buses 21 and 22
It performs the same function as 7 and 18. When the multiplexer 16 selects the connection between the bus 23 and the port DA or DB, the port DA or DB performs the same function as the port W. Therefore, the data registers r ₀ and r ₁ are uniformly described as a part of a general-purpose register group including the registers r _{2 to} r ₁₅ in the program, and are similarly recognized by the decoder 36.

DP (Data Pointer) registers 30, 31
Are the memory banks 45 and 46 of the internal memory 47, respectively.
The address in the memory address space is stored. In addition,
The DP registers 30 and 31 correspond to the general-purpose register module 1
Unlike one register r _{0 to} r ₁₅ , a part of a plurality of control registers is assigned. Therefore, DP register 3
0 and 31 cannot be directly specified using the register specifier of the ALU operation instruction, but are specified by a data transfer instruction. Writing an address on the internal memory 47 to the DP registers 30 and 31 requires one instruction step. However, an access operation to the internal memory 47 via the data registers r ₀ and r ₁ is required. Is not described in the program, and is performed in the background separately from the process directly specified in the program. That is, the access operation to the internal memory 47 is performed in parallel with the pipeline processing.

In the microprocessor 1, for example, FIG.
When the data stored in the memory bank 45 of the internal memory 47 is read, the address of the read data in the memory bank 45 is written to the DP register 30. As a result, the data stored in the address in the memory bank 45 written in the DP register 30 becomes
The data is automatically read from the memory bank 45 to the data register r ₀ via the bus 26 by hardware.
Thereafter, the multiplexer 16 is read from the data register r _0.
Is transferred to the port AIN or BIN of the ALU 13 via the.

Similarly, in the microprocessor 1, for example, when reading data stored in the memory bank 46 of the internal memory 47 shown in FIG. Write to 31. As a result, the data stored in the address in the memory bank 46 written in the DP register 31 is automatically read out from the memory bank 46 to the data register r ₁ via the bus 26 by hardware. Thereafter, data is transferred from the data register r ₁ to the port AIN or BIN of the ALU 13 via the multiplexer 16.

As described above, in the microprocessor 1,
By writing the addresses in the memory banks 45 and 46 to the DP registers 30 and 31, the data stored at the addresses are automatically read out to the data registers r ₀ and r ₁ respectively.

On the other hand, the memory bank 45 of the internal memory 47
When data is written to a predetermined address in data registers 46 and 46, after writing the address to DP registers 30 and 31, respectively, data registers r ₀ and r
Write the relevant data to ₁ . Thereafter, the data stored in the data registers r ₀ and r ₁ are automatically written by hardware into the addresses in the memory banks 45 and 46 stored in the DP registers 30 and 31. In addition,
Data transfer between the data register r ₀ and the memory bank 45 and data transfer between the data register r ₁ and the memory bank 46 can be performed in the same pipeline cycle in the microprocessor 1.

When one of the data registers r _{0 and} r ₁ is used in a memory write operation to the internal memory 47, a slight cycle may be lost.
This is because the operation of automatically reading data from the data register r ₀ or r ₁ is unnecessary. To prevent this, if at least one of the data registers r ₀ and r ₁ is set to the write operation only mode in accordance with the purpose of use, useless memory read (load) operation can be avoided. As a characteristic of memory read or memory write, in fields such as image processing,
It is highly likely that consecutive memory addresses will be referenced. That is, the memory read instruction is often executed again after the memory read instruction. Moreover, at this time, there is a high possibility that consecutive memory addresses are accessed. for that reason,
The DP registers 30 and 31 have, for example, an internal memory 47.
Each time the stored data is accessed, the stored address is changed to, for example, +1, -1, +4, -4, +8
Alternatively, a function of automatically incrementing by -8 is provided to improve processing efficiency when performing image processing.

The memory banks 45 and 46 of the internal memory 47 shown in FIG. 2 store copies of data in the memory address space of the external main memory 50 whose addresses are continuous. The addresses in the memory address space of the external main memory 50 do not need to be continuous between the memory banks 45 and 46.

The ALU 13 has input ports AIN, BIN
And an arithmetic operation or a logical operation on data input from the input ports AIN and BIN based on a control signal S36 from the decoder 36, and transfers the operation result data from the port AOUT to the bus 2
Output to 3. The ALU 13 executes an operation in one clock cycle. Here, depending on the type of the operation instruction, the ALU 13 transmits the ALU1 from the input port AIN or BIN based on the control signal S36 from the decoder 36.
In some cases, the data input to 3 is output from the output port AOUT as it is without performing the operation.

Hereinafter, the pipeline processing operation in the microprocessor 1 will be described. In the microprocessor 1, with the configuration shown in FIG. 1, the data path at the time of instruction execution has a four-stage pipeline structure as shown below. FIG. 4 is a diagram for explaining the pipeline processing of the microprocessor 1. As shown in FIG. 4, the microprocessor 1 includes an IF stage, a DEC stage,
A 4-stage pipeline of an ALU stage and a WB (Write Back) stage is adopted. That is, 4 shown in FIG.
The stage pipeline does not have the MEM stage of the five-stage pipeline shown in FIG.

In the four-stage pipeline shown in FIG.
The processing in the F stage, DEC stage, and ALU stage is the same as in the case of the five-stage pipeline shown in FIG. 29 described above. In the four-stage pipeline shown in FIG.
The IF stage, the DEC stage, the ALU stage and the WB stage are multiplexed and performed. Specifically, in the microprocessor 1, the first IF stage
The instruction to be executed next is fetched (read) from the address on the instruction memory 35 indicated by the program counter 34 shown in FIG. Next, in the second DEC stage, the instruction fetched in the IF stage is decoded by the decoder 36 shown in FIG. The multiplexers 12, 16 and the ALU 13 are controlled based on the control signal S36 according to the decoding result.

If the instruction specifies the registers r _{0 to} r ₁₅ of the general-purpose register module 11 as a source register, the instruction is decoded in the DEC stage, and then the data from the data registers r _{0 to} r _{15 is} transmitted to the multiplexer 12. The data is read out to the ports AIN and BIN of the ALU 13 via the CPU. That is, in the microprocessor 1, in accordance with the program, can access data registers r _0, r ₁ as well as other general purpose register r ₂ ~r _15. At this time,
When a memory access to the internal memory 47 is necessary, a predetermined address on the internal memory 47 is stored in the DP registers 30 and 31 shown in FIG. 2, and then the data registers r ₀ and r ₁ are accessed. , The access to the internal memory 47 is realized. That is, the microprocessor 1 implements memory access to the internal memory 47 via the data registers r ₀ and r ₁ .

Next, in the third ALU stage, the ALU
Execute the operation instruction. The fetched instruction is ALU
If it is not an operation instruction, nothing is performed in the ALU stage, and data input from ports AIN and BIN are
The signal is directly output from the port AOUT 13. Next, 4
In the second WB stage, the ALU 13 for an instruction in which _one of the data registers r ₀ and r ₁ and the registers r _{2 to} r ₁₅ is designated as a destination register
Is written back to the specified register. At this time, by writing data to the data registers r ₀ and r ₁ , the internal memory 4 is indirectly connected via the buses 26 and 27.
Write the data back to 7.

[0037] In four-stage pipeline processing shown in FIG. 4, the code C ₁ is an instruction involving memory write operation to the internal memory 47 shown in FIG. 2, the memory code C ₃ is to the internal memory 47 In the case of an instruction accompanied by a read operation, in the clock cycle Y shown in FIG.
₁ of WB stage 41, in the DEC stage 42 of the code C _3, will perform a memory access at the same time. In this case, in the microprocessor 1, the internal memory 47
Data register r serving as a buffer for access to
₀ and r ₁ and two access paths to the internal memory 47 are provided, so that the code C ₁ and the code C ₃
If the bank of the internal memory 47 to be accessed is different between the WB stage 41 and the code C ₁ , as shown in FIG.
And it can be multiplexed and DEC stage 42 of the code C _3, pipeline processing is not disturbed (not stall).

Hereinafter, an example of an access operation to the internal memory 47 according to the description of the program in the microprocessor 1 will be described. When a two-operand operation instruction is used, a two-operand operation instruction having an operation code (OP) and two operands specifying a [source register] and a [destination register] is used as shown in FIG. Next, an access operation to the internal memory 47 when a program is described will be described.

For example, as shown in FIG. 7, when the data register r ₀ is designated as the source register in the two-operand operation instruction, the data is stored in the data register from the address stored in the DP register 30 on the internal memory 47. After reading to r ₀ , the data stored in the data register r ₀ and the data stored in the register r ₄ are added, and the resulting data is written to the register r ₄ .

For example, as shown in FIG. 8, when the data register r ₁ is specified as a destination register in a two-operand operation instruction, the data stored in the DP register 31 on the internal memory 47 is read from the address. the after reading the data register r _1, and data stored in the data register r _1, register r ₅
By adding the data stored in the write data of the addition result in the register r _1. Then, the internal memory 47
The DP register 31 to the address stored in the above, and writes the data stored in the data register r _1.

For example, as shown in FIG. 9, when the data register r ₀ is specified as the source address and the data register r ₁ is specified as the destination register in the two-operand operation instruction, After reading the data from the addresses stored in the DP registers 30 and 31 into the data registers r ₀ and r ₁ respectively, the data stored in the data register r ₀ and the data stored in the data register r ₁ are added. to write the data of the addition result in the register r _1. Then, the address stored in the DP register 31 in the internal memory 47, and writes the data stored in the data register r _1.

By the way, when the operation instructions shown in FIG. 8 are successively executed, in the pipeline processing of the microprocessor 1 shown in FIG. 4, as shown in FIG. 10, a pipeline hazard (stall) of two clock cycles is generated. ) Occurs. This corresponds to clock cycle T + shown in FIG.
In _No. 3, the write operation and the read operation on the data register r1 conflict with each other. That is, the code C ₁ is an operation command shown in FIG. 8, a clock cycle T + 1
When proceeding to DEC stage in the decoder 36 shown in FIG. 1, the locking internally registers r ₁ recognizes that the code C ₁ is a load / store instruction. The code C ₁ is in when it proceeds to the WB stage in clock cycle T + 3, the lock is released. That is, the read-modify-write to the internal memory 47 is locked until it is written back. When an instruction accesses the locked register, the access waits until the lock is released. Then, at clock cycle T + 3 writes the output of the ALU13 in the data register r _1, to determine the release of the lock, and updates the DP register 31. Then, at clock cycle T + 4, the data register r _{1 is} read from the internal memory 47 according to the code C _2.
Reads data, then repeats the same processing as the processing of the code C _1.

When a three-operand operation instruction is used , as shown in FIG.
An access operation to the internal memory 47 when a program is described using a three-operand operation instruction including three operands specifying [source registers] and [destination registers] will be described. In the microprocessor 1, for example, when the program shown in FIG. 30 in a conventional microprocessor is executed, the program can be described as shown in FIG. In FIG. 12, the instruction “mov r ₀ ,
“r ₂ ” is the internal memory 4 stored in the data register r _0.
Data on 7 indicates that transferred to the register r _2. At this time, prior to execution of the instruction “mov r ₀ , r ₂ ”, the memory bank 4 is stored in the DP register 30 shown in FIG.
Read address of the data of interest within 5 are stored by the hardware, the data stored in the address have been transferred to the data register r ₀ through the bus 26. The data on the internal memory 47 stored in the data register r ₀ is transferred to the bus 24 and the multiplexer 1.
The data is transferred to the register r ₂ via the buses 6 and 12 and the bus 23.

“Add r ₂ , r ₉ , r ₃ ” indicates that the data stored in the register r ₂ and the data stored in the register r ₉ are added and stored in the register r ₃ . As a result, the data stored in the register r ₂ is output to the port AIN of the ALU 13, the data stored in the register r ₉ is output to the port BIN, and these additions are performed in the ALU 13. result via the bus 23 from the port AOUT, written into the register r ₃ of the general register module 11.

Further, "mov r ₃ , r ₁ " means that the data stored in the register r ₃ is transferred to the data register r ₁ . Thus, the data stored in register r _3, for example a bus 17, a multiplexer 12, bus 23, via multiplexer 16 and bus 25, is transferred to the data register r _1. Thereafter, the hardware registers the data register r with the address on the internal memory 47 stored in the DP register 31.
_The data stored in ₁ is automatically written via the bus 27.

As described above, in the microprocessor 1,
The load instruction “lw” and the store instruction “s” shown in FIG.
Instead of "w", a program describing an inter-register transfer instruction "mov" is executed as shown in FIG.

The program shown in FIG. 12 can be described, for example, as shown in FIG. In the program shown in FIG. 13, the data register r ₀ and the register r ₉ are specified as the source register of the instruction “add”, and the data register r ₁ is specified as the destination address. However, in this case, it is necessary that the DP registers 30 and 31 point to addresses in different banks on the internal memory 47. FIG.
The program shown in FIG.
Executed in clock cycles.

In the microprocessor 1, when processing data stored at consecutive memory addresses on the internal memory 47, for example, a program is described as shown in FIG. When the program shown in FIG. 14 is executed, the addresses stored in the DP registers 30 and 31 shown in FIG. 2 are sequentially updated by adding, for example, “+4”, thereby updating the data registers r ₀ and r _1. , Accesses are sequentially made to addresses at intervals of “+4” in the internal memory 47. In FIG.
“Add r ₀ , r ₉ , r ₁ ” is the data register r ₀
The stored data, by adding the data stored in the register r _9, show that for storing data of the addition result in the data register r ₁ is in. In the processing according to the program shown in FIG. 14, eight data on the internal memory 47 are processed. The program shown in FIG. 14 may be described using a loop.

In the microprocessor 1, for example, FIG.
DP of treatment, corresponding to the register r ₁₄ registers r ₁₄ of general register module 11 shown in the data register
By additionally providing a register, three paths for memory access can be provided. In this case, as shown in FIG. 15, by describing a program, the addition instruction “ad
Data registers r ₀ , r ₁₄ , and r ₁ can be specified in all three operands “d”.

As described above, according to the microprocessor 1, a part of the plurality of general-purpose registers constituting the general-purpose register module 11 is replaced with the data registers r ₀ and r _1.
Therefore, it is not necessary to separately describe a memory read instruction and a memory write instruction for accessing the internal memory 47 in the program. In other words, the instruction set can be described as an operation performed between the data stored in the general-purpose registers, even when a memory access is required. That is, according to the microprocessor 1, the access to the internal memory 47 is treated as an extension of the access to the general-purpose register, and the data registers r ₀ and r ₁ can be used as a memory window from software.

In the microprocessor 1, if the address of the internal memory 47 to be accessed and the access order are determined in advance, the DP register 30,
31, the DP register 30,
By automatically updating the address stored in 31, there is no need to explicitly describe the procedure for memory access every time in a program.

Therefore, when sequentially accessing and processing a plurality of data stored at consecutive addresses in the memory address space of the internal memory 47, it is not necessary to specify the address of the data to be accessed each time. Only the ALU operation instruction needs to be described. At this time, with respect to the data registers r _0, r _1, DP register 30,
By reading data from the internal memory 47 immediately after the 31 is automatically updated, it is possible to avoid waiting for the ALU 13 to complete the memory access every time the ALU operation instruction is executed. That is, at the time when the ALU 13 executes the ALU operation according to the program, the data can be already read from the internal memory 47 to the data registers r ₀ and r ₁ . As a result, in the arithmetic processing in the microprocessor 1, multiplexing of instructions can be efficiently realized, and for example, in pipeline processing, an ALU arithmetic instruction can be executed every clock cycle.
Further, the description of the program by the user can be simplified.

According to the microprocessor 1, 2
By providing the DP registers 30 and 31 and executing the ALU operation instruction directly on the data on the internal memory 47, for example, after reading and processing the data on the internal memory 47, The rewriting process can be described by one instruction. Moreover, in this instruction, if the bank of data read from the internal memory 47 is different from the bank of data written to the internal memory 47, the instruction can be executed within one clock cycle. Note that DP register 3
If both 0 and 31 can specify all the addresses of the internal memory 47, the instruction is executed within one clock cycle if the address of the data read from the internal memory 47 is different from the address of the data written to the internal memory 47. it can. For example, in a program, arithmetic processing involving memory access can be described by, for example, one instruction as shown in FIG. 13 and executed within one clock cycle.

[0054] Further, the microprocessor 1, when performing write back data to the internal memory 47 instructions (data transfer instruction specifying the data register r ₀ or r ₁ as the destination register) successively, DP
The automatic read function of the registers 30 and 31 is stopped, and unnecessary memory read can be eliminated. As a result, memory writes can be executed continuously, and multiplexing of instructions can be realized.

In the microprocessor 1, the memory configuration using the data registers r ₀ and r ₁ and the DP registers 30 and 31 eliminates the need for the MEM stage in the conventional five-stage pipeline structure shown in FIG. As shown in FIG. 4, a four-stage pipeline structure can be adopted. That is, since the write operation is performed on the internal memory 47 using the data registers r ₀ and r ₁ , the write operation on the internal memory 47 can be performed by the register write operation performed in the WB stage. Therefore, it is not necessary to provide a memory access processing stage independently in the pipeline processing. As a result, in the microprocessor 1, the control circuit of the entire processor is simplified, and it is possible to flexibly cope with exception processing including an external interrupt.

Second Embodiment The microprocessor according to the second embodiment is characterized in that the number of banks of the internal memory, the number of data registers and DP registers, and that a multiplexer 82 is provided instead of the multiplexers 12 and 16 shown in FIG. Except, basically,
It has the same configuration as the microprocessor 1 of the first embodiment described above. FIG. 16 is a configuration diagram around the internal memory 87 of the microprocessor 81 of the present embodiment. FIG.
As shown in 6, the microprocessor 81 includes an internal memory 87, DP register 91, 92 and 93, the data register _{r 0, r 1 -R, r} 1 -W, a multiplexer 82 and bus 101-106.

The microprocessor 81 includes an ALU 13, a program counter 34, an instruction page memory 35, a decoder 36, and buses 17, 18, 19, 20, and 2, similarly to the microprocessor 1 shown in FIG.
3 is provided. In the microprocessor 81,
Instead of the register r ₁ shown in FIG. 1, the register r ₁ -R
And a register r ₁ -W. That is, the microprocessor 81 has registers r _{2 to} r _{15 in} addition to the data registers r ₀ , r ₁ -R, and r ₁ -W shown in FIG.
Is provided. The microprocessor 81 logically handles the physical data registers r ₁ -R and the data registers r ₁ -W as a single data register r _{1 in} the description of the program.

In the microprocessor 81, the memory bank 11 of the internal memory 87 stored in the DP register 91
Data is read from the address in ₀ and stored in the data register r0. The data register r ₁ -R is
A data read operation only from the memory bank 111 of internal memory 87, when the address of the logical data register r ₁ is designated in the second operand arithmetic instructions written in the program as the destination register, DP register 92 The data read from the address in the memory bank 111 stored in the memory cell is stored. Further, the data register r ₁ -W stores the internal memory 8
7 is a data write operation only with respect to the memory bank 112, if specified address of a logical data register r ₁ as the destination register in the two-operand arithmetic instructions written in the program, the data register r ₁ -W is stored in D
Write to the address in the memory bank 112 stored in the P register 93. Note that the logical data register r ₁
In addition to specifying the logical address directly,
For example, a logical address may be indirectly specified via a logical register name.

Hereinafter, the operation of the microprocessor 81 will be described. In the microprocessor 81, for example,
A two-operand operation instruction having the format shown in FIG. 6 is executed. In the microprocessor 81, for example, FIG.
As shown in FIG. 7, when the data register r ₁ executes the instruction specified by the destination address, first, the address in the memory bank 111 in which the data to be added is stored is written to the DP register 92, The data to be added is read out to the data register r ₁ -R via the bus 102 by hardware. Next, the ALU13 shown in FIG. 1, the data stored in the register r _5, performs addition operation between data stored in the data register r ₁ -R, data register data of the addition result through the bus 106 Store it in r ₁ -W ₀ .
The memory bank 112 to which the data of the addition result is written back
Is written into the DP register 93. As a result, the data of the addition result stored in the data register r ₁ -W ₀ is written back to the memory bank 112 via the bus 103 by hardware.

Hereinafter, in the microprocessor 81,
A case where data stored at consecutive memory addresses on the internal memory 87 is processed will be described. In the microprocessor 81, for example, when the program shown in FIG. 18 is executed by the four-stage pipeline processing shown in FIG.
The result is as shown in FIG. Code C shown in FIG.
Each code ₁ -C _6, in the pipeline processing shown in FIG. 19 (A), the instruction in the IF stage "the add r _0,
Fetching r ₁ "is performed, in DEC stage, one of the addition-target data from the stored address on the memory bank 110 has been read into the data register r ₀ in the DP register 91, the data register r ₀ of ALU13 Output to port AIN. At the same time, the DP register 92
The other addition target data read out from the address on the memory bank 111 stored in the memory register 111 to the data register r ₁ -R is transmitted from the data register r ₁ -R to the port B of the ALU 13.
Output to IN. Next, at the ALU stage, ALU1
3, the addition using both the addition target data is performed, and the addition result of the ALU 13 is
OUT is written to the data register r ₁ -W. Thereafter, the memory bank 11 stored in the DP register 93
The data stored in the data register r ₁ -W is written back to the address on 2.

At this time, as shown in FIG. 19A, the IF stage of the code C ₁ is performed in the clock cycle T. Further, as shown in FIG. 19 (B), in a clock cycle T + 1 to T + 6, a memory read operation for the data registers r ₀ by the code C ₁ -C ₆ (decode stage) is carried out in order. Further, as shown in FIG. 19C, the code C _{1 in} clock cycles T + _{1 to} T + 6.
The memory read operation (decode stage) for the data register r ₁ -R by C ₆ is sequentially performed. Further, as shown in FIG. 19D, the clock cycle T +
From 3 to T + 8, a memory write operation to the data register r ₁ -W by the codes C _{1 to} C ₆ (WB stage)
Are performed in order. That is, in the microprocessor 81, as described above, the data registers r ₁ -R, r _1-
By providing Wr ₀ , a memory read operation and a memory write operation for data register r ₁ can be performed simultaneously. As a result, the codes C _{1 to} C ₆ shown in FIG.
Can be executed in one clock cycle.

[0062] As described above, according to the microprocessor 81, a case where the specified logical data register r ₁ to the destination address performed continuously repeated 2 operand operation instruction for performing the read-modify-write Also, each operation instruction can be executed in one clock cycle. According to the microprocessor 81,
By using a two-operand operation instruction, three different data on the internal memory 87 are accessed in the same clock cycle, and an operation substantially equivalent to a three-operand operation can be realized.

Third Embodiment In the above-described microprocessors of the first and second embodiments, a case where a plurality of data registers and a plurality of banks of the internal memory are fixedly associated with each other in one-to-one correspondence. explained. Therefore, in these microprocessors, it is necessary to provide data registers and DP registers in a number corresponding to the number of banks of the internal memory. Therefore, when the number of banks of the internal memory is large, it is necessary to provide a large number of data registers and DP registers. The microprocessor according to the present embodiment differs from the microprocessor 1 described above in that the microprocessor 1 has a single data register.
The configuration is such that a plurality of banks of the internal memory can be accessed.

FIG. 20 is a configuration diagram around the ALU 13 of the microprocessor 121 of this embodiment, and FIG. 21 is a configuration diagram around the internal memory 147 of the microprocessor 121. In FIGS. 20 and 21, the same components as those shown in FIGS. 1 and 2 are denoted by the same reference numerals. The microprocessor 121 includes a general-purpose register module 123 and a multiplexer 12 shown in FIG.
5, 127, ALU 13, program counter 34, instruction page memory 35, and decoder 36
And the internal memory 147 and the DP register 14 shown in FIG.
9, main memory 150, bank selection module 15
1. A configuration in which the local bus 153 and the control circuit 180 are incorporated in, for example, one chip. The microprocessor 121 is basically the same as the microprocessor 1 of the above-described first embodiment, including, for example, four-stage pipeline processing, except for the relationship between the data register r ₀ and the banks 161 to 164 of the internal memory 147. It is.

The general-purpose register module 123 is a data register r from the general-purpose register module 11 shown in FIG.
₁ and buses 25 and 27 are excluded. The multiplexer 125 is the same as the multiplexer 16 shown in FIG. 1, except that the multiplexer 125 does not have a selection function for the buses 25 and 22 shown in FIG. The multiplexer 127 does not have the function of selecting the bus 22 shown in FIG. 1 except that the multiplexer 127 shown in FIG.
Is the same as

[0066] DP register 149 has a storage capacity capable of storing the address of the whole area of the memory address space the microprocessor 121 makes an access, at the time of memory read, the address of the memory address space of the data to be read into the data register r ₀ stored, during memory write, stores the address of the memory address space is a write destination of data stored in the data register r _0.

As shown in FIG. 22, DP register 149 has a 32-bit field and stores a 32-bit address. As a result, a memory address space having an address of up to 4 Gbytes can be used. The 32-bit field of the DP register 149 includes a page select field 200, a page offset field 201, and a field 202.
The page select field 200 includes bits “9” to
The start address (offset) of a page (memory block) in the memory address space of the main memory 150 is specified by “31”. In this embodiment, the capacity of one page is 512 bytes. Also,
The page offset field 201 includes bits “2” to
It is composed of "8" and indicates an offset within the page. Here, in the page, memory access is performed in units of 4 bytes. The field 202 is constituted by bits “0” and “1”, and is not used to specify an address.

The internal memory 147 is divided into four banks 161, 162, 163 and 164, as shown in FIG. Banks 161, 162, 163, 164
Is connected to the DP register 149 via the local bus 152.
It is connected to the. Here, the local bus 152
Of the P register 149, it is connected only to a page offset field 201 shown in FIG. 22, which will be described later, and has a bus width of 7 bits. Banks 161, 162, 16
3,164, via the local bus 153, and is connected to the data register r _0.

[0069] Bank 161 to 164 each have a capacity of one page, as described below, and stores the pages read from the main memory 150 in response to the selection signal S179 ₁ ~S179 ₄ from the selection circuit 179. Bank 1
The data (pages) on the main memory 150 that are read into 61 to 164 do not overlap each other. In other words, when a page corresponding to the address stored in the DP register 149 is stored in the banks 161 to 164, the selection circuit 179 performs memory access to the page and stores the same page in the main memory. This is because the operation of reading from the 150 is not performed. Therefore, data of the same memory address is not stored in two or more of the banks 161 to 164.

When the banks 161 to 164 input the selection signals S179 _{1 to} S179 ₄ each indicating an enable instruction when performing a read operation on the data register r ₀ , the page offset field 201 of the address stored in the DP register 149 is input. 4 bytes of data are read from the address in the page indicated by, and the read data is transferred to the data register r ₀ via the local bus 153. The data register r ₀ stores the transferred data.

In the write operation from the data register r ₀ , the banks 161 to 164 input the selection signals S 179 _{1 to} S 179 ₄ each indicating an enable instruction, and transfer the 4-byte data stored in the data register r ₀ to the local bus. 153 and the DP register 1
49 is stored at the address within the page indicated by the page offset field 201 of the address stored in 49.

The internal memory 147 has a local bus 153
Through the main memory 150. The main memory 150 may be built in the chip of the microprocessor 121 or provided outside the chip.

As shown in FIG. 21, the bank selection module 151 includes a DPC (Data PointerCache) register 17.
0,171,172,173, comparators 174,175,
176, 177 and a selection circuit 179. DPC
The registers 170, 171, 172, and 173 store the head addresses of the pages stored in the banks 161, 162, 163, and 164 on the main memory 150, respectively. This start address corresponds to the page select field 200 of the address stored in the DP register 149 shown in FIG. Here, the comparators 174 to 17
7, since only the page select field 200 of the addresses stored in the DP register 149 needs to be compared, the DPC registers 170, 171, 17
2,173 only needs to include 23 bits for storing an address corresponding to the page select field 200 among the 32-bit addresses stored in the page select field 200.

DPC registers 170, 171, 172,
The addresses stored in 173 are stored in the respective banks 16
When the pages stored in 1, 162, 163, 164 and the pages stored in the main memory 150 are replaced, the page is updated by the page select field 200 of the address stored in the DP register 149.

The comparators 174, 175, 176, 177
Are the DPC registers 170, 171, 172,
173, and compares the start address of the page on the main memory 150 with the address stored in the page selector field of the DP register 149, and compares the comparison result with the comparison data S174, S175, S176, S1.
77 as the ports in0, in1, i of the selection circuit 179
Output to n2 and in3 respectively. Note that the comparator 17
The comparison process in 4,175,176,177 is DP
This is performed every time the address stored in the register 149 is updated.

The selection circuit 179 outputs the comparison data S 174,
Based on each of S175, S176, and S177,
Select signals S179 ₁ , S179 ₂ , and S17 instructing enable when the comparison result indicates a match, and disabling when the comparison result does not match.
9 ₃ , S179 ₄ into banks 161, 162, 163, 1
64 are continuously output. The selection circuit 17
No. 9 switches the selection signals S179 _{1 to} S179 ₄ between an enable instruction and a disable instruction when the comparison data S174 to S177 change.

The selection circuit 179 outputs the comparison data S1
74, S175, S176, if all of S177 indicates that a mismatch, and outputs an instruction signal S179 ₅ showing a page fault to the control circuit 180. Control circuit 1
80 inputs the instruction signal S179 ₅ showing a page fault, reads a page from the start address of the main memory 150 indicated by the page selector field of the address stored in the DP register 149,
This page is stored in the internal memory 1 via the local bus 153.
Read into 47. The new pages read into the internal memory 147 are stored in the banks 161 to 1 of the internal memory 147.
Of the four pages stored in 64, the page that is accessed first is replaced. That is, LRU (L
east Recently Used) method. Note that the page replacement algorithm is not limited to LRU, and various methods can be adopted. Here, the detection of a page fault often becomes a critical path on a circuit, similarly to the determination of a cache hit in a microprocessor using a cache system. Here, the critical path is a factor that determines the highest operating frequency of the LSI.

Next, the microprocessor 121
Will be described. FIG. 23 is a flowchart illustrating a memory access operation of microprocessor 121. First, an instruction is fetched from the address indicated by the program counter 34 on the instruction page memory 35 shown in FIG.
The data is decoded in the decoder 36. At this time, if the decoded instruction is an operation instruction using data in the memory address space of the main memory 150, the address of the data in the memory address space of the main memory 150 is changed to the DP shown in FIG. It is stored in the register 149 (step S1).

Next, in the comparators 174 to 177, the page select field 200 of the address stored in the DP register 149 and the DPC register 170
173 are compared with each other, and the comparison data S174 to S177 are output to the selection circuit 179 (step S2).

Next, in the selection circuit 179, it is determined whether or not any of the comparison data S174 to S177 indicates an address match (step S3). Include banks 161 to 16 corresponding to the comparison data S174 to S177.
4, instruction signals S179 ₁ to ₁ indicating enable.
79 ₄ to output. As a result, the banks 161 to 161 to which the instruction signals S179 _{1 to} 179 ₄ indicating enable are input are provided.
At 164, data is read from the address in the page indicated by the page offset field 201 of the address stored in the DP register 149, and the read data is transferred to the data register r ₀ via the local bus 153. The data is transferred and stored (step S4).

On the other hand, if the selection circuit 179 determines that all of the comparison data S174 to S177 indicate mismatch (step S3), the main memory is written using the LRU algorithm described above. Fifteen
From 0, it is determined that the corresponding page is to be read out to the internal memory 147 via the local bus 153 (step S).
5).

The banks 161 to 161 of the internal memory 147 which have been replaced by the LRU algorithm
It is determined whether or not the dirty bit exists in the page stored in the memory 164 (step S6).
(Step S8). Here, the dirty bit is added when, for example, the microprocessor 121 has written to the page.

Next, in step S5, the banks 161 to 164 of the internal memory 147 to be replaced are set.
Next, the page pointed to by the address stored in the DP register 149 is read from the main memory 150 via the local bus 153, and the pages are replaced (step S7). At this time, the address stored in the DPC registers 170 to 173 corresponding to the replaced banks 161 to 164 is updated by the page select field 200 of the address stored in the DP register 149.

On the other hand, the bank 16
Even when the dirty bits do not exist in the pages stored in Nos. 1 to 164, the replacement target page is replaced with the page read from the main memory 150, but the write back to the main memory 150 is not performed. (Step S7).

FIG. 24 is a timing chart of memory access in microprocessor 121 shown in FIGS. 20 and 21. As shown in FIG. 24A, access to bank 161 and its procedure (operation) are performed in the first five cycles, and access and procedure to bank 162 are performed in the next five cycles. In the three cycles, access to the bank 163 and its procedure are performed. Note that in FIG. 24 (A), "X" indicates an operation for updating the address stored in the DP register 149, "Y" operations to perform a read operation or a write operation to the data register r ₀ Is shown. Here, it is assumed that the banks 161 to 164 already hold valid data.

FIG. 24B shows the timing of the address stored in the DP register 149 when performing an access operation to the bank 161. The address "A0",
"A1", "A2", "A3", "A4", "A5"
Have the same address for the page select field 200 shown in FIG. FIG. 24C illustrates data on which a read operation or a write operation is performed on the bank 161. The data shown in FIG. _24C is stored in the data register r0.

FIG. 24D shows the timing of the address stored in the DP register 149 when the access operation to the bank 162 is performed.
0 "," B1 "," B2 "," B3 "," B4 "," B
5 "is the page select field 200 shown in FIG.
Are all the same. FIG. 24 (E)
Indicates data for which a read operation or a write operation is performed on the bank 162. The data shown in FIG. _24E is stored in the data register r0.

FIG. 24F shows the timing of the address stored in the DP register 149 when the access operation to the bank 163 is performed.
"0", "C1", "C2", and "C3" all have the same address corresponding to the page select field 200 shown in FIG. FIG. 24G illustrates data on which a read operation or a write operation is performed on the bank 163. Data shown in FIG. 24 (G) is stored in the data register r _0.

FIG. 24H shows the timing of the address stored in the DP register 149 when the bank 164 is accessed, and FIG.
Indicates data for which a read operation or a write operation is performed on the bank 164.

As shown in FIGS. 24A, 24B and 24C, in the first cycle, the address “A0” is written to the DP register 149 in order to select the bank 161. As a result, the page offset field 201 of the address “A0” in the bank 161 is stored in the data register r _0.
Data is read out from the address indicated by, as shown in FIG. 24 (C), is output data "d0" from the data port of the bank 161, the data "d0" is stored in the data register r _0. Thereafter, in the microprocessor 121, as described in the microprocessor 1 of the first embodiment, the address of the DP register 149 is automatically updated, and successive addresses in the bank are sequentially accessed.

The data register r ₀ contains the DP register 1
In the next cycle after updating the address stored in 49,
Prefetch data unless otherwise specified. Therefore, in the second cycle, the address “A0” is updated to “A1”. As a result, the data “d1” is read from the address “A1” of the bank 161 and the data of the bank 1 is read.
It is output from 61 data ports. In the second cycle, since the bank 161 is selected, immediately after the data “d0” stored in the data register r ₀ is output to the input port of the ALU 13 shown in FIG.
Data “d1” is output from the 61 data ports.

Thereafter, similar processing is performed, and FIG.
As shown in the figure, the data “d” is stored in the data register r _0.
"0" to "d12" are sequentially stored.

As described above, according to the microprocessor 121, by providing the bank selection module 151, the four banks 161 to 164 can be accessed using the single DP register 149. The DPC registers 170 to 1 of the bank selection module 151
At 73, the user cannot access in a normal manner, and does not need to be managed by the user.

By the way, if a fixed data register is provided for each bank of the internal memory as in the first and second embodiments, if the number of general-purpose registers is limited, a register that can be used as a general-purpose register is used. May be reduced, and an increase in processing capacity may be suppressed. In contrast, in the microprocessor 121, all banks data register r ₀ is the four single 161 to
Since data transfer with 164 can be performed, only one of the 16 registers provided in the general-purpose register module 123 needs to be provided as the data register r ₀ . As a result, the number of registers that can be used as general-purpose registers can be increased, and the processing capability can be further improved as compared with the first embodiment and the second embodiment. The microprocessor 121 is particularly effective when the number of banks of the internal memory is large.

According to the microprocessor 121, the DPC registers 170 to 173 store the DP register 1
Since only the portion of the address stored in the DP 49 corresponding to the page select field 200 is stored, the DPC registers 170 to 173 and the comparator 1 are compared with the case where the entire address stored in the DP register 149 is stored.
Circuits 74 to 177 can be reduced in size. Also, the comparator 17
4 to 177 can be performed at high speed.

Further, according to the microprocessor 121, the comparators 174 to 177 for the number of banks are provided to parallelize the comparison processing, so that in the same cycle as when the address stored in the DP register 149 is updated, Bank 161
Desired data can be read from.

Further, according to the microprocessor 121, the address stored in the DP register 149 has a format including the page select field 200 and the page offset field 201 as shown in FIG. With 151, the same page can be prevented from being stored in a plurality of banks among the banks 161 to 164 with a simple configuration, and the internal memory 147 can be used efficiently. Also, DP register 1
Only the 49 page offset fields 201 need be connected to the internal memory 147, and the bus width of the local bus 152 can be reduced.

Further, according to the microprocessor 121, only necessary fields among the addresses stored in the DP register 149 are transferred to the DPC register 170 and the banks 161 to 164, so that the number of address lines is suppressed. it can. In general, in order to obtain a high access speed, it is preferable that the address line be short and have a small capacity. Further, it is preferable that the number of wirings used as addresses is small. This is because the effects of the power associated with the access and the power supply wiring capacitance cannot be ignored. Note that the microprocessor 121 can also obtain the same effects as those of the microprocessor 1 of the first embodiment.

The present invention is not limited to the above embodiment. For example, in the microprocessor 121 described above,
Although the case where data transmission between the DP register 149 and the main memory 150 and the banks 161 to 164 is performed via the local bus 153 has been described as an example, in the microprocessor 121, for example, as shown in FIG. , 153b may be used to realize this data transmission.

In this case, as shown in FIG. 25, the data register r ₀ is connected to the local bus 153a, and the main memory 150 is connected to the local bus 153b. The banks 161 to 164 are connected to local buses 153a and 153b via multiplexers 301 to 304, respectively. Multiplexers 301-304
Respectively connects the banks 161 to 164 with the local bus 1
Selectively connect to one of 53a and 153b. The control circuit 300 transmits the control signal S300a to the bank 1
Output to 61-164, controls the reading and writing of data between the data register r _0. Further, the control circuit 300 transmits the control signal S300b to the banks 161-1.
64 to control the page exchange processing with the main memory 150.

[0102] By adopting the configuration as shown in FIG. 25, pages between the data transfer and the other bank and the main memory 150 of between one bank and data registers r ₀ of the bank 161 to 164 The replacement process can be performed (multiplexed) in parallel. Therefore, it is possible to hide the time required for the page replacement process due to the page fault.

In the microprocessor 121, a single DP register 149 is stored in the general-purpose register module 11.
Is provided, but the present invention provides a plurality of D
A configuration may be adopted in which a P register is provided, at least one of which can be connected to a plurality of banks.

In the microprocessor 121, D
The case where the comparison process is performed by the comparators 174 to 177 every time the address stored in the P register 149 is updated has been described. For example, the page stored in the DP register 149 is controlled by the selection circuit 179 or the control circuit 180. Whether or not the select field 200 has been updated may be monitored, and only when the page select field 200 is updated, the comparators 174 to 177 may be controlled to perform the comparison process. By performing control in this manner, the frequency of execution of the comparison processing in the comparators 174 to 177 can be significantly reduced, and power consumption can be reduced.

Also, the microprocessor 121
In the above, the case where four banks are provided in the internal memory 147 has been exemplified, but in the present invention, the number of banks provided in the internal memory is arbitrary as long as it is two or more. Also, in the microprocessor 121 described above, the DPC register 170
173 stores only the page select field 200 of the DP register 149, but the DPC registers 170 to 173 store the entire address stored in the DP register 149 or the page select field 200 and the page offset field 201. Only the information may be stored.

In the microprocessor 1, the case where two general-purpose registers among the general-purpose register modules 11 are used as the data registers r ₀ and r ₁ has been exemplified. However, if the number of data registers is one or more, Optional. The usage of the data registers r ₀ and r ₁ is as follows.
Instead of being used as an interface with the internal memory 47, for example, it may be used as a FIFO (First In First Out) memory when performing communication between microprocessors in a parallel processor equipped with a plurality of microprocessors. Further, data registers r ₀ , r
₁ may be used as a local memory or a stack memory.

Further, in the microprocessor 1, as shown in FIG.
The functions of the multiplexer 16 may be incorporated in the multiplexer 12.

Further, in the microprocessor 1, as shown in FIG. 2, the internal memory 47 is divided into two banks, but the internal memory 47 is divided into three or more banks, or the banks are not divided. It may be configured.

Further, in the microprocessor 1, as shown in FIG. 1, the general-purpose register module 11 is provided with data registers r ₀ and r ₁ as a part of a plurality of general-purpose registers. May be provided with data registers r ₀ and r ₁ so as to be handled separately from general-purpose registers.

In the microprocessor 81 having the memory structure shown in FIG. 16, three FIFO memories are provided instead of the internal memory 87, and the data register r _1-
A configuration may be adopted in which an input FIFO memory is connected to R and an output FIFO memory is connected to the data register r ₁ -W.

[0110]

As described above, according to the arithmetic processing device and the memory access method of the present invention, data transfer between arithmetic means and a plurality of banks of the internal memory via a single data register. And the register resources can be used effectively. As a result, even when a general-purpose register is used as the data register, the function of the general-purpose register can be properly exhibited. According to the arithmetic processing device and the memory access method of the present invention,
By realizing access to the internal memory using the data register, access to the internal memory can be treated in the same way as access to the register.
As a result, the burden on the user when creating a program can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a microprocessor according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining a data register, a DP register, and an internal memory of the microprocessor shown in FIG. 1;

FIG. 3 is a diagram for explaining a configuration of a general-purpose register module shown in FIG. 1;

FIG. 4 is a diagram for explaining a four-stage pipeline process of the microprocessor shown in FIG. 1;

FIG. 5 is a diagram for explaining the pipeline process of the microprocessor shown in FIG. 1;

FIG. 6 is a view for explaining a format of a two-operand operation instruction used in the microprocessor shown in FIG. 1;

FIG. 7 is a diagram for explaining an operation instruction when a data register is specified as a source register in the operation instruction shown in FIG. 6;

FIG. 8 is a diagram for explaining an operation instruction when a data register is designated as a destination register in the operation instruction shown in FIG. 6;

FIG. 9 is a diagram for explaining an operation instruction when a data register is designated as both a source register and a destination register in the operation instruction shown in FIG. 6;

FIG. 10 is a diagram for explaining a stall in pipeline processing that occurs when the operation instructions shown in FIG. 8 are continuously performed.

FIG. 11 is a diagram for explaining a format of a three-operand operation instruction used in the microprocessor shown in FIG. 1;

12 is a diagram for describing a program in the microprocessor shown in FIG. 1 that describes processing similar to the program shown in FIG. 30 in a conventional microprocessor.

13 is a view for explaining a program in which the same processing as the program shown in FIG. 12 is described in the microprocessor shown in FIG. 1 by designating a data register as a source register and a destination address; It is.

FIG. 14 is a diagram for explaining a program showing a process of processing data stored at consecutive memory addresses on an internal memory in the microprocessor shown in FIG. 1;

FIG. 15 is a diagram for explaining a program including an instruction in which a data register is specified in all three operands of an addition instruction in the microprocessor shown in FIG. FIG.

FIG. 16 is a configuration diagram around an internal memory of a microprocessor according to a second embodiment of the present invention.

FIG. 17 shows two-operand operation instructions.
FIG. 4 is a diagram for describing an example in which a data register is specified as a destination address.

FIG. 18 is a diagram for explaining a program for processing data stored in continuous memory addresses on an internal memory in the microprocessor according to the second embodiment of the present invention.

FIG. 19 is a diagram for explaining a case where the program shown in FIG. 18 is executed by the four-stage pipeline processing shown in FIG. 4;

FIG. 20 is a configuration diagram around an ALU of a microprocessor according to a third embodiment of the present invention;

FIG. 21 is a configuration diagram around an internal memory of the microprocessor shown in FIG. 20;

FIG. 22 is a diagram for explaining a configuration of a DP register shown in FIG. 21;

FIG. 23 is a flowchart illustrating a memory access operation of the microprocessor shown in FIGS. 20 and 21;

FIG. 24 is a timing chart of memory access in the microprocessor shown in FIGS. 20 and 21;

FIG. 25 is a configuration diagram of a modification around the internal memory of the microprocessor shown in FIG. 21;

FIG. 26 shows a conventional RISC type and CISC type.
FIG. 4 is a diagram for explaining general-purpose registers of a type microprocessor.

FIG. 27 is a diagram for explaining an ALU operation instruction having three register specifiers in a conventional microprocessor.

FIG. 28 is a diagram for explaining an instruction for processing data on a memory in a conventional microprocessor.

FIG. 29 is a diagram for explaining a five-stage pipeline process of a conventional microprocessor.

FIG. 30 is a diagram for explaining a program for processing in which data on a memory is subjected to an ALU operation in the five-stage pipeline processing shown in FIG. 29;

FIG. 31 is a diagram for explaining a program of a process of repeatedly accessing addresses at a predetermined distance in a memory address space in a conventional microprocessor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Microprocessor, 11, 123 ... General-purpose register module, 12, 16, 125, 127 ... Multiplexer, 13 ... ALU, 21, 22, 23, 24, 25,
26, 27 bus, 30, 31, 149 DP register, 35 instruction page memory, 36 decoder, 45, 46 bank, 47, 147 internal memory, 50 external main memory, 150 main memory,
151: Bank selection module, 152, 153: Local bus, 161-164: Bank, 170-173 ...
DPC register, 174 to 177 comparator, 179 selection circuit, 180 control circuit

Claims (11)

[Claims] 1. An internal memory having a plurality of banks for storing pages of a predetermined data amount stored at consecutive addresses in a memory address space, and a data pointer register for storing addresses in the memory address space. Arithmetic means for performing arithmetic processing; a data register for transferring data between the internal memory and the arithmetic means; and storing a head address in a memory address space of a page stored in the plurality of banks. Comparing the stored start address with the address stored in the data pointer register, and determining whether there is a page to be accessed in any of the plurality of banks based on a result of the comparison. Page presence / absence determination means for determining whether the plurality of banks are to be accessed as a result of the determination. Control means for controlling transfer of data between a bank in which a page to be accessed is stored and the data register by using an address stored in the data pointer register, if any An arithmetic processing unit having: 2. The apparatus according to claim 2, further comprising a main memory having the memory address space, wherein the control unit determines that the page to be accessed does not exist in any of the plurality of banks as a result of the determination. 2. The arithmetic processing device according to claim 1, wherein a page to be accessed is read from the plurality of pages and replaced with a page stored in the plurality of banks. A plurality of first address storage means for storing first addresses of the pages stored in the plurality of banks in the memory address space; and a plurality of the first address storage means. A plurality of comparing means for respectively comparing the stored head address and the address stored in the data pointer register; and accessing any one of the plurality of banks based on a comparison result of the plurality of comparing means. And determining means for determining whether or not a page to be present exists, wherein the control means, based on a determination result of the determining means,
Using the address stored in the data pointer register between the bank corresponding to the comparing means in which the start address and the address stored in the data pointer register match as a result of the comparison, using the address stored in the data pointer register. The arithmetic processing device according to claim 1, wherein control is performed so as to perform transfer. 4. The page presence / absence determination means determines whether or not a page to be accessed exists in any of the plurality of banks each time an address stored in the data pointer register is updated. Claim 1
An arithmetic processing unit according to item 1. 5. An address in the memory address space stored in the data pointer register includes an offset address of a page in the memory address space and an offset address of data in the page. The page presence / absence determining means stores an offset address of the page in the memory address space of the page stored in the plurality of banks, and an offset address of the stored page and an address stored in the data pointer register. 2. The arithmetic processing device according to claim 1, wherein the arithmetic processing device compares the offset address of the page included in the data. 6. The arithmetic processing device according to claim 5, wherein said page presence / absence determination means performs said comparison only when an offset address of said page included in an address stored in said data pointer register is updated. . 7. The arithmetic processing device according to claim 1, wherein data stored in said memory address space is stored in a plurality of banks of said internal memory so as not to be duplicated. 8. The data read from the address stored in the data pointer register in the plurality of banks is transferred to the data register and stored, and the data stored in the data register is transferred to the arithmetic means. The arithmetic processing device according to claim 1, which performs a memory read operation. 9. The arithmetic processing device according to claim 1, wherein data is written to said data register at an address in said plurality of banks stored in said data pointer register to perform a memory write operation. 10. The arithmetic processing device according to claim 1, wherein a part of a plurality of general-purpose registers is used as said data register. 11. An arithmetic unit via a data register,
A memory access method for accessing an internal memory having a plurality of banks for storing pages of a predetermined data amount stored at consecutive addresses on a memory address space, comprising: Storing the first address in the memory address space of the page stored in the plurality of banks in the memory address space; comparing the stored first address with the address stored in the data pointer register; Based on the result of the comparison, it is determined whether a page to be accessed exists in any of the plurality of banks. As a result of the determination, the page to be accessed exists in any of the banks. Between the bank where the page to be accessed is stored and the data register, Memory access method for transferring data using the address stored in the data pointer register.