JPH1165841A - Arithmetic processor and its method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently perform processing accompanied with successive access to a memory address space by performing arithmetic processing by using data stored in a 1st data register and writing the result in a 2nd data register when a 2-operand arithmetic instruction is decoded. SOLUTION: A decoder 36 decodes an instruction. According to the control signal S36 corresponding to the result, multiplexers 12 and 15, ALU 13, etc., are controlled. For example, the 2-operand arithmetic instruction specifies a data register r0 as a source register and a data register r1 as a destination register. Data from an internal memory are read out to the registers r0 and r1, respectively. The data stored in the register r0 and the data stored in the register r1 are added and the sum data are written in the register r1. Then the data stored in the register r1 is written to the internal memory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to an arithmetic processing device and a method thereof.

[0002]

2. Description of the Related Art Conventional microprocessors and DSPs
In general, a digital signal processor reads data from a register, performs an operation, and writes the operation result in the read register. Also, in view of the history of the development of the processor, it is common that the register only temporarily stores data and does not use it for other purposes. As technology evolves, for example, processors such as Intel's 8088 (trade name)
The use form of registers has also been diversified, such as using a general-purpose register (C-reg) as a loop counter of a program.

[0003] However, M3000 R3000
Some processors, such as (product name), fix the value of read data to a specific value when reading data from a register. The R3000 includes 32 32-bit general-purpose registers.
Is always returned as "0" when read. Note that writing can be designated for the general-purpose register r0 on the program, but it has no particular meaning.

[0004] In the above-mentioned R3000, a three-operand operation instruction is executed. In the three-operand operation instruction, three registers are specified at the same time. Two of them are source registers and the other is a destination register. The R3000 does not execute a read-modify-write, but has an instruction system in which a register to be read and a register to be written can be specified physically independently. In this instruction system, the same register may be designated as a register to be read and a register to be written.

By the way, in configuring an instruction set of a processor, an instruction length determines an operation system of a register. In Intel's 8088, the operation between registers is realized by a 2-byte instruction. However, 80
Since 88 employs a variable length instruction system, an operation instruction for performing memory access may have an instruction length of 3 bytes or more. However, in any case, the 2-operand operation instruction is based on the architecture of 8088. In the two-operand operation instruction, two registers are specified at the same time.
Here, one designates a source register and the other designates a destination register. In this case, the destination register is a register to be read and is also a register to be written. That is, read-modify-write is executed for the destination register. With the two-operand operation instruction described above, ALU operation can be performed by accessing data on up to two different memories.

[0006]

In media processing such as image processing and audio processing, vector operations, particularly matrix multiplications, are often performed. In such operations, data on a continuous memory address space is specified. ALU operation is repeatedly performed. In order to perform such an operation at high speed, it is required to specify three memory addresses at the same time. A conventional microprocessor employing a two-operand operation instruction has a function to specify substantially three registers. Therefore, there is a problem that such a demand cannot be met.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems of the prior art, and has been made in consideration of the above-mentioned problems, and has been made in consideration of the above-described conventional technique by using a two-operand operation instruction capable of efficiently performing processing that involves continuous access to a memory address space in a predetermined pattern. It is an object to provide a processing device and a method thereof.

[0008]

In order to achieve the above object, an arithmetic processing unit according to the present invention comprises an internal memory for storing data to be operated and a first memory for storing an address on the internal memory. Data pointer register and second
A data pointer register, a first data register for storing data read from an address on the internal memory stored in the first data pointer register, and the internal data stored in the second data pointer register. A second data register for writing storage data to an address on a memory; an operation unit for performing an operation based on a decoding result; the first data register and the second data register;
When the two-operand operation instruction instructing to perform the read-modify-write operation is decoded by specifying the data register and the data register as the destination register using the same logical address, the operation means stores the instruction in the first data register. Perform arithmetic processing using the data obtained,
Decoding means for controlling a result of the arithmetic processing to be written to the second data register.

In the arithmetic processing device according to the present invention, the first data register and the second data register are designated as destination registers using the same logical address, and instruct to perform read-modify-write. When the operand operation instruction is executed, the first data register and the second data register function similarly to the case where the first data register and the second data register are designated as the source register and the destination register of the three-operand operation instruction, respectively.

Preferably, the arithmetic processing unit of the present invention performs read-modify-write by designating the first data register and the second data register as a destination register using the same logical address. When executing a two-operand operation instruction indicating that an instruction is to be executed, an instruction fetch process for reading an instruction from an address on an instruction memory indicated by a program counter, decoding the fetched instruction, and executing the first data register and the third A four-stage pipeline multiplexing a decoding process for transferring data from a data register to the arithmetic unit, an arithmetic process by the arithmetic unit, and a write-back process for writing an arithmetic result of the arithmetic process to the second data register. Perform processing.

Further, according to the arithmetic processing method of the present invention, the first data register and the second data register are designated as a destination register using the same logical address, and the third data register is designated as a source register. And
When executing a two-operand operation instruction instructing to perform a read-modify-write, an instruction fetch process of reading an instruction from an address on an instruction memory indicated by a program counter, decoding the fetched instruction, and executing the first data 4-stage multiplexed decoding processing for transferring data from a register and the third data register to the arithmetic means, arithmetic processing, and write-back processing for writing the arithmetic result of the arithmetic processing to the second data register Performing a pipeline process to read data from an address on the internal memory stored in the first data pointer register and storing the data in the first data register; and a process of reading data written in the second data register. On the internal memory stored in the second data pointer register The process of writing back to the address and the process of reading data from the address on the internal memory stored in the third data pointer register and storing the data in the third data register are performed in parallel with the four-stage pipeline process. Do.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a microprocessor according to an embodiment of the present invention will be described. First Embodiment FIG. 1 is a configuration diagram of a microprocessor 1 of the present embodiment. The microprocessor 1 includes a general-purpose register module 11, a multiplexer (MUX) 12, 1 shown in FIG.
6, an ALU (Arithmetic Logic Unit) 13, an instruction page memory 35, a decoder 36, the DP registers 30 and 31 and the internal memory 47 shown in FIG. 2, and these are incorporated in one chip.
In the microprocessor 1, the following processing is performed based on the control signal S36 according to the decoding result of the decoder 36.

The general-purpose register module 11 has, for example, 16 32-bit registers r ₀ to r ₀ to be generally used.
It is composed of a register set in r _15. The number of registers constituting the general-purpose register module 11 largely depends on the instruction set or the chip architecture, and is generally set in the range of 8 to 32. The general-purpose register module 11 is provided with seven ports W, RA, RB, MA, MB, DA, and DB, as shown in FIG. Here, port W is a write port and ALU
The data output from port AOUT of bus 13 is
3 and the general-purpose register module 1 via the port W
Written to 1. The ports MA and MB are connected to the memory banks 4 of the internal memory 47, respectively, as shown in FIG.
Ports between the buses 26 and 2 respectively.
7, data is transferred to and from the ports of the memory banks 45 and 46. It should be noted that the port R is provided outside the general-purpose register module 11 without providing the ports MA and MB.
A, RB, W may be switched to realize a connection with the memory banks 45, 46.

The ports RA and RB are read ports. Data read from the general-purpose register module 11 is output to the multiplexer 12 via the ports RA and RB and the buses 17 and 18. Further, the ports DA and DB are ports for performing bidirectional communication between the multiplexer 16 and the data registers r ₀ and r ₁ , respectively.

In the general-purpose register module 11, the ports W, RA, RB, MA, MB, DA, and DB can be used simultaneously. That is, general-purpose register module 1
1 can be executed independently of the read operation and the write operation.

In the microprocessor 1, the data registers r ₀ and r ₁ are used as buffers serving as interfaces for communicating with the memories via the buses 26 and 27, respectively. The register r ₂ ~r ₁₅ is used as a general-purpose register. In the microprocessor 1, for example, the internal memory 4 in the ALU 13
In the case of using the data stored in 7, the data is read out to the data register r ₀ via the bus 26, and then the data register r ₀ is accessed. At this time,
From the internal memory 47 via the bus 27, after reading the data into the data register r _1, may access the data register r _1. Further, the microprocessor 1, when writing data in the internal memory 47, after writing data to the data register r ₀ or r _1,
The written data is transferred to the internal memory 47 via the bus 26 or 27.

[0017] The data register r _0, r ₁ is the substantially the same topology and other registers r ₂ ~r _15, can also be used as well as general-purpose registers and register r ₂ ~r _15. Specifically, for example, the multiplexer 16
Selects the connection between the buses 21 and 22 and the ports DA and DB, the ports DA and DB
Performs the same function as RB, and buses 21 and 22
It performs the same function as 7 and 18. When the multiplexer 16 selects the connection between the bus 23 and the port DA or DB, the port DA or DB performs the same function as the port W. Therefore, the data registers r ₀ and r ₁ are uniformly described as a part of a general-purpose register group including the registers r _{2 to} r ₁₅ in the program, and are similarly recognized by the decoder 36.

DP (Data Pointer) registers 30, 31
Are the memory banks 45 and 46 of the internal memory 47, respectively.
The address in the memory address space is stored. In addition,
The DP registers 30 and 31 correspond to the general-purpose register module 1
Unlike one register r _{0 to} r ₁₅ , a part of a plurality of control registers is assigned. Therefore, DP register 3
0 and 31 cannot be directly specified using the register specifier of the ALU operation instruction, but are specified by a data transfer instruction. Writing an address on the internal memory 47 to the DP registers 30 and 31 requires one instruction step. However, an access operation to the internal memory 47 via the data registers r ₀ and r ₁ is required. Is not described in the program, and is performed in the background separately from the process directly specified in the program. That is, the access operation to the internal memory 47 is performed in parallel with the pipeline processing.

In the microprocessor 1, for example, FIG.
When the data stored in the memory bank 45 of the internal memory 47 is read, the address of the read data in the memory bank 45 is written to the DP register 30. As a result, the data stored in the address in the memory bank 45 written in the DP register 30 becomes
The data is automatically read from the memory bank 45 to the data register r ₀ via the bus 26 by hardware.
Thereafter, the multiplexer 16 is read from the data register r _0.
Is transferred to the port AIN or BIN of the ALU 13 via the.

Similarly, in the microprocessor 1, when reading data stored in the memory bank 46 of the internal memory 47 shown in FIG. 2, for example, the address of the read data in the memory bank 46 is stored in the DP register. Write to 31. As a result, the data stored in the address in the memory bank 46 written in the DP register 31 is automatically read out from the memory bank 46 to the data register r ₁ via the bus 26 by hardware. Thereafter, data is transferred from the data register r ₁ to the port AIN or BIN of the ALU 13 via the multiplexer 16.

As described above, in the microprocessor 1,
By writing the addresses in the memory banks 45 and 46 to the DP registers 30 and 31, the data stored at the addresses are automatically read out to the data registers r ₀ and r ₁ respectively.

On the other hand, the memory bank 45 of the internal memory 47
When data is written to a predetermined address in data registers 46 and 46, after writing the address to DP registers 30 and 31, respectively, data registers r ₀ and r
Write the relevant data to ₁ . Thereafter, the data stored in the data registers r ₀ and r ₁ are automatically written by hardware into the addresses in the memory banks 45 and 46 stored in the DP registers 30 and 31. In addition,
Data transfer between the data register r ₀ and the memory bank 45 and data transfer between the data register r ₁ and the memory bank 46 can be performed in the same pipeline cycle in the microprocessor 1.

When one of the data registers r _{0 and} r ₁ is used in a memory write operation to the internal memory 47, some cycles may be lost.
This is because the operation of automatically reading data from the data register r ₀ or r ₁ is unnecessary. To prevent this, if the data register r ₀ or r ₁ is set to the write operation only mode according to the purpose of use, it is possible to avoid performing unnecessary memory read (load) operation. As a characteristic of memory read or memory write, in the field of image processing or the like, there is a high possibility that consecutive memory addresses are referred to. That is, the memory read instruction is often executed again after the memory read instruction. Moreover, at this time, there is a high possibility that consecutive memory addresses are accessed. Therefore, for example, each time the data stored in the internal memory 47 is accessed, the stored address is set to, for example, +1, -1, +4, -4, +8, or-.
A function of automatically incrementing by eight is provided to improve processing efficiency when performing image processing.

The memory banks 45 and 46 of the internal memory 47 shown in FIG. 2 store copies of data in the memory address space of the external main memory 50 whose addresses are continuous. The addresses in the memory address space of the external main memory 50 do not need to be continuous between the memory banks 45 and 46.

The ALU 13 has input ports AIN, BIN
And an arithmetic operation or a logical operation on data input from the input ports AIN and BIN based on a control signal S36 from the decoder 36, and transfers the operation result data from the port AOUT to the bus 2
Output to 3. The ALU 13 executes an operation in one clock cycle. Here, depending on the type of the operation instruction, the ALU 13 transmits the ALU1 from the input port AIN or BIN based on the control signal S36 from the decoder 36.
In some cases, the data input to 3 is output from the output port AOUT as it is without performing the operation.

Hereinafter, a pipeline processing operation in the microprocessor 1 will be described. In the microprocessor 1, with the configuration shown in FIG. 1, the data path at the time of instruction execution has a four-stage pipeline structure as shown below. FIG. 4 is a diagram for explaining the pipeline processing of the microprocessor 1. As shown in FIG. 4, the microprocessor 1 includes an IF stage, a DEC stage,
A 4-stage pipeline of an ALU stage and a WB (Write Back) stage is adopted. That is, 4 shown in FIG.
The stage pipeline does not include the MEN stage of the conventional general five-stage pipeline shown in FIG.

In the four-stage pipeline shown in FIG.
The processing in the F stage, DEC stage and ALU stage is the same as in the case of the five-stage pipeline shown in FIG. In the four-stage pipeline shown in FIG. 4, the IF stage, the DEC stage, the ALU stage, and the WB stage are multiplexed and performed. Specifically, the microprocessor 1 fetches (reads) the next instruction to be executed from the address on the instruction memory 35 indicated by the program counter 34 shown in FIG. 1 in the first IF stage. Next, the second stage DEC
In the stage, the instruction fetched in the IF stage is decoded by the decoder 36 shown in FIG. The multiplexers 12, 16 and the ALU 13 are controlled based on the control signal S36 according to the decoding result.

If the instruction specifies the registers r _{0 to} r ₁₅ of the general-purpose register module 11 as the source register, the instruction is decoded in the DEC stage, and then the data from the data registers r _{0 to} r _{15 is} transmitted to the multiplexer 12. The data is read out to the ports AIN and BIN of the ALU 13 via the CPU. That is, in the microprocessor 1, in accordance with the program, can access data registers r _0, r ₁ as well as other general purpose register r ₂ ~r _15. At this time,
When a memory access to the internal memory 47 is necessary, a predetermined address on the internal memory 47 is stored in the DP registers 30 and 31 shown in FIG. 2, and then the data registers r ₀ and r ₁ are accessed. , The access to the internal memory 47 is realized. That is, the microprocessor 1 implements memory access to the internal memory 47 via the data registers r ₀ and r ₁ .

Next, in the third ALU stage, the ALU
Execute the operation instruction. The fetched instruction is ALU
If it is not an operation instruction, nothing is performed in the ALU stage, and data input from ports AIN and BIN are
The signal is directly output from the port AOUT 13. Next, 4
In the second WB stage, the ALU 13 for an instruction in which _one of the data registers r ₀ and r ₁ and the registers r _{2 to} r ₁₅ is designated as a destination register
Is written back to the specified register. At this time, by writing data to the data registers r ₀ and r ₁ , the internal memory 4 is indirectly connected via the buses 26 and 27.
Write the data back to 7.

[0030] In four-stage pipeline processing shown in FIG. 4, the code C ₁ is an instruction involving memory write operation to the internal memory 47 shown in FIG. 2, the memory code C ₃ is to the internal memory 47 In the case of an instruction accompanied by a read operation, in the clock cycle Y shown in FIG.
₁ of WB stage 41, in the DEC stage 42 of the code C _3, will perform a memory access at the same time. In this case, in the microprocessor 1, the internal memory 47
Data register r serving as a buffer for access to
₀ and r ₁ and two access paths to the internal memory 47 are provided, so that the code C ₁ and the code C ₃
If the bank of the internal memory 47 to be accessed is different between the WB stage 41 and the code C ₁ , as shown in FIG.
And it can be multiplexed and DEC stage 42 of the code C _3, pipeline processing is not disturbed (not stall).

An example of an access operation to the internal memory 47 according to the description of the program in the microprocessor 1 will be described below. When a two-operand operation instruction is used, a two-operand operation instruction having an operation code (OP) and two operands specifying a [source register] and a [destination register] is used as shown in FIG. Next, an access operation to the internal memory 47 when a program is described will be described.

For example, as shown in FIG. 7, when the data register r ₀ is specified as the source register in the two-operand operation instruction, the data is stored in the data register from the address stored in the DP register 30 on the internal memory 47. After reading to r ₀ , the data stored in the data register r ₀ and the data stored in the register r ₄ are added, and the resulting data is written to the register r ₄ .

For example, as shown in FIG. 8, when the data register r ₁ is specified as a destination register in a two-operand operation instruction, the data stored in the DP register 31 on the internal memory 47 is read from the address. the after reading the data register r _1, and data stored in the data register r _1, register r ₅
By adding the data stored in the write data of the addition result in the register r _1. Then, the internal memory 47
The DP register 31 to the address stored in the above, and writes the data stored in the data register r _1.

For example, as shown in FIG. 9, when the data register r ₀ is specified as a source address and the data register r ₁ is specified as a destination register in a two-operand operation instruction, After reading the data from the addresses stored in the DP registers 30 and 31 into the data registers r ₀ and r ₁ respectively, the data stored in the data register r ₀ and the data stored in the data register r ₁ are added. to write the data of the addition result in the register r _1. Then, the address stored in the DP register 31 in the internal memory 47, and writes the data stored in the data register r _1.

When the operation instructions shown in FIG. 8 are successively executed, in the pipeline processing of the microprocessor 1 shown in FIG. 4, as shown in FIG. ) Occurs. This corresponds to clock cycle T + shown in FIG.
In _No. 3, the write operation and the read operation on the data register r1 conflict with each other. That is, the code C ₁ is an operation command shown in FIG. 8, a clock cycle T + 1
When proceeding to DEC stage in the decoder 36 shown in FIG. 1, the locking internally registers r ₁ recognizes that the code C ₁ is a load / store instruction. The code C ₁ is in when it proceeds to the WB stage in clock cycle T + 3, the lock is released. That is, the read-modify-write to the internal memory 47 is locked until it is written back. When an instruction accesses the locked register, the access waits until the lock is released. Then, at clock cycle T + 3 writes the output of the ALU13 in the data register r _1, to determine the release of the lock, and updates the DP register 31. Then, at clock cycle T + 4, the data register r _{1 is} read from the internal memory 47 according to the code C _2.
Reads data, then repeats the same processing as the processing of the code C _1.

When a three- operand operation instruction is used , as shown in FIG.
An access operation to the internal memory 47 when a program is described using a three-operand operation instruction including three operands specifying [source registers] and [destination registers] will be described. In the microprocessor 1, for example, when executing the program shown in FIG. 21 in a conventional microprocessor, the program can be described as shown in FIG. In FIG. 12, the instruction “mov r ₀ ,
“r ₂ ” is the internal memory 4 stored in the data register r _0.
Data on 7 indicates that transferred to the register r _2. At this time, prior to execution of the instruction “mov r ₀ , r ₂ ”, the memory bank 4 is stored in the DP register 30 shown in FIG.
Read address of the data of interest within 5 are stored by the hardware, the data stored in the address have been transferred to the data register r ₀ through the bus 26. The data on the internal memory 47 stored in the data register r ₀ is transferred to the bus 24 and the multiplexer 1.
The data is transferred to the register r ₂ via the buses 6 and 12 and the bus 23.

“Add r ₂ , r ₉ , r ₃ ” indicates that the data stored in the register r ₂ and the data stored in the register r ₉ are added and stored in the register r ₃ . As a result, the data stored in the register r ₂ is output to the port AIN of the ALU 13, the data stored in the register r ₉ is output to the port BIN, and these additions are performed in the ALU 13. result via the bus 23 from the port AOUT, written into the register r ₃ of the general register module 11.

Further, "mov r ₃ , r ₁ " means to transfer the data stored in the register r ₃ to the data register r ₁ .

As a result, the data stored in the register r ₃ is transferred to the data register r ₁ via, for example, the bus 17, the multiplexer 12, the bus 23, the multiplexer 16 and the bus 25. Thereafter, the internal memory 4 stored in the DP register 31 is stored in hardware by the hardware.
The address of the 7, data stored in the data register r ₁ is automatically written via the bus 27.
Thus, in the microprocessor 1, instead of the load instruction “lw” and the store instruction “sw” shown in FIG. 21, an inter-register transfer instruction “mov” as shown in FIG.
Is executed.

The program shown in FIG. 12 can be described, for example, as shown in FIG. In the program shown in FIG. 13, the data register r ₀ and the register r ₉ are specified as the source register of the instruction “add”, and the data register r ₁ is specified as the destination address. However, in this case, it is necessary that the DP registers 30 and 31 point to addresses in different banks on the internal memory 47. FIG.
The program shown in FIG.
Executed in clock cycles.

In the microprocessor 1, when processing data stored at consecutive memory addresses on the internal memory 47, a program is described, for example, as shown in FIG. When the program shown in FIG. 14 is executed, the addresses stored in the DP registers 30 and 31 shown in FIG. 2 are sequentially updated by adding, for example, “+4”, thereby updating the data registers r ₀ and r _1. , Accesses are sequentially made to addresses at intervals of “+4” in the internal memory 47. In FIG.
“Add r ₀ , r ₉ , r ₁ ” is the data register r ₀
The stored data, by adding the data stored in the register r _9, show that for storing data of the addition result in the data register r ₁ is in. In the processing according to the program shown in FIG. 14, eight data on the internal memory 47 are processed. The program shown in FIG. 14 may be described using a loop.

In the microprocessor 1, for example, FIG.
DP of treatment, corresponding to the register r ₁₄ registers r ₁₄ of general register module 11 shown in the data register
By additionally providing a register, three paths for memory access can be provided. In this case, as shown in FIG. 15, by describing a program, the addition instruction “ad
Data registers r ₀ , r ₁₄ , and r ₁ can be specified in all three operands “d”.

As described above, according to the microprocessor 1, some of the general-purpose registers constituting the general-purpose register module 11 are partially replaced by the data registers r ₀ and r _1.
Therefore, it is not necessary to separately describe a memory read instruction and a memory write instruction for accessing the internal memory 47 in the program. In other words, the instruction set can be described as an operation performed between the data stored in the general-purpose registers, even when a memory access is required. That is, according to the microprocessor 1, the access to the internal memory 47 is treated as an extension of the access to the general-purpose register, and the data registers r ₀ and r ₁ can be used as a memory window from software.

In the microprocessor 1, if the address of the internal memory 47 to be accessed and the access order are determined in advance, the DP register 30,
31, the DP register 30,
By automatically updating the address stored in 31, there is no need to explicitly describe the procedure for memory access every time in a program.

Therefore, when sequentially accessing and processing a plurality of data stored at consecutive addresses in the memory address space of the internal memory 47, it is not necessary to specify the address of the data to be accessed each time, and the program is not required. Only the ALU operation instruction needs to be described. At this time, with respect to the data registers r _0, r _1, DP register 30,
By reading data from the internal memory 47 immediately after the 31 is automatically updated, it is possible to avoid waiting for the ALU 13 to complete the memory access every time the ALU operation instruction is executed. That is, at the time when the ALU 13 executes the ALU operation according to the program, the data can be already read from the internal memory 47 to the data registers r ₀ and r ₁ . As a result, in the arithmetic processing in the microprocessor 1, multiplexing of instructions can be efficiently realized, and for example, in pipeline processing, an ALU arithmetic instruction can be executed every clock cycle.
Further, the description of the program by the user can be simplified.

According to the microprocessor 1, 2
By providing the DP registers 30 and 31 and executing the ALU operation instruction directly on the data on the internal memory 47, for example, after reading and processing the data on the internal memory 47, The rewriting process can be described by one instruction. Moreover, in this instruction, if the bank of data read from the internal memory 47 is different from the bank of data written to the internal memory 47, the instruction can be executed within one clock cycle. Note that DP register 3
If both 0 and 31 can specify all the addresses of the internal memory 47, the instruction is executed within one clock cycle if the address of the data read from the internal memory 47 is different from the address of the data written to the internal memory 47. it can. For example, in a program, arithmetic processing involving memory access can be described by, for example, one instruction as shown in FIG. 13 and executed within one clock cycle.

Further, the microprocessor 1, when performing write back data to the internal memory 47 instructions (data transfer instruction specifying the data register r ₀ or r ₁ as the destination register) successively, DP
The automatic reading function of the registers 30 and 31 is stopped, and unnecessary memory reading can be eliminated. As a result, memory writes can be executed continuously, and multiplexing of instructions can be realized.

Further, in the microprocessor 1, the memory configuration using the data registers r ₀ and r ₁ and the DP registers 30 and 31 eliminates the need for the MEM stage in the conventional five-stage pipeline structure shown in FIG. As shown in FIG. 4, a four-stage pipeline structure can be adopted. That is, since the write operation is performed on the internal memory 47 using the data registers r ₀ and r ₁ , the write operation on the internal memory 47 can be performed by the register write operation performed in the WB stage. Therefore, it is not necessary to provide a memory access processing stage independently in the pipeline processing. As a result, in the microprocessor 1, the control circuit of the entire processor is simplified, and it is possible to flexibly cope with exception processing including an external interrupt.

Second Embodiment The microprocessor according to the second embodiment is characterized in that the number of banks of the internal memory, the number of data registers and DP registers, and that a multiplexer 82 is provided instead of the multiplexers 12 and 16 shown in FIG. Except, basically,
It has the same configuration as the microprocessor 1 of the first embodiment described above. FIG. 16 is a configuration diagram around the internal memory 87 of the microprocessor 81 of the present embodiment. FIG.
As shown in 6, the microprocessor 81 includes an internal memory 87, DP register 91, 92 and 93, the data register _{r 0, r 1 -R, r} 1 -W, a multiplexer 82 and bus 101-106.

The microprocessor 81 includes an ALU 13, a program counter 34, an instruction page memory 35, a decoder 36, and buses 17, 18, 19, 20, and 2, similarly to the microprocessor 1 shown in FIG.
3 is provided. In the microprocessor 81,
Instead of the register r ₁ shown in FIG. 1, the register r ₁ -R
And a register r ₁ -W. That is, the microprocessor 81 has registers r _{2 to} r _{15 in} addition to the data registers r ₀ , r ₁ -R, and r ₁ -W shown in FIG.
Is provided. The microprocessor 81 logically handles the physical data registers r ₁ -R and the data registers r ₁ -W as a single data register r _{1 in} the description of the program.

In the microprocessor 81, the memory bank 11 of the internal memory 87 stored in the DP register 91
Data is read from the address in ₀ and stored in the data register r0. The data register r ₁ -R is
A data read operation only from the memory bank 111 of internal memory 87, when the address of the logical data register r ₁ is designated in the second operand arithmetic instructions written in the program as the destination register, DP register 92 The data read from the address in the memory bank 111 stored in the memory cell is stored. Further, the data register r ₁ -W stores the internal memory 8
7 is a data write operation only with respect to the memory bank 112, if specified address of a logical data register r ₁ as the destination register in the two-operand arithmetic instructions written in the program, the data register r ₁ -W is stored in D
Write to the address in the memory bank 112 stored in the P register 93. Note that the logical data register r ₁
In addition to specifying the logical address directly,
For example, a logical address may be indirectly specified via a logical register name.

Hereinafter, the operation of the microprocessor 81 will be described. In the microprocessor 81, for example,
A two-operand operation instruction having the format shown in FIG. 6 is executed. In the microprocessor 81, for example, FIG.
As shown in FIG. 7, when the data register r ₁ executes the instruction specified by the destination address, first, the address in the memory bank 111 in which the data to be added is stored is written to the DP register 92, The data to be added is read out to the data register r ₁ -R via the bus 102 by hardware. Next, the ALU13 shown in FIG. 1, the data stored in the register r _5, performs addition operation between data stored in the data register r ₁ -R, data register data of the addition result through the bus 106 Store it in r ₁ -W ₀ .
The memory bank 112 to which the data of the addition result is written back
Is written into the DP register 93. As a result, the data of the addition result stored in the data register r ₁ -W ₀ is written back to the memory bank 112 via the bus 103 by hardware.

Hereinafter, in the microprocessor 81,
A case where data stored at consecutive memory addresses on the internal memory 87 is processed will be described. In the microprocessor 81, for example, when the program shown in FIG. 18 is executed by the four-stage pipeline processing shown in FIG.
The result is as shown in FIG. Code C shown in FIG.
Each code ₁ -C _6, in the pipeline processing shown in FIG. 19 (A), the instruction in the IF stage "the add r _0,
Fetching r ₁ "is performed, in DEC stage, one of the addition-target data from the stored address on the memory bank 110 has been read into the data register r ₀ in the DP register 91, the data register r ₀ of ALU13 Output to port AIN. At the same time, the DP register 92
Port from the stored address on the memory bank 111 of the other read the data register r ₁ -R addition target data from the data register r ₁ -R of ALU13 to B
Output to IN. Next, at the ALU stage, ALU1
3, the addition using both the addition target data is performed, and the addition result of the ALU 13 is output to the port A in the WB stage.
OUT is written to the data register r ₁ -W. Thereafter, the memory bank 11 stored in the DP register 93
The data stored in the data register r ₁ -W is written back to the address on 2.

At this time, as shown in FIG. 19A, the IF stage of the code C ₁ is performed in the clock cycle T. As shown in FIG. 19B, the clock cycle T
+ In 1 to T + 6, a memory read operation for the data registers r ₀ by the code C ₁ -C ₆ (decode stage) is carried out in order. Further, as shown in FIG. 19C, in clock cycles T + ₁ to T + 6, the codes C ₁ to C _{1 are} output.
The memory read operation (decode stage) for the data register r ₁ -R by C ₆ is performed in order. Further, as shown in FIG. 19D, the clock cycle T +
From 3 to T + 8, a memory write operation to the data register r ₁ -W by the codes C _{1 to} C ₆ (WB stage)
Are performed in order. That is, in the microprocessor 81, as described above, the data registers r ₁ -R, r _1-
By providing Wr ₀ , a memory read operation and a memory write operation for data register r ₁ can be performed simultaneously. As a result, the codes C _{1 to} C ₆ shown in FIG.
Can be executed in one clock cycle.

[0055] As described above, according to the microprocessor 81, a case where the specified logical data register r ₁ to the destination address performed continuously repeated 2 operand operation instruction for performing the read-modify-write Also, each operation instruction can be executed in one clock cycle. According to the microprocessor 81,
By using a two-operand operation instruction, three different data on the internal memory 87 are accessed in the same clock cycle, and an operation substantially equivalent to a three-operand operation can be realized.

The present invention is not limited to the above embodiment. For example, in the above-described embodiment, the case where two general-purpose registers are used as the data registers r ₀ and r _{1 in} the general-purpose register module 11 has been described as an example. is there. The method of using the data registers r ₀ and r ₁ is not only used as an interface with the internal memory 47, but also for example, when a FIFO is used for communication between microprocessors in a parallel processor equipped with a plurality of microprocessors. (First In First Out) It may be used as a memory. Further, the data registers r ₀ and r ₁ may be used as a local memory or a stack memory.

In the microprocessor 1, as shown in FIG.
The functions of the multiplexer 16 may be incorporated in the multiplexer 12.

Further, in the microprocessor 1, as shown in FIG. 2, the internal memory 47 is divided into two banks, but the internal memory 47 is divided into three or more banks, or the banks are not divided. It may be configured.

In the microprocessor 1, as shown in FIG. 1, the general-purpose register module 11 is provided with data registers r ₀ and r ₁ as a part of a plurality of general-purpose registers. May be provided with data registers r ₀ and r ₁ so as to be handled separately from general-purpose registers.

In the microprocessor 81 having the memory structure shown in FIG. 16, three FIFO memories are provided instead of the internal memory 87, and the data register r _1-
A configuration may be adopted in which an input FIFO memory is connected to R and an output FIFO memory is connected to the data register r ₁ -W.

[0061]

As described above, according to the arithmetic processing unit of the present invention, the first data register and the second data register are designated as the destination register using the same logical address, and the read modification is performed. When a two-operand operation instruction instructing to perform writing is executed, three different data in the internal memory are accessed in the same clock cycle, and an operation substantially equivalent to the three-operand operation can be realized. Further, according to the arithmetic processing device and the method thereof of the present invention, even when the above-described two-operand arithmetic instruction is repeatedly and continuously performed, each arithmetic instruction can be efficiently executed using pipeline processing. Further, according to the arithmetic processing device of the present invention, by realizing access to the internal memory using the data register, access to the internal memory can be handled in the same manner as access to the register. it can. As a result, the burden on the user when creating a program can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a microprocessor according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining a data register, a DP register, and an internal memory of the microprocessor shown in FIG. 1;

FIG. 3 is a diagram for explaining a configuration of a general-purpose register module shown in FIG. 1;

FIG. 4 is a diagram for explaining a four-stage pipeline process of the microprocessor shown in FIG. 1;

FIG. 5 is a diagram for explaining the pipeline process of the microprocessor shown in FIG. 1;

FIG. 6 is a view for explaining a format of a two-operand operation instruction used in the microprocessor shown in FIG. 1;

FIG. 7 is a diagram for explaining an operation instruction when a data register is specified as a source register in the operation instruction shown in FIG. 6;

FIG. 8 is a diagram for explaining an operation instruction when a data register is designated as a destination register in the operation instruction shown in FIG. 6;

FIG. 9 is a diagram for explaining an operation instruction when a data register is designated as both a source register and a destination register in the operation instruction shown in FIG. 6;

FIG. 10 is a diagram for explaining a stall in pipeline processing that occurs when the operation instructions shown in FIG. 8 are continuously performed.

FIG. 11 is a diagram for explaining a format of a three-operand operation instruction used in the microprocessor shown in FIG. 1;

12 is a diagram for describing a program in the microprocessor shown in FIG. 1 that describes processing similar to the program shown in FIG. 21 in a conventional microprocessor.

13 is a view for explaining a program in which the same processing as the program shown in FIG. 12 is described in the microprocessor shown in FIG. 1 by designating a data register as a source register and a destination address; It is.

FIG. 14 is a diagram for explaining a program showing a process of processing data stored at consecutive memory addresses on an internal memory in the microprocessor shown in FIG. 1;

FIG. 15 is a diagram for explaining a program including an instruction in which a data register is specified in all three operands of an addition instruction in the microprocessor shown in FIG. FIG.

FIG. 16 is a configuration diagram around an internal memory 87 of a microprocessor according to a second embodiment of the present invention.

FIG. 17 shows two-operand operation instructions.
FIG. 4 is a diagram for describing an example in which a data register is specified as a destination address.

FIG. 18 is a diagram for explaining a program for processing data stored in continuous memory addresses on an internal memory in the microprocessor according to the second embodiment of the present invention.

FIG. 19 is a diagram for explaining a case where the program shown in FIG. 18 is executed by the four-stage pipeline processing shown in FIG. 4;

FIG. 20 is a diagram for explaining five-stage pipeline processing of a conventional microprocessor.

FIG. 21 is a diagram for explaining a program for processing in which data on a memory is subjected to an ALU operation in the five-stage pipeline processing shown in FIG. 20;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Microprocessor, 11 ... General-purpose register module, 12, 16 ... Multiplexer, 13 ... ALU, 2
1, 22, 23, 24, 25, 26, 27 ... bus 3,
0, 31: DP register, 35: instruction page memory, 36: decoder, 45, 46: bank, 4
7 internal memory, 50 external main memory 18

Claims (13)

[Claims] An internal memory for storing data to be operated on; a first data pointer register and a second data pointer register for storing addresses on the internal memory; and a first data pointer register for storing the data. A first data register for storing data read from an address on the internal memory, and a second data register for writing storage data to an address on the internal memory stored in the second data pointer register Calculating means for performing an operation based on a decoding result; and designating the first data register and the second data register as a destination register using the same logical address, and performing a read-modify-write. When the designated two-operand operation instruction is decoded, the operation means Serial first performs arithmetic processing using the data stored in the data register, the result of the arithmetic processing, the arithmetic processing unit and a decoding means for controlling to write to the second data register. 2. The internal memory according to claim 1, wherein said internal memory has at least a first bank for reading data from said first data register and a second bank for writing data from said second data register. Arithmetic processing unit. 3. A third data pointer register for storing an address on the internal memory, and a third data for storing data read from the address on the internal memory stored in the third data pointer register. The arithmetic processing device according to claim 1, further comprising a register. 4. A third data pointer register for storing an address on the internal memory, and a third data for storing data read from the address on the internal memory stored in the third data pointer register. The arithmetic processing device according to claim 2, further comprising a register, wherein the internal memory further includes a third bank for reading data to the third data register. 5. The first data pointer register and the second data pointer register, when there is a predetermined pattern in access to the internal memory, respectively store addresses stored in accordance with the pattern. The arithmetic processing device according to claim 1, wherein the arithmetic processing device automatically updates the data. 6. The first data register and the second data register.
The data register reads and stores data from the updated address in the internal memory immediately after the addresses stored in the first data pointer register and the second data pointer register are updated, respectively. 2. The arithmetic processing device according to 1. 7. The first data register and the second data register.
When the data write to the internal memory is continuously and repeatedly performed, the data register immediately after the address stored in the first data pointer register and the address stored in the second data pointer register are updated, respectively. The arithmetic processing device according to claim 1, wherein a function of reading data from the updated address of the memory is stopped. 8. The first data register and the second data register.
2. The switch according to claim 1, further comprising: a switching unit that switches a connection between the data register, the plurality of general-purpose registers other than the first data register and the second data register, and the arithmetic unit. Arithmetic processing unit. 9. The first data register and the second data register.
2. The connection form between the data register and the calculation means is equivalent to the connection form between the plurality of general-purpose registers other than the first data register and the second data register and the calculation means. An arithmetic processing unit according to any one of the preceding claims. 10. A two-operand operation instruction designating the first data register and the second data register as a destination register using the same logical address, and instructing to perform a read-modify-write operation. An instruction fetch process for reading an instruction from an address on an instruction memory indicated by a program counter; decoding the fetched instruction; and transferring data from the first data register and the third data register to the arithmetic means. 5. The arithmetic operation according to claim 4, wherein a four-stage pipeline process is performed in which a decoding process for performing the operation, a calculation process by the arithmetic unit, and a write-back process for writing an operation result of the arithmetic process to the second data register are performed. Processing equipment. 11. The arithmetic processing unit according to claim 10, wherein a predetermined two-operand arithmetic instruction is repeatedly and continuously executed. 12. A process of reading data from an address on the internal memory stored in the first data pointer register and storing the data in the first data register, and data written in the second data register. Back to the address on the internal memory stored in the second data pointer register, and reading the data from the address on the internal memory stored in the third data pointer register to read the third data register The arithmetic processing device according to claim 10, wherein the processing to be stored in the arithmetic processing unit is performed in parallel with the four-stage pipeline processing. 13. Specifying the first data register and the second data register as a destination register using the same logical address, specifying the third data register as a source register, and performing a read-modify-write. An instruction fetch process for reading an instruction from an address on an instruction memory indicated by a program counter, decoding the fetched instruction, and executing the first data register and the third Performing a four-stage pipeline process that multiplexes a decode process of transferring data from a data register to the arithmetic unit, an arithmetic process, and a write-back process of writing an arithmetic result of the arithmetic process to the second data register; The address on the internal memory stored in the first data pointer register Reading the data from the memory and storing the data in the first data register; and writing back the data written in the second data register to the address on the internal memory stored in the second data pointer register. An arithmetic processing method for performing, in parallel with the four-stage pipeline processing, processing of reading data from an address on the internal memory stored in a third data pointer register and storing the data in the third data register .