JPH1165524A - Method for driving plasma display panel and device thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To expand erasing margin by performing a minute change type erasure for erasing a wall charge stored by impressing plural pulse group, being changed very slightly, on an electrode during a resetting period. SOLUTION: Capacitors C4, C5 for supplying electric power are a second power source, while a power source Vs is a first power source, switching elements SW17 and SW18 stop the power supply from the power source Vs at the time of a resetting period, change the power supply to the capacitors C4, C5 and are used for a stepwise erasing method for erasing wall eletric charges. A reset period begings succeeding to a sustaining discharge period, by turning off the switching elements SW17 and SW18 in first and second row electrode drive drivers 21, 22, and voltages are supplied to the respective row electrodes. The light-emitting intensity is weakened, while the stored wall charge amount is decreased, accompanied by the attenuation of discharge voltage from the capacitors C4, C5 so that the intensiey is erased gradually.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving method and a driving apparatus for an AC plasma display panel (hereinafter referred to as AC-PDP).

[0002]

2. Description of the Related Art As is well known, a plasma display panel has a structure in which minute discharge cells (also called display cells or pixels) are formed between two glass plates, and has been variously studied as a thin television or display monitor. An AC plasma display panel (AC-PDP) having a memory function is known as one of them. Surface discharge type AC-PDP as one of AC-PDP
There is.

FIG. 10 is a perspective view showing the structure of a surface discharge type AC-PDP.
P is described in, for example, JP-A-7-140922 and JP-A-7-140922.
287548. In FIG.
1 is a surface discharge type plasma display panel, 2 is a front glass substrate which is a display surface, 3 is a rear glass substrate which is opposed to the front glass substrate 2 with a discharge space interposed therebetween, and 4 and 5 are on the front glass substrate 2 A first row electrode X1 to Xn and a second row electrode Y1 to Yn formed to form a pair;
6 is a dielectric layer coated on these row electrodes 4 and 5;
Is MgO formed on the dielectric layer 6 by a method such as vapor deposition.
(Magnesium oxide).

[0004] Reference numeral 8 denotes a row electrode 4 on the rear glass substrate 3.
Column electrodes W1 to Wm formed so as to be orthogonal to
Reference numeral 9 denotes a phosphor layer formed on the column electrode 8;
The phosphor layers 9 emitting red, green, and blue light are provided in stripes in order. Reference numeral 10 denotes a partition formed between the column electrodes 8. The partition 10 has a role of separating the discharge cells and also a role of a column for preventing the plasma display panel from being crushed by the atmospheric pressure. A discharge gas such as a Ne—Xe mixed gas or a He—Xe mixed gas is sealed in the space between the glass substrates at a pressure equal to or lower than the atmospheric pressure, and a pair of row electrodes 4 and 5 and a pair of column electrodes 8 orthogonal thereto are provided. The discharge cell at the intersection of becomes a pixel. Hereinafter, the first row electrode 4
May be called an X electrode, the second row electrode 5 may be called a Y electrode, and the column electrode 8 may be called a W electrode.

Next, the operation will be described. In the AC-PDP shown in FIG. 10, a first row electrode 4 and a second row electrode 5 are covered with a dielectric layer 6, and at the time of display, a voltage pulse is alternately applied between the two row electrodes, and a half pulse is applied. A discharge whose polarity is inverted in each cycle is caused to cause the display cell to emit light. In the color display, the phosphor layer 9 formed in each cell is excited by ultraviolet light from discharge to emit light. Since the first row electrode 4 and the second row electrode 5 that perform discharge for display are covered with the dielectric layer 6, once a discharge occurs between the electrodes of each cell, the first row electrode 4 and the second row electrode 5 are generated in the discharge space. The electrons and ions move in the direction of the applied voltage and accumulate on the dielectric layer 6. The charges such as electrons and ions accumulated on the dielectric layer 6 are called wall charges. The electric field formed by the wall charges acts in a direction to weaken the applied electric field, and thus the discharge is rapidly extinguished with the formation of the wall charges.

When an electric field whose polarity is inverted to that of the previous discharge is applied after the discharge is extinguished, the electric field formed by the wall charges overlaps with the applied electric field. It becomes possible. Thereafter, the discharge can be maintained by inverting the low voltage every half cycle. Such a function is a function originally provided in the AC-PDP, and this function is called a memory function. A discharge sustained at a low applied voltage using this memory function is called a sustain discharge, and a voltage pulse applied to the first row electrode 4 and the second row electrode 5 every half cycle is called a sustain discharge pulse. This sustain discharge is continued as long as the sustain discharge pulse is applied, until the wall charge is extinguished. Eliminating the wall charges is called erasing, and forming the wall charges on the dielectric layer 6 first is called writing.

Writing is performed for an arbitrary cell on the screen of the AC-PDP, and thereafter, by performing a sustain discharge, characters, figures, images, etc. can be displayed. In addition, writing, sustaining discharge, and erasing can be performed at high speed. By doing so, a moving image can be displayed. In the case of performing a gray scale display, it can be performed by controlling the time for emitting light by the sustain discharge.

Next, a method of driving the AC-PDP will be described. FIG. 11 is a timing chart showing voltage waveforms in one subfield of a conventional plasma display panel driving method disclosed in, for example, JP-A-7-160218. One subfield includes a reset period for erasing a display history, an address period for selecting a cell to be displayed, and a sustain discharge period for obtaining a luminance that is to be discharged a specified number of times. The voltage waveform shown in FIG. 11 is a voltage waveform applied to the column electrode Wj, the first row electrode X, and the second row electrodes Y1, Y2, and Yn in order from the top.

First, in the reset period, the entire-surface write pulse Pxp is applied to the first row electrode X commonly connected to all the screens at time a in FIG. This full write pulse Pxp may be called a priming pulse. Hereinafter, unless otherwise specified, it is referred to as a priming pulse. The priming pulse Pxp is set to be equal to or higher than the discharge starting voltage between the first row electrode X and the second row electrode Y, and
Since the voltage is applied for a sufficiently long time of about μsec, all cells discharge and emit light irrespective of light emission / non-light emission in the previous subfield. At this time, the priming assist pulse Pwp is also applied to the column electrode W, which is applied to the first row electrode X.
In order to make it difficult for a discharge to occur between
This is for reducing the potential difference between the W electrodes, and is set to a value that is approximately の of the voltage between the X and Y electrodes. When the priming pulse Pxp is applied, a strong discharge occurs between the X and Y electrodes, and a large amount of wall charges are accumulated between the X and Y electrodes, and the discharge ends.

Next, in the figure, at time b, the priming pulse Pxp falls, and when the applied voltage to the first row electrode X and the second row electrode Y is eliminated, the priming pulse is applied between the X and Y electrodes. An electric field due to the wall charges accumulated at Pxp remains. Since this electric field is large and the discharge can be started again by itself, the discharge occurs again between the X and Y electrodes.
However, since there is no externally applied voltage, the electrons and ions generated by this discharge are not attracted to the row electrodes X and Y,
It is neutralized and disappears.

As described above, all cells are written regardless of the presence / absence of the wall charge in the previous subfield,
Then, by erasing, the wall charges of the cells on the entire screen can be set to the “absent” state, and the reset is performed. Even when there is no externally applied voltage, the discharge is performed only by the accumulated wall charges, and the discharge in which the wall charges are erased is called a self-erasing discharge.

At the end of the reset period and at time c in the drawing, almost no wall charges remain on the first row electrode 4 and the second row electrode 5. On the other hand, a small amount of charged particles generated by the discharge due to the previous entire writing pulse Pxp remains in the discharge cell. The charged particles are for ensuring discharge in the next writing, and serve as a seed for the writing discharge. For this reason, the whole-surface write pulse Pxp is called a priming pulse, and therefore, this method, which combines the priming effect and the erasing effect with one pulse, is considerably required for stable operation of the plasma display panel. This is a good method. In addition, since erasing by the self-erasing discharge can be performed only by lowering a high voltage pulse, it is a good erasing method for stably operating the AC-PDP.

However, the priming pulse P
Since xp emits light in all cells irrespective of the display history, there is also a problem that the contrast is lowered. Since the priming effect has a time constant of several msec, the priming pulse Pxp is applied once to several subfields, and the erasing pulse having a narrow pulse width or a low voltage value is applied to the remaining subfields to apply the priming pulse Pxp to the previous subfield. Only the cells lit in the field may be discharged and erased. As the erasing method at this time, narrow width erasing, wide erasing, and the like are well known. Since these principles are well known to those skilled in the art of AC-PDP, they will not be described in detail here.
(Kenichi Ohwaki et al .: Kyoritsu Shuppan, 1983).

The narrow erase pulse is a pulse having the same voltage value as the sustain discharge pulse and a pulse width of about 0.5 μsec. When this pulse is applied, the pulse is interrupted before the progression of the discharge, that is, before the formation of the wall charge of the opposite polarity, so that the wall charge is erased. This erasing method requires a pulse with a narrow pulse width, while having a wide erasing margin, and is sensitive to the high speed of the drive circuit and the blunting of the voltage pulse due to the capacitance and resistance components of the plasma display panel. As the display panel becomes larger, the dullness of the voltage pulse becomes larger, making it difficult to realize.

On the other hand, the thick erase pulse is a pulse having a pulse width similar to that of the sustain discharge pulse and a low voltage value. This pulse causes a weak discharge that is insufficient to form wall charges of the opposite polarity and erases the wall charges. In this method, since the erase margin is narrow, in a plasma display panel having a very large number of discharge cells, it is rare for the erase margin to overlap in all the discharge cells, and it is difficult to operate stably only by this erase method. Therefore, both the narrow erase pulse and the wide erase pulse are often applied.

Further, for example, Japanese Patent Laid-Open No.
As disclosed in Japanese Patent Application Laid-Open No. 315196, a method of coping with cell variations by changing the voltage value with pulses of the same polarity is also known. Since these pulse groups have the same polarity, once they are discharged, they are not discharged by the subsequent erase pulses.
Therefore, although the number of pulses for erasing is large, each cell has a characteristic of only one discharge.

Returning to FIG. 11, when the address period comes,
A negative scan pulse Scyp is sequentially applied to the independent second row electrodes Y1 to Yn, and scanning is performed. On the other hand, a positive address pulse A according to the image data content is applied to the column electrode W.
wp is applied. By the scan pulse Scyp applied to the second row electrode Y and the address pulse Awp applied to the column electrode W, any cell on the screen can be selected in a matrix. Since the total voltage value of the scan pulse Scyp and the address pulse Awp is set to be equal to or higher than the discharge start voltage between the Y and W electrodes of the cell, the scan pulse Sc
A cell to which yp and the address pulse Awp are simultaneously applied discharges between the Y-W electrodes.

During the address period, the common first row electrode Xi is maintained at a positive voltage value. Although this voltage value does not discharge between the X and Y electrodes even when summed with the voltage value of the scan pulse Scyp, when a discharge occurs between the Y and W electrodes,
Triggered by this discharge, the voltage value is set such that a discharge occurs simultaneously between the X and Y electrodes. The discharge between the X and Y electrodes that is triggered by the discharge between the Y and W electrodes may be referred to as a write sustain discharge. By this write sustaining discharge, wall charges are accumulated on the first and second row electrodes.

After the scanning of the entire screen is completed, the sustain discharge pulse Sp is applied to the entire screen all at once, and the sustain discharge is performed only in the cells addressed during the address period and storing the wall charges. Then, the next subfield starts again, and the priming pulse Pxp is applied to all the cells in the reset period to perform the reset. As described above, the driving method for separating the address period and the sustain discharge period over the entire screen of the AC-PDP is called “address / sustain separation method”, and the current AC-P
DP is a known technique that has become common.

Next, a driving apparatus for realizing this driving method will be described. FIG. 13 shows a simplified configuration of a driving device for a plasma display panel described in JP-A-7-160218. In FIG.
The first row electrode Xi of any display cell 11 in the plasma display panel 1 is connected to the first row electrode drive driver 2.
1, the second row electrode Yi is connected to the second row electrode drive driver 22, and the column electrode Wj as the third electrode
Are connected to the column electrode drive driver 23. And
Each of these electrode driving drivers has a reset period, an address period, and a sustain discharge period in each subfield obtained by dividing one field for displaying an image into a plurality of subfields, and outputs a control output corresponding to each period. It is controlled by the control circuit 24 which sends out to the electrode drive driver.

The first row electrode drive driver 21 includes power supplies Vs, Vw, Va, diodes D11 to D14, a capacitor C3, and switch elements SW12 to SW16. The second row electrode driving driver 22 includes a Y common driver 22a and a Yi driving circuit 22bi, and includes power supplies -Vsc, Vs, Vs, -Vy, diodes D5 to D1.
0, switch elements SW5 to SW11. Further, the column electrode drive driver 23 includes a voltage step-up circuit 23a and a Wj drive circuit 23bj common to each column, and includes a power supply Va, diodes D1 to D4, a resistor R1, a capacitor C1, and switch elements SW1 to SW4. I have. These switch elements are turned on / off by the control circuit 24.
Controlled off.

During the reset period, the priming pulse Pxp is supplied to the first row electrode Xi by turning on the switch elements SW15 and SW12, and the priming pulse Pxp is turned off by turning on the switch element SW16. .
Similarly, the switch element SW14 is turned on during the address period, and the switch element SW15 is turned off during the sustain discharge period.
N, a voltage is supplied.
W16 is turned on to make the pulse fall.

On the second row electrode Yi side, the switch elements SW11, SW8, and SW6 are turned off during the sustain discharge period.
By applying N, the power supply Vs is supplied, and the pulses fall when the switch elements SW10 and SW5 are turned on. During the address period, switch elements SW9, SW
7 is turned on, and the switch elements SW10 and SW11 are selectively turned on and off, whereby the scan pulse Sc
yp is created. Further, these potentials turn off the switching elements SW7 and SW9, and switch the switching elements SW5 and SW9.
8 is turned on to return to the GND level.

Further, on the column electrode Wj side, in the address period, the switch element SW3 is turned on and the switch element SW4 is turned off, so that the address pulse Awp of the voltage value Va is applied to the column electrode Wj. In the reset period, the voltage value Va + Vas is generated by turning off the switch element SW2 and turning on the switch element SW1, and the priming auxiliary pulse Pwp is supplied to the column electrode Wj by turning on and off the switch elements SW3 and SW4.

[0025]

By using the above-described driving device, a priming pulse Pxp is applied once every several subfields to improve dark contrast, and the wide or narrow width is applied to the remaining subfields. When driving is performed by using the erasing method, there is a problem that erasing defects increase with an increase in screen size and definition. This is an essential problem in that, when the screen is large and the number of cells is large, the variation of the operating point in each cell is large, and it cannot be absorbed by the pulse width of the narrow pulse or the voltage value of the wide pulse.

The variation in the operating point works in a direction to increase the voltage of the priming pulse. If the erasing after full lighting was performed by using another erasing method without using the self-erasing discharge in order to lower the voltage value of the priming pulse, erasing failures would occur frequently as in the previous problem, causing display problems. Would.

The present invention has been made in order to solve the above-mentioned problems, and an erasing margin can be expanded by performing erasing capable of absorbing a discharge variation of a display cell accompanying a large screen and high definition. It is an object to obtain a driving method and a driving device of a plasma display panel.

[0028]

In order to achieve the above object, a method of driving a plasma display panel according to the present invention comprises the steps of: forming a first substrate covered with a dielectric layer on a first substrate; A plurality of displays formed in a matrix by arranging third electrodes intersecting the first and second electrodes on a second substrate arranged in parallel with the first substrate. A method for driving a plasma display including cells, comprising: a reset period for erasing wall charges accumulated on the dielectric layer in each subfield obtained by dividing one field for image display into a plurality of fields; The first electrode or the second electrode corresponding to any display cell
An address period in which a discharge is caused between the first electrode and the third electrode to accumulate wall charges on the dielectric layer;
And a sustain discharge period in which a sustain discharge is performed between the second electrode and the second electrode by utilizing a wall charge accumulated on the dielectric layer. The method is characterized in that a minute change type erasure is performed in which a plurality of minutely changing pulse groups are applied to one of the first electrode and the second electrode to erase accumulated wall charges.

Further, the above-mentioned minute change type erasing is characterized in that it is step erasing in which the voltage value of a pulse is changed.

Further, the frequency of the pulse at the time of the step erasing is different from the frequency of the sustain discharge pulse applied to the first electrode and the second electrode during the sustain discharge period. .

Further, the above-mentioned minute change type erase is characterized in that it is a pulse width change type erase in which the pulse width is minutely changed.

Further, the above-mentioned minute change type erasing is characterized in that it is a rising speed changing type erasing in which the rising speed of a pulse is minutely changed.

In addition, the micro-change type erasure is characterized in that it is used for erasing a priming discharge by a priming pulse generated at an arbitrary timing irrespective of display information in order to reliably generate a discharge.

In addition, the above-mentioned small change erasure is used for erasing wall charges during a sustain discharge period of a subfield having large display luminance information, and a single pulse is used for erasing wall charges during a sustain discharge period of a subfield having small display luminance information. It is characterized by using erasure.

Further, the single pulse erasing is characterized by erasing by a high voltage full lighting pulse utilizing self-erasing discharge.

After the micro-change type erasure, the first
And an auxiliary pulse for adjusting the polarity of the wall charges remaining on the second electrode and the second electrode.

In the driving apparatus for a plasma display panel according to the present invention, first and second electrodes covered with a dielectric layer are provided side by side on a first substrate, and the first and second electrodes are opposed to the first substrate. On the second substrate to be arranged, the first and second
A plasma display having a plurality of display cells formed in a matrix by arranging a third electrode that intersects with a plurality of sub-electrodes, and sub-fields obtained by dividing one field for displaying an image on the plasma display into a plurality of sub-cells In the field,
A reset period for erasing wall charges accumulated on the dielectric layer, and a discharge between the first electrode or the second electrode and the third electrode corresponding to an arbitrary display cell selected in a matrix. And an address period during which wall charges are accumulated on the dielectric layer, and a sustain discharge is performed between the first electrode and the second electrode using the wall charges accumulated on the dielectric layer. A control circuit that has a discharge period and sends a control output corresponding to each period to each electrode driver, and a first power supply provided corresponding to the first to third electrodes, respectively. And a first to a third electrode driving driver for outputting a pulse corresponding to a control output from the control circuit to each electrode, and wherein any one of the first electrode driving driver and the second electrode driving driver is provided. Alternatively, the first power supply A second power supply capacitor arranged in parallel, and a switch element provided between the first power supply capacitor and the second power supply capacitor for switching the power supply. 2 is provided.

The first power supply applies a sustain discharge pulse to the first electrode and the second electrode during the sustain discharge period, and the second power supply supplies
It is characterized by being charged by a first power supply.

Further, the switch element stops the voltage supply from the first power supply during the reset period, switches the power supply to the second power supply capacitor side, and switches the second power supply capacitor. And a step erasing method for erasing wall charges by applying a pulse whose voltage is attenuated.

[0040]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. FIG. 1 is a partial cross-sectional view of a cell of a surface discharge type plasma display panel for explaining a display cell in particular of a plasma display panel according to Embodiment 1 of the present invention. As shown in FIG. 1, the cells of the surface discharge type plasma display panel 1 are configured as follows. That is, the front glass substrate 2 serving as a display surface and the rear glass substrate 3 are arranged to face each other with a discharge space interposed therebetween, and the first row electrode 4 (X
i) and the second row electrode 5 (Yi) are arranged. A dielectric layer 6 is provided on the row electrodes 4 and 5, and a Mg layer is further provided thereon.
O7 is formed.

A column electrode 8 (Wj) is provided on the rear glass substrate 3 facing the front glass substrate 2 so as to be orthogonal to the row electrodes 4 and 5 (Xi, Yi). The body layer 9 is formed. Partition walls 10 for separating the discharge cells are formed between the column electrodes 8, and the discharge space between the front glass substrate 2 and the rear glass substrate 3 of each discharge cell separated by the partition walls 10 is Ne−. A discharge gas such as a Xe mixed gas or a He-Xe mixed gas is sealed.

FIG. 2 is a schematic structural view showing a driving device of the plasma display panel. 2, the same parts as those of the conventional example shown in FIG. 13 are denoted by the same reference numerals, and the description thereof will be omitted. As a new symbol, SW18 and C5 are a switch element and a power supply capacitor provided on the first row electrode drive driver 21 side, and the power supply capacitor C5 is parallel to the power supply Vs via the switch element SW18. Has been established. SW17 and C4 are a switch element and a power supply capacitor provided on the second row electrode drive driver 22 side. The power supply capacitor C4 is provided in parallel with the power supply Vs via the switch element SW17. The power supply capacitors C4 and C5 use the power supply Vs as the first power supply and the second power supply. The switch elements SW17 and SW18 supply power from the power supply Vs during the reset period. Stopping, switching the power supply to the capacitors C4 and C5 side, discharging while attenuating the charge voltage value charged to the capacitors C4 and C5 during the sustain discharge period, supplying an erase pulse, and erasing the wall charge. Used for the erasing method.

FIG. 3 is a timing chart of voltage waveforms showing a method of driving the plasma display panel according to the first embodiment of the present invention. In FIG. 3, the voltage waveform is a voltage waveform applied to the column electrode Wj, the first row electrode Xi, and the second row electrode Yi in order from the top. Pxp is a priming pulse applied to the first row electrode Xi for performing priming and overall erasing, Pwp is a priming auxiliary pulse applied to the column electrode Wj at the same timing as the priming pulse Pxp, and Exp is power supply capacitors C4 and C5. , An erase pulse group applied while attenuating the voltage, Sp is a sustain discharge pulse supplied from the power supply Vs, Scyp is a scan pulse for scanning, and Awp is an address pulse applied according to display data contents.

In the first embodiment, for example, the priming pulse Pxp has a pulse width of 7 μsec and a voltage of 3
10V, the sustain discharge pulse Sp has a voltage of 180V,
The priming auxiliary Pwp has a voltage of 150 V, the scan pulse Scp has a voltage of -180 V, and the address pulse A
wp is set to a voltage of 60V.

In the first embodiment, in one field, only the conventional subfield A to which a high-voltage priming pulse Pxp for performing full lighting and full erasing is applied, and only the cell that was lit in the previous subfield are selectively used. The sub-field B is applied with an erasing pulse Exp for step erasing. The combination of these subfields is arbitrary, but as shown in FIG. 4 showing the configuration of the subfields of one whole field, the subfield (L
When erasing the sustain discharge period (SB and 2LSB), the priming pulse Pxp is set to be applied during the reset period of the next subfield.

Next, the operation will be described. First, in the reset period at the beginning of the subfield A shown in FIG. 3, the priming pulse Pxp is applied to the first row electrodes Xi commonly connected to all the screens. At this time, in FIG. 2, the switch elements SW15 and SW in the first row electrode drive driver 21 are connected.
The switch 18 and the switch SW12 are turned on, and a pulse in which the power supply voltages of the power supplies Vs and Vw are added is supplied. Since this pulse voltage is as high as 310 V, discharge is started between the first row electrode Xi and the second row electrode Yi, and a large amount of wall charges are generated. Thereafter, in FIG. 2, when the switch element SW16 is turned on, the priming pulse Px
p falls and discharges again only with the generated accumulated wall charges. However, since there is no externally applied voltage, electrons and ions generated by this discharge are neutralized and disappear without being attracted to the row electrodes X and Y.

When the reset period ends, an address period starts. A negative scan pulse Scyp is sequentially applied to the independent second row electrodes Y1 to Yn, and at the same time, an address pulse Awp according to image data is applied to the column electrode Wj, thereby discharging cells to be displayed in a matrix. . In FIG. 2, the switch elements SW9 and SW11 in the second row electrode drive driver 22 are set to O in the selected row line.
N, the voltage of the scan pulse Scyp becomes -Vy
(= −180 V), and non-selected row lines are
In this case, when the switch elements SW7 and SW10 are turned on, the voltage becomes -Vsc (for example, -90 V). At this time, the first row electrode Xi and the second row electrode Yi are triggered by a discharge between the Y-W electrodes of the second row electrode Yi and the column electrode Wi.
A wall charge is formed on the first and second row electrodes Xi and Yi by causing a discharge between the X and Y electrodes.

In the sustain discharge period, display luminance is obtained by discharging a display cell arbitrarily selected in the address period a specified number of times. On the first row electrode Xi side, the switch element S in the first row electrode driving driver 21 in FIG.
W15, SW18 and SW16 are repeatedly turned on and off, and on the second row electrode Yi side, in FIG. 2, the switch elements SW17, 6,
8 and SW5 are repeatedly turned ON and OFF to generate a sustain discharge pulse Sp.

When the sustain discharge period ends, the reset period of the next subfield B starts. Here, only the cells that were lit in the previous subfield are simultaneously discharged to erase the wall charges. In the first embodiment, the reset period is entered as a continuation of the sustain discharge period. In FIG. 2, the switch elements SW17 and SW18 in the first and second row electrode drive drivers 21 and 22 are turned off, so that the capacitor C is turned off.
A voltage is supplied from each of C4 and C5. FIG. 5 schematically shows a voltage waveform and a light emission waveform at that time. As shown in FIG. 5, the emission intensity decreases with the decay of the discharge voltage from the capacitors C4 and C5 during the reset period, and the light is gradually erased while reducing the accumulated wall charge.

This erasing method is disclosed in Japanese Patent Application Laid-Open No. 4-315196.
In contrast to the method using a plurality of erasing pulses of the same polarity shown in Japanese Patent Application Laid-Open Publication No. H10-209, a small change erasing method in which a plurality of bipolar pulses whose voltage values change little by little and which are discharged many times is characterized. It is known that in the discharge via the dielectric layer 6, a plurality of discharges are required for the wall charges to be in a steady state. The method using a plurality of erasing pulses of the same polarity disclosed in the above-mentioned publication takes into consideration the discharge variation of the cell. However, the discharge for erasing is performed only once for the cell, and the erasing using the transient state is performed. Therefore, they tend to be dominated by accidental factors. On the other hand, Embodiment 1
The micro-change type erasing method, as described above, weakens the discharge little by little and reduces the wall charge while selecting a stable operating point in each cell from the steady state in which all cells are lit. Not only does it respond to variations, but it does not rely on accidental factors because it does not use transient states. Therefore, more reliable erasing can be performed.

In the first embodiment, a capacitor is provided as a second power supply on both the first row electrode Xi side and the second row electrode Yi side to perform stepwise erasing.
Either the electrode side or the Y electrode side may be used. Needless to say, the cost is reduced because the number of components of the circuit is reduced, but the time constant for erasure is correspondingly longer.

In the first embodiment, only erase is performed in the form of step erase, but may be applied to the sustain discharge period. That is, the second power supply is turned on and off at a level that does not cause erasure, thereby generating a sustain discharge pulse with a small accumulated wall charge. It is well known that when the voltage is high, the discharge luminous efficiency decreases, and by performing these operations, the discharge luminous efficiency in the sustain discharge period can be improved.

In the first embodiment, the frequency and pulse width of the pulse at the time of the step erase are set to be equal to the frequency and pulse width of the sustain discharge pulse applied during the sustain discharge period. Good. In particular, when the frequency is increased, the time required for erasing can be shortened, and the time utilization rate is improved. The step erasing may be performed with a pulse width corresponding to the narrow pulse, or the pulse width may be changed for each applied pulse. These settings can be easily made only by changing the signal.

Embodiment 2 Next, FIG.
6 is a timing chart of voltage waveforms for explaining a method of driving the plasma display panel according to the first embodiment. In the second embodiment, a small-change erasing method is used to erase a priming discharge by a priming pulse generated at an arbitrary timing irrespective of display information in order to reliably generate a discharge. That is, the voltage value of the priming pulse Pxp is reduced, and the step erasing is used instead of the reset by the self-erasing discharge.

In FIG. 6, the priming pulse Pxp
Is set to a voltage of 280 V and a pulse width of 20 μsec. The step erasure is performed by attenuating the sustain discharge pulse Sp in the same manner as in the first embodiment by using the apparatus shown in FIG. In the second embodiment, the priming pulse P
In order to minimize the voltage value of xp, the pulse width is widened. Further, priming pulse Pxp does not need to be applied to all subfields, and in subfields where priming is not performed, sustain discharge pulse Sp may be attenuated and erased as in the first embodiment.

According to the second embodiment, the dielectric breakdown of the panel can be suppressed by lowering the priming voltage. In general, since the luminance is proportional to the voltage value, according to this method, the luminance in the black display state can be reduced and the contrast can be improved.

Further, the first embodiment is used for erasing wall charges during a sustain discharge period of a subfield having large display luminance information.
By using single-pulse erasing, that is, a priming pulse that is a high-voltage full-lighting pulse using self-erasing discharge, to erase wall charges during a sustain discharge period of a subfield with small display luminance information,
Stable erasure can be performed without increasing the luminance of a subfield having small display luminance information.

In the second embodiment, the priming pulse Pxp is manufactured such that the power supply Vw is superimposed on the power supply Vs in FIG. 2. However, the priming pulse Pxp is provided as an independent power supply, and a switch element and a capacitor are provided. May be performed in a similar manner.

Embodiment 3 In the third embodiment, a method of aligning the polarities of minutely remaining wall charges after stepwise erasing is described. The light emission waveform shown in FIG. 5 shows the sum of the light emission of a large number of cells. In some cells, the pulse is applied to the X electrode and the last one is applied to the Y electrode. Some are the last. Although these are erased, a small amount of wall charges remain, which may cause a failure in the address period of the next subfield. Therefore, in FIG. 7, a pulse of 240 V is applied to the X electrode as the first auxiliary pulse after the end of the step erase,
After that, a second assistant pulse of 180 V is applied to the Y electrode,
After that, a so-called narrow pulse is applied to the X electrode side.

In the cell where the erasing is completed by the accumulation of the positive minute wall charges on the X electrode, the wall charges have the first auxiliary pulse of 240 V
It emits light to be superimposed on. On the other hand, a cell in which erasure has been completed by accumulation of minus minute wall charges cannot emit light because the wall charges act to cancel the first assistant pulse 240V. Since the voltage value is the same as the sustain voltage in the second assistant pulse, only the cell that is turned on by the first assistant pulse is turned on. This pulse stabilizes the discharge and amplifies the wall charges. Thereafter, a conventionally known narrow erase is applied. Of course, this pulse may be a wide pulse or a combined erasing method. Also, round erase may be used.

With such a waveform, the cell in which the wall charges are accumulated at an arbitrary polarity is selectively discharged and erased, whereby the minute residual wall charges can have the same polarity. As a result, the address discharge can be performed without any trouble.

Embodiment 4 The first to third embodiments have mainly described the step erasing method of the small change type erasing method. In the fourth embodiment, a pulse width change type erasing method of the minute change type erasure will be described. FIG. 8 is a diagram showing voltage waveforms in one subfield of the driving method according to the fourth embodiment. In FIG. 8, the voltage of the erase pulse Exp is set equal to the voltage of the sustain discharge pulse Sp, and only the pulse width is changed. Here, the duty ratio is fixed and the frequency is gradually increased, so that erasure can be performed reliably in a short time. The pulse width of the last pulse is 0.3 ~
It is 0.4 μsec.

With such a waveform, the accumulated wall charges are gradually weakened as in the case of stepwise erasing, and erasing can be performed according to the state of the cell even when the number of cells is large. This setting can be easily performed by changing only the signal, so that the number of components is small and a wide erasing margin can be obtained.

Embodiment 5 In the fifth embodiment, a pulse rising speed change type erasing method which is another means of the minute change type erasing method will be described. FIG. 9 is a diagram showing voltage waveforms in one subfield of the driving method according to the fifth embodiment. In FIG. 9, the voltage of the erase pulse Exp is set to be equal to the voltage of the sustain discharge pulse Sp, and the pulse width increases as the rising speed decreases.

With such a waveform, the accumulated wall charges are gradually weakened as in the case of other small-change erasures.
Even if the number of cells is large, erasing according to the state of the cells becomes possible.

The erasing method with the variable pulse width and the erasing method with the rising speed of the pulse may be used for erasing the priming pulse. Can be erased without lowering the margin.

[0067]

As described above, according to the method of driving the plasma display panel according to the present invention, during the reset period, at least one of the first electrode and the second electrode is changed to at least one of the first electrode and the second electrode. A micro-change type erasure that erases accumulated wall charges by applying a pulse group is performed, so the discharge characteristics of many cells can be absorbed and erasure can be performed reliably, resulting in a large screen and high definition. By performing erasure capable of absorbing the variation in discharge of the display cells, the erasure margin can be expanded.

Also, by using stepwise erasure in which the voltage value of the pulse is changed as the above-mentioned minute change type erasure, the discharge characteristics of many cells can be absorbed and erasure can be performed reliably.

Further, by making the frequency of the pulse at the time of the above-mentioned step erasing different from the frequency of the sustain discharge pulse applied to the first electrode and the second electrode during the sustain discharge period, erasing is performed under the optimum condition. be able to.

Further, by using the pulse width change type erasure in which the pulse width is minutely changed as the above-mentioned minute change type erasure, the discharge characteristics of many cells can be absorbed and the erasure can be performed reliably.

Further, by using the rising speed changing type erasing in which the rising speed of the pulse is minutely changed as the above minute changing type erasing, the discharge characteristics of many cells can be absorbed and the erasing can be performed reliably.

Further, by using the above-mentioned small change type erasing for erasing a priming discharge by a priming pulse generated at an arbitrary timing irrespective of display information in order to reliably generate a discharge, the voltage value of the priming pulse can be reduced. A high contrast can be obtained by preventing the panel from withstanding pressure.

In addition, the above-mentioned small change erasure is used for erasing wall charges during a sustain discharge period of a subfield having large display luminance information, and a single pulse is used for erasing wall charges during a sustain discharge period of a subfield having small display luminance information. By using erasure, erasure can be performed without increasing the luminance of a subfield having small display luminance information.

In the single-pulse erasing, stable erasing can be performed by using a priming pulse which is a high-voltage full lighting pulse utilizing self-erasing discharge.

Further, by applying an assisting pulse for aligning the polarity of the remaining wall charges after the above-mentioned minute change type erasure, the polarity of the wall charges can be aligned and the address margin can be expanded.

Further, according to the plasma display panel driving apparatus of the present invention, the first and second electrodes covered with the dielectric layer are arranged side by side on the first substrate, and the first substrate is mounted on the first substrate. A plasma display including a plurality of display cells formed in a matrix by arranging a third electrode crossing the first and second electrodes on a second substrate opposed to the plasma display; In each subfield obtained by dividing one field for displaying an image on a display into a plurality of fields, a reset period for erasing wall charges accumulated on the dielectric layer and a sub-field corresponding to an arbitrary display cell selected in a matrix. The first electrode or the second electrode and the third electrode
An address period in which a discharge is caused between the first electrode and the second electrode to generate a discharge between the first electrode and the second electrode.
A control circuit for transmitting a control output corresponding to each period to each of the electrode driving drivers, including a sustain discharge period for performing a sustain discharge using wall charges accumulated on the dielectric layer between the electrodes.
The first to third electrodes are provided corresponding to the first to third electrodes.
And a first to a third electrode driving driver for respectively outputting a pulse corresponding to the control output from the control circuit to each electrode, and the first electrode or the second electrode One of the electrode driving drivers described above, a second power supply capacitor provided in parallel with the first power supply, and a second power supply capacitor between the first power supply and the second power supply capacitor. Since the second power supply including the provided switch element for switching the power supply is provided, the accumulated wall charges can be erased by a plurality of pulse groups whose voltage values attenuate.

The first power supply applies a sustain discharge pulse to the first electrode and the second electrode during the sustain discharge period, and the second power supply supplies:
Since the battery is charged by the first power supply, the second
Wall charges accumulated by a pulse obtained by attenuating the sustain discharge pulse supplied from the supply power supply of the present invention can be erased.

Further, during the reset period, the switch element stops the voltage supply from the first power supply, switches the power supply to the second power supply capacitor side, and switches the second power supply capacitor. Then, by applying a pulse whose voltage attenuates, the accumulated wall charges can be erased by the step erase method.

[Brief description of the drawings]

FIG. 1 is a sectional view of a cell of a surface discharge type AC-PDP to which a driving method of a plasma display panel according to the present invention is applied.

FIG. 2 is a schematic configuration diagram showing a driving device of the plasma display panel according to Embodiment 1 of the present invention.

FIG. 3 is a timing chart of voltage waveforms showing a driving method of the plasma display panel according to Embodiment 1 of the present invention.

FIG. 4 is an explanatory diagram showing a subfield configuration of one entire field in the driving method of the plasma display panel according to the first embodiment of the present invention;

FIG. 5 is an explanatory diagram showing light emission waveforms of the plasma display panel driving method according to the first embodiment of the present invention.

FIG. 6 is a timing chart of voltage waveforms showing a method of driving a plasma display panel according to Embodiment 2 of the present invention.

FIG. 7 is a timing chart of voltage waveforms showing a method of driving a plasma display panel according to Embodiment 3 of the present invention.

FIG. 8 is a timing chart of voltage waveforms showing a method of driving a plasma display panel according to Embodiment 4 of the present invention.

FIG. 9 is a timing chart of voltage waveforms showing a method of driving a plasma display panel according to Embodiment 5 of the present invention.

FIG. 10 is a perspective view showing a surface discharge type plasma display panel.

FIG. 11 is an explanatory diagram showing voltage waveforms in one subfield showing a conventional method of driving a plasma display panel.

FIG. 12 is an explanatory diagram showing a conventional erasing method disclosed in Japanese Patent Application Laid-Open No. 4-315196.

FIG. 13 is a configuration diagram showing a driving device for driving a conventional plasma display panel.

[Explanation of symbols]

Reference Signs List 1 plasma display panel, 2 front glass substrate, 3 back glass substrate, 4 first row electrode (X electrode), 5 second row electrode (Y electrode), 6 dielectric layer, 7
MgO (magnesium oxide), 8 column electrodes, 9 phosphor layers, 10 barrier ribs, Pxp priming pulse (full write pulse), Exp erase pulse, Awp address pulse, Sp sustain discharge pulse, Scyp scan pulse.

Claims (12)

[Claims] A first substrate covered with a dielectric layer on a first substrate;
And a second electrode arranged side by side, and a third electrode intersecting the first and second electrodes is arranged on a second substrate facing the first substrate in a matrix. A method for driving a plasma display including a plurality of display cells to be formed, wherein wall charges accumulated on the dielectric layer are erased in each subfield obtained by dividing one field for image display into a plurality of fields. During a reset period, a discharge is generated between the first electrode or the second electrode and the third electrode corresponding to an arbitrary display cell selected in a matrix to accumulate wall charges on the dielectric layer. The method of driving a plasma display, comprising: an address period; and a sustain discharge period in which a sustain discharge is performed between the first electrode and the second electrode by utilizing wall charges accumulated on the dielectric layer. period A micro-change erasing method for erasing accumulated wall charges by applying a plurality of minutely changing pulse groups to at least one of the first electrode and the second electrode. Display panel driving method. 2. The method according to claim 1, wherein the micro-change erasing is a step erasing in which a voltage value of a pulse is changed.
The driving method of the plasma display panel described in the above. 3. The frequency of the pulse during the step erase is different from the frequency of a sustain discharge pulse applied to the first electrode and the second electrode during the sustain discharge period. The driving method of the plasma display panel described in the above. 4. The method of driving a plasma display panel according to claim 1, wherein the minute change type erase is a pulse width change type erase in which a pulse width is minutely changed. 5. The method of driving a plasma display panel according to claim 1, wherein the minute change type erasing is a rising speed changing type erasing in which a rising speed of a pulse is minutely changed. 6. The erasing method according to claim 1, wherein the small-change erasing is used for erasing a priming discharge by a priming pulse generated at an arbitrary timing irrespective of display information in order to reliably generate a discharge. A driving method of the plasma display panel according to any one of the above. 7. A method of erasing wall charges during a sustain discharge period of a subfield having a large display luminance information using the above-described small change erasure, and a single pulse for erasing wall charges during a sustain discharge period of a subfield having a small display luminance information. 7. The method of driving a plasma display panel according to claim 1, wherein erasing is used. 8. The driving method of a plasma display panel according to claim 7, wherein said single pulse erasing is erasing by a high voltage full lighting pulse utilizing self-erasing discharge. 9. The method according to claim 1, further comprising: applying an assisting pulse for adjusting the polarity of wall charges remaining on the first electrode and the second electrode after the small-change erasing.
9. The method for driving a plasma display panel according to any one of items 8 to 8. 10. A first and a second electrode covered with a dielectric layer are provided side by side on a first substrate, and the first and second electrodes are disposed on a second substrate opposed to the first substrate. A plasma display including a plurality of display cells formed in a matrix by arranging a third electrode crossing the second electrode; and dividing a field for displaying an image on the plasma display into a plurality of fields. In each of the subfields, a reset period for erasing wall charges accumulated on the dielectric layer, the first electrode or the second electrode corresponding to an arbitrary display cell selected in a matrix, and the third An address period in which a discharge is caused between the electrodes and the wall charges are accumulated on the dielectric layer, and the wall charges accumulated on the dielectric layer between the first electrode and the second electrode are used. And the sustain discharge period to perform the sustain discharge A, a control circuit that sends a control output according to each period to each electrode driver, provided corresponding to the first to third electrode, the first
And a first to a third electrode driving driver for respectively outputting a pulse corresponding to the control output from the control circuit to each electrode, and the first electrode or the second electrode One of the electrode driving drivers described above, a second power supply capacitor provided in parallel with the first power supply, and a second power supply capacitor between the first power supply and the second power supply capacitor. A driving device for a plasma display panel, comprising a second power supply comprising a switch element provided for switching the power supply. 11. The first power supply applies a sustain discharge pulse to the first electrode and the second electrode during the sustain discharge period, and the second power supply supplies the first supply power to the first electrode. 11. The driving device for a plasma display panel according to claim 10, wherein the driving device is charged by a power supply. 12. The switch element stops a voltage supply from the first power supply during a reset period, switches power supply to the second power supply capacitor side, and switches the second power supply capacitor. 12. The driving apparatus for a plasma display panel according to claim 10, wherein a step erasing method of erasing a wall charge by applying a pulse whose voltage is attenuated from is applied.