JPH1155591A - Image processor and its method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid the passing of data from occurring in a memory field by predicting data passing that occurs in field memory and appropriately switching write to field memory. SOLUTION: This device is provided with four frame memory which respectively store frame image data of four images which become object of composition processing. The existence of passing of data in field memory that constitute each frame memory is decided from the relationship between a read timing (A) of frame image data to the frame memory and a write start timing (B) of a frame image to the frame memory. A passing phenomenon at the time of four image composition is prevented from occurring by switching field memory in which field image data that constitute frame image data is written based on the result.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus and method for outputting frame image data of a parent screen including a plurality of child screens.

[0002]

2. Description of the Related Art In an image processing apparatus for synthesizing and outputting video signals of two screens input asynchronously in order to display one parent screen including two screens as child screens,
In order to reduce the storage capacity of the memory to be used and to reduce the price, a storage capacity for one frame as a memory (hereinafter also referred to as a frame memory) for temporarily storing the sub-screen when performing the synthesizing process of the video signal. Is used. The child screen is displayed within the parent screen, for example, at a compression ratio that is inversely proportional to the ratio of the display area of the child screen to the parent screen. As described above, when a frame memory having a storage capacity for one frame is used, it is necessary to simultaneously perform the writing operation and the reading operation of the video signal of the small screen to the frame memory. Further, in the above-described image processing apparatus, one frame of the video signal written in the frame memory is read out at a reading speed twice or three times the writing speed in accordance with the compression rate of the small picture.

[0003]

However, when the video signal is read from the frame memory at a reading speed twice or three times the writing speed as described above, the phase difference between the parent screen and the child screen and the parent screen are read. When the video signal of the child screen is read from the frame memory depending on the relationship with the display position of the child screen within the frame, the reading operation may be performed before the writing operation for the video signal ends. As a result, an unsightly horizontal streak may be generated on the parent screen obtained by synthesizing and outputting the child screens.

When performing interlaced scanning in screen display, the frame image data is composed of first field image data and second field image data, and the frame memory stores the first field image data in the frame memory. A first field memory for storing data and a second field memory for storing second field image data are provided.

Therefore, during the normal operation, the writing operation and the reading operation for the frame memory are performed alternately with respect to the first field memory and the second field memory. However, the write operation and the read operation are performed asynchronously and independently of each other, and the read speed is faster than the write speed as described above. The address at which the operation is performed may intersect.

For example, after starting the operation of writing the current frame image data 12 shown in FIG. 14 into the frame memory, the current frame image data 1 is read from the frame memory.
2 is started. At this time, since the read speed is faster than the write speed, depending on the relationship between the timing at which the write operation is started and the timing at which the read operation is started, the read operation may be performed at a certain timing rather than at a certain address. Is performed at the earlier timing. As a result, before the current frame image data 12 is written to the address, a read operation is performed from the address, and as a result, the frame image data 10 of the frame preceding the current frame is read. This phenomenon is called an overtaking phenomenon. When such an overtaking phenomenon occurs, FIG.
As shown in (1), frame image data in which the frame image data 10 of the previous frame and the current frame image data 12 are mixed in one frame is read.

In order to avoid such an overtaking phenomenon, it is necessary to switch the field memory from which reading is performed to a field memory to which writing is not currently performed, and to control so that the overtaking phenomenon does not occur in the field memory. However, conventionally, no specific method for predicting the occurrence of the overtaking phenomenon in the field memory has been known.

The present invention has been made in view of the above-mentioned prior art, and predicts an overtaking of data occurring in a field memory, and can appropriately switch writing to the field memory based on the prediction result. It is an object to provide a processing device and a method thereof.

[0009]

In order to achieve the above object, an image processing apparatus according to the present invention combines frame image data of a plurality of sub-screens to form a frame of a main screen including the plurality of sub-screens. An image processing apparatus for outputting image data, comprising: a first field image data and a second field image data that are provided corresponding to each of the plurality of small screens and that form frame image data of the small screen. A plurality of frame storage means including a first field storage section and a second field storage section for storing, and a write timing detection for detecting a start timing of writing frame image data of the child screen into the frame storage means Means, read control means for controlling reading of frame image data from the plurality of frame storage means, and Image synthesizing means for synthesizing frame image data of a plurality of child screens read out from the memory storage means and outputting frame image data of the parent screen, and from timing when reading of the frame image data from the frame storage means is started. One frame section is divided into a plurality of determination areas for determining whether data overtaking occurs in at least one of the first field storage unit and the second field storage unit, and the timing detection is performed. Determining means for determining whether the data overtaking occurs by detecting to which of the plurality of determination areas the write start timing detected by the means belongs; If it is determined that no overtaking of the data will occur, the first field image data is replaced with the first field data. The second field image data is written to the second field storage unit after the data is written to the first field image data, and if the determination unit determines that the overtaking of the data occurs, the second field image data is written to the first field image data. And writing control means for writing the second field image data into the first field storage section after writing the second field image data into the second field storage section.

In the image processing apparatus according to the present invention, the determination means determines whether or not data has been overtaken in the field storage unit, and based on the determination result, determines whether or not the data has been overtaken by the write control means. The field storage for writing the image data is switched.

In the image processing apparatus according to the present invention, preferably, the writing control means performs the writing when the overtaking of the data is determined by the determining means and the overtaking is determined not to occur. Control is performed so that writing is started from a line one line before the start line.

Preferably, the image processing apparatus of the present invention further comprises a read timing detecting means for detecting a timing at which reading of the frame image data from the frame storage means is started based on the frame image data of the main screen. Have more.

Further, the image processing method of the present invention is provided corresponding to each of a plurality of small screens, and includes a first field image data and a second field image data constituting frame image data of the small screen. Using a plurality of frame storage means provided with a first field storage unit and a second field storage unit for storing, frame image data of a plurality of sub-screens are synthesized, and a parent screen including the plurality of sub-screens is synthesized. An image processing method for outputting frame image data, comprising: detecting a start timing of writing frame image data of the child screen into the frame storage unit, and reading frame image data from the plurality of frame storage units. Controlling the frame image data of the plurality of sub-screens read from the frame storage means to synthesize the frame of the main screen. Image data is output, and at least one of the first field storage unit and the second field storage unit overtakes data in one frame period from the timing at which reading of the frame image data from the frame storage unit is started. It is divided into a plurality of determination areas for determining whether or not the writing occurs, and it is detected which of the plurality of determination areas the write start timing detected by the timing detection means belongs to. Thus, it is determined whether or not the overtaking of the data occurs. If it is determined that the overtaking of the data does not occur, the first field image data is written into the first field storage unit. 2 is written in the second field storage unit, and the data is overtaken by the determination unit. If it is determined that that is the said first field image data second
After writing to the first field storage unit, the second field image data is controlled to be written to the first field storage unit.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an image processing apparatus according to an embodiment of the present invention will be described. First Embodiment An image processing apparatus according to the present embodiment combines frame image data of four screens to generate frame image data of one parent screen including four child screens. In this image processing apparatus, overtaking of data generated in a frame memory is predicted, and a field memory for writing image data is switched using the prediction result.

The overtaking prediction method will first be adopted in the image processing apparatus, a method for predicting the passing of data to be generated in the field memory. In this image processing apparatus, the number of effective pixels per line is set to 360 pixels, which is half of 720 pixels.
Image data in which the number of effective lines is 240 lines, which is half of 480 lines, is written to each frame memory. In addition, reading of image data from the frame memory is performed by 1
Since it is necessary to read out four frames of image data in a time-division manner during the frame period, the write clock frequency of 2
It is performed at twice the clock frequency. Therefore, the reading time of one frame of image data from the frame memory is completed in half the writing time.

FIG. 1 is a diagram for explaining write and read timings when data overtaking occurs in a field memory. As shown in FIG. 1, the write operation of the field image data of the current frame into the field memory is performed at a write start timing 20.
At the writing end timing 26.
The operation of reading field image data from the field memory is started at a read start timing 22 and ends at a read end timing 24. Further, for example, the reading speed of the field image data from the field memory is four times the writing speed.

In the example shown in FIG.
8, data overtaking occurs. Therefore, before the overtaking timing 28, the field image data of the current frame is read out after being written to the field memory. However, after the overtaking timing 28, the field image data of the current frame is read out before being stored in the field memory. Since the operation is performed, the field image data of the previous frame is read. Therefore, as shown in FIG. 2, the field image data read from the field memory is divided by the line "37".
The field image data of the current frame and the field image data of the previous frame are mixed.

FIG. 3 is a diagram for explaining write and read timings when data overtaking does not occur in the field memory. As shown in FIG.
The writing operation of the field image data of the current frame into the field memory is performed at the writing start timing 2
0, and ends at the write end timing 26. The operation of reading the field image data from the field memory is performed at the read start timing 32.
And ends at the read end timing 34.
Further, for example, the reading speed of the field image data from the field memory is four times the writing speed.

In the example shown in FIG. 3, the field image data of the current frame is read out for all the lines, and then the field image data of the subsequent frame is written. The field image data of the frame is not mixed. That is, data overtaking does not occur in the field memory. In FIG. 3, if the read start timing 32 is shifted in the direction of arrow A, or if the field memory accessed in the read operation differs from the field memory accessed in the write operation, data overtaking does not occur.

FIG. 4 is a diagram for explaining write and read timings in other cases where data overtaking does not occur in the field memory. As shown in FIG. 4, the operation of writing the field image data of the current frame into the field memory is started at a write start timing 20 and ends at a write end timing 26. The operation of reading the field image data from the field memory is started at the read start timing 42 and ends at the read end timing 44. Further, for example, the reading speed of the field image data from the field memory is 4 times the writing speed.
Doubled.

In the example shown in FIG. 4, since the field image data of the current frame is written for all the lines after the field image data of the current frame is written, the read field image data differs from the read field image data. The field image data of the frame is not mixed. That is, data overtaking does not occur in the field memory. In FIG. 4, if the read start timing 42 is shifted in the direction of arrow A, or if the field memory accessing the read operation differs from the field memory accessing the write operation, data overtaking does not occur.

Hereinafter, a specific method for predicting the overtaking of data in the field memory according to the present embodiment will be described. In the present embodiment, four screens are synthesized and
The determination of whether to overtake data in the field memory when outputting a parent screen including two child screens is performed based on the relationship between the synchronization phase of the parent screen and each child screen and the display position of each child screen. One frame period is divided into three regions from the read start timing, and whether or not there is overtaking of data in each field memory for each of the four sub-screens based on the relationship between each of the divided regions and the write start timing of each sub-screen. Are simultaneously determined.

That is, in the present embodiment, the four frame memories respectively storing the frame image data of the four screens to be subjected to the synthesizing process are the same as those of the frame memory shown in FIG. 5B and the start timing of writing frame image data to the frame memory shown in FIG. 5B, it is determined whether or not data has passed in the field memories constituting each frame memory. .

As shown in FIG. 5 (B), one frame period from the start of the operation of reading the image data of the four sub-screens constituting the main screen from the four frame memories is defined as the first field of the main screen. An area 55 extending from the upper screen read start timing 51 to the lower read start timing 52 of the first field, and a lower field read start timing 52 of the first field to start reading the lower screen of the second field. Timing 5
3 and an area 57 extending from the lower screen read start timing 53 of the second field to the upper screen read start timing 51 of the first field. . Here, the upper screen is the child screens 60 and 61 shown in FIG. 6, and the lower screen is the child screens 62 and 63 shown in FIG. In this embodiment,
As will be described later, the write start timing of the frame image data to each frame memory is determined by the count value of the line counter in the above-described areas 55, 56, and 55.
It is determined to which of 57 the region belongs.

Then, it is determined whether or not data overtaking occurs in the field memory based on the area determination result and the following overtaking occurrence conditions. [Conditions that No Overtaking Occurs] (a) When the start timing of writing image data to each frame memory is within the area 56 (b) Child screens 60 and 61 located on the upper side of the screen shown in FIG.
In the case where the writing start timing to the frame memory for storing the frame image data exists in the area 55 (c) the sub-screens 62 and 63 located at the lower side of the screen shown in FIG.
When the write start timing to the frame memory for storing the frame image data of

[When Overtaking Occurs] (d) Sub-screens 60 and 61 located at the upper side of the screen shown in FIG.
When the write start timing to the frame memory for storing the frame image data exists in the area 57. (e) The child screens 62 and 63 located at the lower side of the screen shown in FIG.
When the timing to start writing to the frame memory that stores the frame image data of

Hereinafter, the configuration of the image processing apparatus of this embodiment and a remote monitoring system using the image processing apparatus will be described. FIG. 7 is a system configuration diagram of a remote monitoring system 70 using the image processing device 74 described above. FIG.
As shown in FIG.
1 _1, 71 _2, 71 _3, 71 _4, monitor 72,146,
A transmitter 73, a communication network 140, a receiver 142, and a remote controller 148 are provided. Here, the cameras 71 ₁ , 7
1 _2, 71 _3, 71 _4, a monitor 72 and a transmitter 73
Is provided at the monitoring location. Also, the receiver 142,
The monitor 146 and the remote controller 148 are provided in a management center or the like remote from the monitoring place.

The cameras 71 ₁ , 71 ₂ , 71 ₃ , 71
₄ are installed so as to have different imaging ranges,
Image data S98 ₁ , S98 ₂ , S98 ₃ ,
The S98 _4, respectively outputted to the image processing apparatus 74. Monitor 72, the image processing apparatus 74, the camera 71 _1-7
Inputting image data S98 ₅ main screen, including four children screen corresponding to 1 ₄ of the imaging result, and displays the main screen corresponding to the image data S98 _5.

The transmitter 73 includes an image processing device 74 and an image
An image compression encoding transmission device 75 is provided. Image processing device
Reference numeral 74 denotes a camera 71 as described later.₁, 71_Two, 71
_Three, 71 _FourImage data S98 of the imaging range from₁, S9
8_Two, S98_Three, S98_FourAnd synthesize them based on
To generate image data S74 of the parent screen including four child screens.
This is output to the image compression / encoding / transmission apparatus 75.
The image compression encoding transmission device 75 compresses the image data S74.
The compressed image data is compressed as compressed image data S75 on the communication network 14.
0 to the receiver 142.

The receiver 142 has an image compression / decoding transmission device 144. Image compression / decoding transmission device 144
Is transmitted via the communication network 140 to the image compression / encoding / transmission apparatus 7.
The image data S144 obtained by decompressing and decoding the compressed image data S75 received from No. 5 is output to the monitor 146 for display. Further, in response to the operation of the remote controller 148 by the user, the control signal S148 is transmitted from the remote controller 148 to the receiver 1
From 42 is transmitted to the transmitter 73. And the control signal S
148, the image processing device 74 and the camera 7
1 _1, 71 _2, 71 _3, 71 ₄ is controlled.

FIG. 8 is a block diagram of the image processing apparatus 74 of this embodiment shown in FIG. As shown in FIG. 8, the image processing device 74 includes frame memories 76 ₁ , 76 ₂ , 76 ₃ ,
76 _4, the writing-side selector 80 _1, 80 _2, 80 _3,
80 _4, the read-side selector 82 _1, 82 _2, 82 _3,
82 _3, the multiplexing unit 84, the write control unit 86, the read control unit 88, the field memory write switching judgment circuit 90, line counter 92, frame start position detection unit 94 _1, 94 _2, 94 _3, 94 _4, 94 ₅ Have.

Frame start position detectors 94 _{1 to} 94 _1
4, the image data S98 ₁ shown in FIG. 7 which is inputted from the camera 71 _{1-71 4} shown in FIGS 7, S98 _2, S
98 _3, S98 sync signal S96 contained in _{4 1,} S96
_2, S96 _3, S96 ₄ on the basis of, respectively detects a write start timing of the frame image data to the frame memory 76 _{1-76 4,} the detection result of the frame start signal S94 _1, respectively, S94 _2, S9
4 _3, S94 outputs the determination circuit 90 as a _4. Also,
Frame start position detection unit 94 ₅ in accordance with the synchronization signal S96 ₅ for reading included in the image data of the main screen,
Detecting a read start timing of the frame image data to the frame memory 76 _{1-76 4,} and outputs the line counter 92 the result of detection as a frame start signal S94 _5.

The line counter 92, based on the frame start signal S94 ₅ for reading from the frame start position detector 94 _5, the number of lines from the head position of the read frame (reading start timing) one frame period, counted, The three areas 55, 56, 5 shown in FIG.
The count value indicating the boundary portion of the
Decoding as a region identification signal S92a of each area 2a, with the same frame start signal S92b and frame start signal S94 _5, and outputs the determination circuit 90.

The determination circuit 90 includes a frame start signal S94 ₁ from the frame start position detectors 94 _{1 to} 94 ₄ ,
S94 _2, S94 _3, S94 and _4, based on the region identification signal S92a and the frame start signal S92b from the frame start position detector 94 _5, each frame start signal S94 ₁ ~S94 ₄ is a region 55 shown in FIG. 5 , 5
Of 6,57, which region or determined it belongs, and outputs a determination signal S90 ₁ ~S90 ₄ indicating the determination result to the write-side selector 80 _{1-80 4} respectively. The determination signal S90 ₁ ~S90 ₄ is also output to the write control unit 86.

The writing-side selector 80 _{1-80 4,} based on the respective determination signals S90 ₁ ~S90 _4, respectively field memories 78 ₁₁ and 78 _12, the field memory 78 ₂₁ and 78 _22, the field memory 78 ₃₁ and 78 _32, selecting one of the frame memory of the field memory 78 ₄₁ and 78 _42.

Write-side selector 80₁~ 80_FourIs
In the normal operation, the child screens 60, 61, and 61 shown in FIG.
62, 63 image data S98₁, S98_Two, S9
8_Three, S98_FourFor the frame start signal S94
₁, S94_Two, S94_Three, S94 _FourAs indicated by
First first field after start of frame
Image data is stored in the field memory 78₁₁, 78_{twenty one}, 7
8₃₁, 78₄₁To the next second field image data
Data to field memory 78₁₂, 78_{twenty two}, 78₃₂, 78
₄₂, But the judgment signal S90₁~ S90_FourOvertake
The first first field image
Data is stored in the field memory 78₁₂, 78_{twenty two}, 78 ₃₂, 7
8₄₂To the next field image data.
Field memory 78₁₁, 78_{twenty one}, 78₃₁, 78₄₁Write on
Switch the write destination field memory
You.

Note that the write-side selectors 80 ₁ to 80 ₄
The determination signal S90 ₁ ~S90 ₄ indicates the occurrence of overtaking, after switching field memory, judgment signal S9
0 ₁ ~S90 ₄ is if it becomes as indicating no overtaking returns to normal operation.

[0038] Specifically, for example, the writing-side selector 80 _1, as shown in FIG. 9, when the determination signal S90 ₁ indicates the presence of overtaking connects the switch 100 to the "2" side, This switch 101 is connected to the field memory 78 _12. On the other hand, the writing-side selector 80 _1, determination signal S90 when _{the 1} indicates the absence of overtaking connects the switch 100 to the "1" side, whereby the switch 101 is a field memory 7
8 Connected to the ₁₁ side. Write-side selector 80 ₂ to 80
₄ structure is the same as the write-side selector 80 ₁ shown in FIG.

In the write control unit 86, the judgment signal S90
Based on _{1 ~S90 4,} a frame memory 7 which overtaking switches the field memory is expected to write to
Against 6 _{1-76 4,} the write start line of the second field so that before one line than normal controls writing. Specifically, as shown in FIG. 9, the control signal generation unit 102 generates a memory write line control signal S102 with the start line one line before using the field memory write line control signal S105. The write in the selector 103, when the determination signal S90 ₁ indicates the presence of overtaking, the switch is connected to the "2" side, based on the memory write line control signal S102, with respect to the frame memory 76 ₁ Is controlled. On the other hand, the selector 103, when the determination signal S90 ₁ indicates a no overtaking, the switch is connected to the "1" side, based on the memory write line control signal S105, the frame memory 7
6. Writing to ₁ is controlled.

[0040] In this embodiment, the switching control in the writing-side selector 80 _{1-80 4} described above, by the write control of the write control unit 86, the field image data of the image data for the child screen, the frame memories 76 ₁ ~ 76 ₄ two fields memories selectively written.

The read control unit 88 in accordance with the synchronization signal S96 ₅ and the frame start signal S94 ₅ for reading the field memory switching signal S88a and the read address S to the frame memory 76 _{1-76 4}
88b.

Read-side selector 82₁~ 82_FourIs
Switching signal S88 for field memory, respectively₁~ S8
8_FourAnd the vertical position in the parent screen of the child screen to be processed
Frame to read based on and horizontal position
Memory 76₁~ 76_FourAnd field memory
You. At this time, the frame memory 76 for reading₁~
76_FourIs selected by the synchronization signal S96 for reading._Fivefrom
The frame memory 76 starts from the read start position.₁, 7
6_Two, 76_Three, 76_FourIn the order of line scanning on the output screen
Is read out in a time-division manner on a line-by-line basis.
Frame image data S82₁, S82 _Two, S82
_Three, S82_FourIs output to the multiplexing unit 84.

The multiplexing section 84 includes a read-side selector 82
Frame image data S82 ₁ input from _{1-82 4,}
S82 _2, S82 _3, S82 ₄ multiplexes, four child screen is output as the frame image data S74 in the parent screen are synthesized.

Next, an operation example of the image processing device 74 shown in FIG. 8 will be described. FIG. 10 is a diagram showing a timing chart for explaining the operation of the image processing device 74 shown in FIG. FIG. 10A is a diagram showing the timing of the read operation of the frame memory, and corresponds to FIG. FIG. 10B is a diagram showing the relationship between the write start timing of the frame memory and the passing condition, and corresponds to FIG. 5B. FIG. 10 (C),
(D), (E) and (F) respectively show the write start timing (frame start) and write destination of one frame of image data for the frame memories 76 ₁ , 76 ₂ , 76 ₃ and 76 ₄ shown in FIG. 3 is a diagram showing a field memory of FIG.

In the frame memory 76 ₁ , FIG.
As shown in FIG.
Since present in the region 57 of the determination region shown in, from the condition of the above-mentioned (d), it is determined that the overtaking in the determination circuit 90 occurs, the first field image data in the first field memory 78 ₁₂ is stored after then, the second field image data is stored in the field memory 78 _11. The frame start 121 and 122 together, since there the region 57, similarly, first the field memory 78 ₁₂ after the first field image data is stored, then the second field memory 78 ₁₁ Field image data is stored.

Frame memory 76_TwoThen, FIG. 10 (D)
As shown in FIG.
Since it exists in the area 57 of the determination area shown in FIG.
According to the condition (d), the overtaking is performed in the determination circuit 90.
Is determined to occur, first the field memory 78_{twenty two}Second
After one field image data is stored, next,
Field memory 78_{twenty one}The second field image data
It is memorized. Also, the frame start 124 is similarly
Since it exists in the area 57,
Is determined to occur, and first the field memory 7
8_{twenty two}After the first field image data is stored in
Next, the field memory 78 _{twenty one}The second field image
The data is stored.

Frame memory 76_ThreeThen, FIG. 10 (E)
As shown in FIG.
Since it exists in the area 56 of the determination area shown in FIG.
From the condition (a), the overtaking is determined in the determination circuit 90.
It is determined that no error occurs, and₃₁To
After the first field image data is stored,
Field memory 78₃₂To the second field image data
Is stored. Also, frame start 126 is the same.
In addition, since it exists in the area 56,
It is determined that no overtaking will occur and the field
Moly 78 ₃₁Stored the first field image data
Later, then, the field memory 78₃₂The second feel
Image data is stored.

In the frame memory 76 ₄ , FIG.
As shown in FIG.
Since present in the region 55 of the determination region shown in, from the condition of the above-mentioned (e), it is determined overtaking occurs in the decision circuit 90, first to first field memory 78 ₄₂
After field image data is stored, then the second field image data is stored in the field memory 78 _41. Next, the frame start 126 is executed as shown in FIG.
Since present in the region 56 (B), the the condition of the above-mentioned (a), it is determined that overtaking does not occur in the determination circuit 90, the first field image data is stored in the first field memory 78 ₄₁ after the, then, the second field image data is stored in the field memory 78 _42.

As described above, the image processing device 74 divides one frame period into three regions when reading out frame image data from the frame memory, so that the image data can be input asynchronously with those regions. The overtaking phenomenon occurring in each field memory is predicted and determined in advance based on the frame image data writing start positions of the two small screens. Then, by switching the field memory in which the field image data constituting the frame image data is written based on the determination result, it is possible to prevent the overtaking phenomenon at the time of combining four screens. Further, in order to avoid the occurrence of overtaking, when the field memory of the writing destination is switched, it is possible to correct the line deviation on the display screen in the interlaced scanning.

Second Embodiment The image processing apparatus according to the present embodiment combines frame image data of 16 screens, and as shown in FIG. 11, 16 sub-screens located in a 4 × 4 matrix form. Is generated for one parent screen. In this image processing apparatus, overtaking of data generated in a frame memory is predicted, and a field memory for writing image data is switched using the prediction result.

FIG. 12 shows an image processing apparatus 17 according to this embodiment.
4 is a configuration diagram of FIG. As shown in FIG.
174 is a 16-frame memory 176 ₁~ 17
6₁₆, 16 write-side selectors 180₁~ 18
0₁₆, Read-side selector 182₁~ 182₁₆,Multiplexing
Unit 184, write control unit 186, read control unit 18
8. Field memory write switching determination circuit 19
0, line counter 192, 16 frame start positions
Detector 194₁~ 194₁₆Having. In FIG.
Functionally similar to the image processing device 74 shown in FIG.
Have the same name.

In the image processing device 174, the small-screen image data S198 _{1 to} S198 ₁₆ are converted into a judgment signal S190 _1.
～S190 ₁₆ writing-side selector 180 ₁ based on
In response to the switching of 180 _16, the data is selectively written into one of the field memories A and B of the frame memories 176 _{1 to} 176 ₁₆ . Further, the multiplexing unit 184, the frame image data S182 ₁ ~S182 ₁₆ from the reading-side selector 182 _{1-182 16} are multiplexed,
This is output as frame image data S174 of the parent screen in which 16 child screens are combined as shown in FIG.

Hereinafter, a method of determining whether to pass data by the determination circuit 190 will be described. That is, in the present embodiment, 16 frame memories each storing frame image data of 16 screens to be subjected to the synthesis processing are compared with those of the frame memory shown in FIG. From the relationship between the read timing and the timing to start writing frame image data to the frame memory shown in FIG. 13B, it is determined whether or not data is overtaken in the field memories constituting each frame memory.

As shown in FIG. 13B, one frame period from the timing at which the operation of reading the image data of the 16 child screens constituting the parent screen from the 16 frame memories is started is shown in FIG. A region 160 extending from the read start timing 151 of the first screen of the first field of the screen to the read start timing 152 of the second screen of the first field;
An area 161 having a range from the read start timing 152 of the second screen of the field to the read start timing 153 of the third screen of the first field.
And an area 162 extending from the read start timing 153 of the third screen of the first field of the first field of the parent screen to the read start timing 154 of the fourth screen of the first field. The read start timing 15 of the second screen of the second field from the read start timing 154 of the fourth screen of the one field
5 and the read start timing 155 of the second screen of the second field of the parent screen.
From the read start timing 156 of the third screen in the second field of the second field from the first field, and the second field from the read start timing 156 of the third screen in the second field of the parent screen. A region 165 extending to the read start timing 157 of the fourth screen, and the first screen of the first field from the read start timing 157 of the fourth screen of the second field of the parent screen And a region 166 extending to the read start timing 151 of FIG.

[0055] Here, the first stage of the screen is Shimesuko screen 160 _{1-160 4} 11, and the second stage of the screen is Shimesuko screen 160 _{5-160 8} 11, The screen of the third row is the child screens 160 _{9 to} 160 ₁₂ shown in FIG. 11, and the screen of the fourth row is the child screen 160 ₁₃ shown in FIG.
Is 160 _16. Further, the image data S198 ₁ ~S198 ₄ of the child screen 160 _{1-160 4} is stored in the frame memory 176 _{1 to 176 4,} respectively. Child screen 16
0 _{5-160 8} image data of S198 ₅ ~S198
₈ is stored in the frame memory 176 _{5-176 8} respectively. Image data S1 of child screens 160 _{9 to} 160 ₁₂
98 _{9 to} S198 ₁₂ are stored in the frame memory 176, respectively.
It is stored in the _{9-176 12.} Sub screen 160 _{13 to} 160 ₁₆
Image data S198 ₁₃ ~S198 ₁₆ of are respectively stored in the frame memory 176 _{13-176 16.}

In this embodiment, the determination circuit 190 uses the count value of the line counter 192 shown in FIG. 12 to determine whether the writing start timing of the frame image data to each frame memory is equal to the area shown in FIG. It is determined to which region among 160 to 166 it belongs.

Then, the determination circuit 190 determines whether or not data overtaking occurs in the field memory based on the area determination result and the following overtaking occurrence conditions. [Conditions where overtaking does not occur] (f) and (g) below
If either one of the conditions is satisfied, the frame memory 176
In all _{1-176 16,} passing data does not occur. (F) The timing to start writing image data to all of the frame memories 176 _{1 to} 176 ₁₆ is determined in the area 16
If it exists in 3

[0058] The write start timing of the image data for all the case conditions are satisfied (g-1) frame memory 176 _{1 to 176 4} (g) below (g-1) ~ (g -4) is, respectively present in the area 160,161,162,163 (g-2) writing start timing of the image data of the frame memory 176 _{5-176 8} is present in the area 161, 162, 163, and 164 respectively (G-3) Image data write start timings for the frame memories 176 _{9 to} 176 ₁₂ exist in the areas 162, 163, 164, and 165, respectively. (G-4) Frame memories 176 _{13 to} 176 ₁₆ The write start timing of the image data exists in the areas 163, 164, 165, and 166, respectively.

[When Overtaking Occurs] The frame memories 176 _{1 to} 176 ₁₆ store the data in the above-mentioned (e) and (g-
When none of the conditions 1) to (g-4) is satisfied,
Frame memories 176 _{1 to} 176 that do not satisfy the conditions
₁₆ is overtaken.

As described above, the image processing device 174
According to the above, without causing data overtaking in the frame memories 176 _{1 to} 176 ₁₆ , the 16 frame image data input asynchronously are synthesized, and the frame of the parent screen including the 16 child screens is synthesized. Image data can be generated.

The present invention is not limited to the above embodiment. In the above-described embodiment, the case where the frame image data of the main screen is generated by synthesizing the four and sixteen frame image data has been exemplified. However, the number of frame image data to be synthesized in the present invention is arbitrary.

[0062]

As described above, according to the present invention,
By predicting the overtaking of the data occurring in the field memory and switching the writing to the field memory based on the prediction result, it is possible to avoid the occurrence of the overtaking of the data in the field memory. For this reason, it is possible to prevent unsightly horizontal streaks from being generated on the parent screen obtained by combining and outputting the child screens.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining write and read timings when data overtaking occurs in a field memory;

FIG. 2 is a diagram for explaining a read image when data overtaking shown in FIG. 1 occurs.

FIG. 3 is a diagram for explaining write and read timings when data overtaking does not occur in a field memory;

FIG. 4 is a diagram for explaining write and read timings in other cases in which data overtaking does not occur in the field memory.

FIG. 5 is a diagram for explaining a method of determining whether or not data overtakes in a frame memory according to the first embodiment of the present invention.

FIG. 6 is a diagram for explaining a main screen according to the first embodiment of the present invention.

FIG. 7 is a system configuration diagram of a remote monitoring system using the image processing device according to the first embodiment of the present invention.

FIG. 8 is a configuration diagram of the image processing apparatus according to the first embodiment of the present invention shown in FIG. 7;

FIG. 9 is a diagram for explaining a write-side selector and a write control unit illustrated in FIG. 1;

FIG. 10 is a timing chart illustrating the operation of the image processing apparatus illustrated in FIG. 8;

FIG. 11 is a diagram for explaining a main screen according to the second embodiment of the present invention.

FIG. 12 is a configuration diagram of an image processing apparatus according to a second embodiment of the present invention.

FIG. 13 shows a second embodiment of the present invention.
FIG. 9 is a diagram for explaining a method of determining whether data is overtaken in a frame memory.

FIG. 14 is a diagram for explaining a problem of the related art.

FIG. 15 is a diagram for explaining a problem of the related art.

[Explanation of symbols]

 76₁~ 76_Four, 176₁~ 176₁₆… Frame memo
Li, 78₁₁~ 78₄₂... Field memory, 80₁~ 80
_Four, 180₁~ 180₁₆... Write-side selector, 82₁
~ 82_Four, 182₁~ 182₁₆… Readout selector
84, 184: multiplexing unit, 86, 186: write control
, 88, 188... Read control unit, 90, 190.
Constant circuit, 92, 192 ... line counter, 94₁~ 94
_Four, 194 ₁~ 194₁₆… Frame start position detector

Claims (4)

[Claims] An image processing apparatus for synthesizing frame image data of a plurality of sub-screens and outputting frame image data of a parent screen including the plurality of sub-screens, wherein each of the plurality of sub-screens corresponds to each of the plurality of sub-screens. A plurality of frame storage means provided with a first field storage unit and a second field storage unit for storing first field image data and second field image data constituting the frame image data of the child screen; Writing timing detection means for detecting a start timing of writing frame image data of the child screen to the frame storage means; read control means for controlling reading of frame image data from the plurality of frame storage means; Synthesizing frame image data of a plurality of child screens read from the frame storage means; Image synthesizing means for outputting frame image data of the main screen, and storing the one frame period from the timing at which reading of the frame image data from the frame storing means is started, in the first field storage section and the second field storage section. At least one of the sections is divided into a plurality of determination areas for determining whether or not data overtaking occurs. A determination unit that determines whether or not the data is overtaken by detecting which area the data belongs to, and a first unit that determines that the data is not overtaken by the determination unit. Field image data is stored in the first
After the second field image data is written into the second field storage section, the second field image data is written into the second field storage section. After writing data to the second field storage unit, the second
And writing control means for controlling to write the field image data into the first field storage section. 2. The writing control means according to claim 1, wherein when the determination means determines that data overtaking occurs, the writing control means starts writing from a line one line before a writing start line when it determines that overtaking does not occur. The image processing apparatus according to claim 1, wherein control is performed to start. 3. The image processing apparatus according to claim 1, further comprising read timing detection means for detecting a timing at which reading of the frame image data from the frame storage means is started based on the frame image data of the main screen. . 4. A first field storage section provided corresponding to each of a plurality of small screens, and storing first field image data and second field image data constituting frame image data of the small screen. Image processing for synthesizing frame image data of a plurality of sub-screens using a plurality of frame storage units having a second field storage unit and outputting frame image data of a parent screen including the plurality of sub-screens In the method, a start timing of writing frame image data of the child screen to the frame storage unit is detected, reading of frame image data from the plurality of frame storage units is controlled, and reading from the frame storage unit is performed. Combining the frame image data of the plurality of child screens thus output and outputting the frame image data of the parent screen, It is determined whether or not data overtaking occurs in at least one of the first field storage unit and the second field storage unit for one frame section from the timing at which the reading of the frame image data from the system storage unit is started. A plurality of areas for determination, and by detecting which of the plurality of areas for determination the write start timing detected by the timing detection means belongs to, the data is overtaken. Is determined, and if it is determined that data overtaking does not occur, the first field image data is written in the first field storage unit, and then the second field image data is stored in the first field storage unit. When the data is written to the second field storage unit and it is determined that data overtaking occurs, the first field An image processing method for controlling to write the second field image data to the first field storage unit after writing the image data to the second field storage unit.