JPH1155039A - Mixer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a mixer circuit which operates at a low voltage and reduces the leak age of a local signal to an output side. SOLUTION: Active filters 30 and 40 for blocking the passage of a local signal are provided on the post stage of a double balanced mixing part 20 constituted by using four MOS-FETS 21 to 24. Input signals are supplied to the drains of 1st and 2nd FETS 21 and 22, while input signals with phases different at 180 deg. are supplied to the drains of 3rd and 4th FET 23 and 24. The local signals are suplied to the gates of the 1st and 4th FETS 21 and 24, and the local signals with phases different at 180 deg. are supplied to the getes of the 2nd and 3rd FETS 22 and 23. A 1st mixing signal is extracted from the node of the sources of the 1st and 3rd FETS 23 and supplied to the 1st active filter 30. A 2nd mixing signal is extracted from the node of the sources of the 2nd and 4th FETS 22 and 24 and supplied to the 2nd active filter 40.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mixer circuit used in a transceiver for wireless communication and the like, and more particularly, to a cascade connection of a mixing section for mixing an input signal and a local signal and an active filter section. Thus, the present invention relates to a mixer circuit that can operate at a low voltage and reduces leakage of a local signal to an output side.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram of a conventional Gilbert cell type mixer circuit. The conventional mixer circuit 100 includes:
It comprises a voltage-current converter 110, a mixing unit 120, and a load unit 130. Positive and negative power supply VCC,
Between the VEEs, the load unit 130, the mixing unit 120, and the voltage-current conversion unit 110 are cascaded and connected in that order.

The voltage-current converter 110 includes two N-channel depletion type MOS-FETs (hereinafter referred to as FETs) 111 and 112. Each FET 111, 11
The two sources S are each connected to the negative power supply VEE. The gate G of one FET 111 is connected to the first differential signal input terminal 101, and the gate G of the other FET 112 is connected to the second differential signal input terminal 101.
Are connected to the differential signal input terminal 102. The first differential signal input terminal 101 is supplied with a high-frequency first input signal, and the second differential signal input terminal 102 is supplied with a second input signal having a phase 180 degrees different from the phase of the first input signal. Is supplied.

The mixing section 120 includes four N-channel depletion type MOS-FETs (hereinafter, referred to as FETs) 121, 122, 123, and 124. FET
The source S of the FET 121 and the source S of the FET 122 are connected to each other.
111 is connected to the drain D. The source S of the FET 123 and the source S of the FET 124 are connected to each other and to the drain D of the FET 112 of the voltage-current converter 110. Gate G of FET122
And the gate G of the FET 123 are connected to each other and to the first local signal input terminal 103. Gate G of FET 121 and Gate G of FET 124
Are connected to each other and to the second local signal input terminal 104. The first local signal input terminal 103 is supplied with a first local (local oscillation) signal, and the second local signal input terminal 104 is supplied with a first local (local oscillation) signal having a phase different from that of the first local (local oscillation) signal by 180 degrees. Two local (local oscillation) signals are provided. FET1
The drain D of the FET 21 and the drain D of the FET 123 are connected to each other. Drain D of FET122 and FET
The drain D 124 is connected to each other.

[0005] The load unit 130 is connected to the positive power supply VCC and the FET1.
21, a first load resistor 131 interposed between each drain D of the FET 123, the positive power supply VCC and the FET 12
A second load resistor 132 interposed between each drain D of the FET 124; Second load resistance 1
A connection point between the D. 32 and each drain D of the FET 122 and the FET 124 is connected to the first differential output terminal 105, and a connection point between the first load resistor 131 and each drain D of the FET 121 and the FET 123 is connected to the second differential output terminal. Connected to output terminal 106.

The conventional mixer circuit 100 is configured to cancel even-order distortion by making both the operation of the voltage-current conversion unit 110 and the operation of the mixing unit 120 differential.

Japanese Patent Application Laid-Open No. 54-100617 discloses that the sources of the first and second MOS-FETs are connected to each other and the sources of the third and fourth MOS-FETs are connected to each other. And the first and second MOS-FE
T and the third and fourth MOS-F
Connecting the connection points of the respective sources of ET to the drains of the fifth and sixth FETs respectively connected to the differential amplifier configuration;
A high-frequency input signal is supplied to the gates of the fifth and sixth FETs, a local oscillation signal of the first polarity is supplied to respective gates of the first and fourth MOS-FETs, and second and third input signals are supplied.
To the respective gates of the MOS-FETs, a local oscillation signal of a second polarity, which is 180 degrees out of phase with the local oscillation signal of the first polarity, is supplied to the respective drains of the first and third MOS-FETs. Second and fourth MOS connected to each other
A mixer circuit is described in which the respective drains of the FET are connected to each other and an intermediate frequency signal is extracted from a connection point of these drains.

[0008]

However, the conventional mixer circuit shown in FIG. 3 or the mixer circuit described in Japanese Patent Application Laid-Open No. 54-10017 is replaced with a low voltage, for example, a pager (wireless call receiver). When used in a wireless communication device or the like that is required to operate at a low current, there are the following problems. (1) The conventional mixer circuit 100 includes a load unit 130, a mixing unit 120, and a voltage-current conversion unit 110.
Are arranged vertically, it is difficult to operate at a low voltage of 2 volts or less. (2) MOS-F
Since the ET has a smaller transfer conductance than the bipolar transistor, it is difficult to obtain a high gain and a low noise characteristic in a low voltage operation. (3) Further, if a circuit design that can obtain a high gain at a low voltage operation is attempted, the distortion in the characteristics of the MOS transistor increases from the above two points.

In order to solve the above-mentioned problem, a low-voltage operation type mixer circuit shown in FIG. 2 is used, for example, in NABIL I. KHACH.
AB and others “Novel Continuous-TIME All MOS FOUR-QUADRAN
T MULTIPLIERS ", 1987 ISCAS, PP762-765. The low-voltage operation type mixer circuit 50 shown in FIG.
Is composed of a mixing section 60 and amplification sections 70 and 80 provided at a stage subsequent to the mixing section 60.

The mixing section 60 includes four N-channel depletion type MOS-FETs (hereinafter, referred to as FETs).
61, 62, 63 and 64. The drain of the first FET 61 and the drain of the second FET 62 are connected to each other and to the first differential signal input terminal 51. The drain of the third FET 63 and the fourth FET 64
Are connected to each other and to the second differential signal input terminal 52. The first differential signal input terminal 51 is supplied with a high-frequency first input signal, and the second differential signal input terminal 52 has a phase of 18 with the first input signal.
A second input signal that is 0 degrees different is provided.

The gate of the first FET 61 and the fourth FET
The gates 64 are connected to each other and to the first differential local signal input terminal 53. Second FE
The gate of T62 and the gate of the third FET 63 are connected to each other and to the second differential local signal input terminal 54. A first local signal input terminal 53 is supplied with a first local (local oscillation) signal, and a second local signal input terminal 54 is supplied with a first local (local oscillation) signal having a phase different from that of the first local (local oscillation) signal by 180 degrees. Two local (local oscillation) signals are provided.

The source of the first FET 61 and the third FET
The sources of 63 are connected to each other and to the input terminal 70a of the first amplifier 70. Second FET 6
The source of the second FET and the source of the fourth FET 64 are connected to each other and to the input terminal 80a of the second amplifier 80.

The first amplifier 70 includes an operational amplifier 71,
An input resistor 72 interposed between the input terminal 70a of the first amplifier 70 and the inverting input terminal 71b of the operational amplifier 71
And the output terminal 71c of the operational amplifier 71 and the operational amplifier 71
Feedback resistor 73 interposed between the inverting input terminal 71b
And The output terminal 71c of the operational amplifier 71 is connected to the first differential output terminal 55. The non-inverting input terminal 71a of the operational amplifier 71 is connected to a reference potential N (ground (0 volt) in the case of a dual power supply configuration, for example, １ ／ of the power supply voltage in the case of a single power supply configuration).

The second amplifying section 80 includes an operational amplifier 81,
Input terminal 80a and inverted input terminal 81b of operational amplifier 81
, An output terminal 81c of the operational amplifier 81, and an inverting input terminal 81b of the operational amplifier 81.
And a feedback resistor 83 interposed therebetween. The output terminal 81c of the operational amplifier 81 is connected to the second output terminal 56. The non-inverting input terminal 81a of the operational amplifier 81 is connected to a reference potential N (ground (0 volt) in the case of a dual power supply configuration).
In the case of a single power supply configuration, the power supply voltage is, for example, １ ／ of the power supply voltage).

The low-voltage operation type mixer circuit 50 amplifies the differential mixing output signal obtained by mixing the differential input signal and the differential local input signal in the mixing section 60 with the amplifying sections 70 and 80, respectively. And each differential output terminal 5
Output to 5,56.

The mixer circuit 50 shown in FIG. 2 does not have a vertical stack of MOS-FETs as shown in FIG. 3, and therefore can operate with a low-voltage power supply. The mixer circuit 50 shown in FIG. 2 includes input resistors 72, 8 in each of the amplifiers 70, 80.
The gain can be set by the resistance ratio between the feedback resistor 2 and the feedback resistors 73 and 83.

In the Gilbert cell type mixer circuit 100 shown in FIG. 3, the distortion (distortion of the differential output signal) has a deep relationship with the gain and the power supply voltage, whereas the mixer circuit 50 shown in FIG. In the configuration, since distortion occurs only in the mixing unit 60, there is an advantage that the reduction of distortion and the setting of gain can be separated.

The distortion characteristic of the mixing unit 60 is mainly determined by the level of a local (local oscillation) signal supplied to each gate of each of the MOS-FETs 61 to 64. The smallest distortion occurs when each MOS-FET 6
Nos. 1 to 64 correspond to cases where a clock waveform having an amplitude sufficient for performing a switching operation is applied.

However, each MOS-FE is connected to each gate.
When the local (local oscillation) signal of a clock waveform having an amplitude sufficient for the T61 to 64 to perform the switching operation is supplied, this local (local oscillation) signal
Leakage at 0,80 (feedthrough of the local signal to the amplification unit) poses a problem.

In a device that handles a weak signal such as a pager (wireless call receiver), the level of a local (local oscillation) signal is higher by several tens of decibels than the level of a received signal that is a differential input signal. Is common. While the amplitude of the clock signal, which is a local signal, is several volts, the level of the received signal, which is a differential input signal, is about several microvolts to several millivolts, and the level difference between the local signal and the differential input signal is large. Even if the received signal is amplified by the low noise amplifier and the amplified output is supplied to the mixing circuit 60, it is difficult to eliminate the levels of the local signal and the received signal.

As a result of the local (local oscillation) signal leaking into each amplifier, a differential output signal including the signal component of the local (local oscillation) signal is output from each amplifier. This may hinder signal processing in a connected signal processing circuit or the like, and may cause a malfunction.

The present invention has been made to solve such a problem, and has as its object to provide a mixer circuit capable of operating at a low voltage and reducing leakage of a local signal to an output side. .

[0023]

In order to solve the above problems, a mixer circuit according to the present invention supplies a first input signal to a drain of a first MOS-FET and a drain of a second MOS-FET. Supplying a second input signal having a phase 180 degrees different from the phase of the first input signal to the drain of the third MOS-FET and the drain of the fourth MOS-FET,
The first local signal is supplied to the gate of the fourth MOS-FET and the gate of the fourth MOS-FET,
A second local signal whose phase differs from the first local signal by 180 degrees is supplied to the gate of the FET and the gate of the third MOS-FET, and the source of the first MOS-FET and the third MOS-FET A first output signal in which the input signal and the local signal are mixed is obtained from the connection point with the source of the second MOS-FET and the source of the second MOS-FET and the fourth M
A mixing unit configured to obtain a second output signal in which an input signal and a local signal are mixed from a connection point with a source of the OS-FET, and a mixing unit connected to a subsequent stage of the mixing unit and having the first output signal as an input A first active filter section for blocking passage of a signal component of a local signal, and a second active filter section connected to a stage subsequent to the mixing section for blocking passage of a signal component of the local signal with a second output signal as an input It is comprised with.

The mixing section mixes a pair of differential input signals having a phase difference of 180 degrees and a pair of differential local signals having a phase difference of 180 degrees to form a pair of mixing signals having a phase difference of 180 degrees. Output a signal. The first active filter section receives the first mixing signal as an input,
A signal in which the signal component of the local signal included in the first mixing signal has been removed or reduced is output. Second
Receives the second mixing signal and outputs a signal in which the signal component of the local signal included in the second mixing signal has been removed or reduced. By each output of the first and second active filter units, a pair of differential output signals in which the signal component of the local signal is removed or reduced is obtained.

The mixer circuit according to the present invention outputs a differential output signal in which the signal component of the local signal has been removed or reduced. Therefore, in a configuration in which a filter is provided at the subsequent stage of the mixer circuit, the order of the filter can be reduced. The filter characteristics can be reduced, and the configuration of the filter circuit can be simplified. The mixer circuit according to the present invention includes:
Since each active filter section is connected to the subsequent stage of the mixing section composed of four MOS-FETs, the mixing section and other circuit sections are not vertically stacked with respect to the power supply. Therefore, the mixer circuit according to the present invention can operate with a low-voltage power supply.

[0026]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a circuit diagram of a mixer circuit according to the present invention. The mixer circuit 10 according to the present invention includes a mixing section 20 and first and second active filter sections 30 and 40 connected to a stage subsequent to the mixing section 20. FIG. 1 shows an example in which a SHALEN-KEY type filter is used for each of the active filter units 30 and 40.

The mixing section 20 includes four N-channel depletion type MOS-FETs (hereinafter, referred to as FETs).
21, 22, 23 and 24. The drain of the first FET 21 and the drain of the second FET 22 are connected to each other and to the first differential signal input terminal 11. The drain of the third FET 23 and the fourth FET 24
Are connected to each other and to the second differential signal input terminal 12. The first differential signal input terminal 11 is supplied with a high-frequency first input signal, and the second differential signal input terminal 12 has a phase of 18 with the first input signal.
A second input signal that is 0 degrees different is provided.

The gate of the first FET 21 and the fourth FET
24 are connected to each other and to the first differential local signal input terminal 13. Second FE
The gate of T22 and the gate of the third FET 23 are connected to each other and to the second differential local signal input terminal 14. The first local signal input terminal 13 is supplied with a first local (local oscillation) signal, and the second local signal input terminal 14 is supplied with a first local (local oscillation) signal having a phase 180 degrees different from that of the first local (local oscillation) signal. Two local (local oscillation) signals are provided.

The source of the first FET 21 and the third FET
Sources 23 are connected to each other and to an input terminal 30a of the first active filter unit 30.
The source of the second FET 22 and the source of the fourth FET 24 are connected to each other and to the input terminal 40a of the second active filter unit 40.

The first active filter unit 30 includes an operational amplifier 31 and a first active filter unit 30 connected in series between an input terminal 30a of the first active filter unit 30 and a non-inverting input terminal 31b of the operational amplifier 31. And the second input resistance 3
2, 33, the inverting input terminal 31a of the operational amplifier 31 and the reference potential N (ground (0 volt) in the case of the dual power supply configuration, for example, 1/2 of the power supply voltage in the case of the single power supply configuration).
A third input resistor 34, a feedback resistor 35 between the output terminal 31c of the operational amplifier 31 and the inverting input terminal 31a of the operational amplifier 31, Each of the resistors 36 and 37 for generating a positive feedback signal, which are provided in series between the output terminal 31c of the
A first capacitor 38 interposed between the non-inverting input terminal 31b of the operational amplifier 31 and the reference potential N; a connection point between the first and second input resistors 32 and 33; And a second capacitor 39 interposed between the connection points of the resistors 36 and 37. The output terminal 31c of the operational amplifier 31 is connected to the first differential output terminal 15.

The first active filter section 30 has a second
A low-pass filter is constituted by the input resistor 33 and the first capacitor 38, and a signal obtained by dividing the output signal of the operational amplifier 31 by the resistors 36 and 37 for generating positive feedback signals is used as the second signal. A positive feedback filter is formed by positively feeding back the connection point between the first and second input resistors 32 and 33 via the capacitor 39.

Then, the first active filter section 30
Is a signal obtained by amplifying the first differential mixing signal supplied from the mixing unit 20 to the input terminal 30a, and removing or reducing the signal component of the local signal included in the first differential mixing signal. To the first differential output terminal 15 as a first differential output signal.

The second active filter section 40 includes a first
Has the same configuration as that of the active filter section 30. The second active filter unit 40 includes an operational amplifier 41,
First and second input resistors 42 and 43 interposed in series between an input terminal 40a of the second active filter unit 40 and a non-inverting input terminal 41b of the operational amplifier 41; The terminal 41a and the reference potential N (positive / negative 2
A third input resistor 44 interposed between a ground (0 volt) in the case of the power supply configuration, and a voltage of, for example, 電源 of the power supply voltage in the case of the single power supply configuration, and an output terminal of the operational amplifier 41 A feedback resistor 45 provided between the inverting input terminal 41a of the operational amplifier 41 and a feedback resistor 45 for generating a positive feedback signal provided in series between the output terminal 41c of the operational amplifier 41 and the reference potential N. Resistors 46 and 47, a first capacitor 48 interposed between the non-inverting input terminal 41b of the operational amplifier 41 and the reference potential N, and first and second input resistors 4
2 and 43 and each resistor 46 and 4 for generating a positive feedback signal.
And a second capacitor 49 interposed between the second capacitor 49 and the connection point 7. The output terminal 41c of the operational amplifier 41 is connected to the first differential output terminal 16.

The second active filter section 40 has a second
Constitutes a low-pass filter by the input resistor 43 and the first capacitor 48, and a signal obtained by dividing the output signal of the operational amplifier 41 by the resistors 46 and 47 for generating positive feedback signals is used as the second signal. Positive feedback is provided to the connection point between the first and second input resistors 42 and 43 via the capacitor 49 to form a positive feedback filter.

The second active filter section 40
Is a signal obtained by amplifying the second differential mixing signal supplied from the mixing section 20 to the input terminal 40a, and removing or reducing the signal component of the local signal included in the second differential mixing signal. To the second differential output terminal 16 as a second differential output signal.

With the above configuration, the mixer circuit 10 according to the present invention converts a local signal, such as a local clock, leaked from the double-balanced mixing section 20 composed of four FETs 21 to 24 into a subsequent stage. , And the differential output signal from which the signal component of the local signal has been removed can be obtained.

The mixer circuit 10 according to the present invention is provided with high-order active filter sections 30 and 40 using an operational amplifier (op-amp) at the subsequent stage of the mixing section 20, so that the mixer shown in FIG. Like circuit 50,
The setting of the overall gain (gain) of the mixer circuit 10 is easy.

The gain K of the SHALEN-KEY type filter is given by Expression 1 for the first active filter unit 30 and by Expression 2 for the second active filter unit 40.

K = 1 + (R35 / R34) (1) K = 1 + (R45 / R44) (2) where R35 is the resistance of the feedback resistor, and R34 is the resistance of the third input resistor. , R45 are the resistance values of the feedback resistor, and R44 is the resistance value of the third input resistor.

Further, there is a relationship shown in Expression 3 between the selectivity Q and the gain K of the SHALEN-KEY type filter.

Q = 1 / (3-kK) (3) Here, the coefficient k for the first active filter unit 30 is given by the following equation (4).
0 is given by Equation 5.

K = R37 / (R36 + R37) (4) k = R47 / (R46 + R47) (5) Here, R37, R37, R46 and R47 are resistors 36 and 37 for generating a positive feedback signal. , 46, and 47 respectively.

By setting the coefficient k to an appropriate value, the selectivity Q and the gain K can be arbitrarily set as required. Thereby, each of the active filter units 30 and 4
At 0, it is possible to selectively pass only the mixing signal having a frequency different from the frequency of the received signal and the frequency of the local signal, for example, and to effectively remove or reduce the signal of the frequency component of the local signal.

Therefore, by applying the mixer circuit 10 according to the present invention to a transceiver for wireless communication, low-voltage operation is enabled, and a local signal such as a local clock is transmitted to a subsequent circuit section or the like. Leakage can be eliminated. In a transceiver for wireless communication or the like, a filter for removing a signal of an unnecessary band component is often provided in a circuit section subsequent to the mixer circuit. The circuit part after the mixer circuit is an IC
If the IC is implemented as an active filter, a switched capacitor filter, a GmC
It is composed of a filter, a gyrator filter and the like. By using the mixer circuit 10 according to the present invention, it is possible to lower the order of a filter provided at a subsequent stage of the mixer circuit. Since the circuit configuration of the filter is simplified by lowering the order of the filter, it is possible to contribute to a reduction in power consumption of a transceiver for wireless communication and the like.

[0045]

As described above, the mixer circuit according to the present invention comprises four MOS-FETs and has a phase difference of 18.
A double-balanced mixing unit that mixes a pair of differential input signals that differ by 0 degrees and a pair of differential local signals that differ by 180 degrees to output a pair of differential mixing signals; and And an active filter section connected to the subsequent stage of the section to block the passage of local signal components contained in the differential mixing signal, so that a differential output signal in which the signal components of the local signal are removed or reduced can be obtained. it can.

Therefore, it is possible to prevent malfunction of the signal processing in the signal processing unit connected to the subsequent stage of the mixer circuit due to leakage of the local signal. Further, in a configuration in which a filter is provided at a stage subsequent to the mixer circuit, the order of the filter can be reduced, the filter characteristics can be reduced, and the configuration of the filter circuit can be simplified.

Further, the mixer circuit according to the present invention has a configuration in which each active filter section is connected to the subsequent stage of the mixing section composed of four MOS-FETs.
The mixing unit and other circuit units do not have a vertically stacked circuit configuration with respect to the power supply. Therefore, the mixer circuit according to the present invention can operate with a low-voltage power supply.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a mixer circuit according to the present invention.

FIG. 2 is a circuit configuration diagram of a low-voltage operation type mixer circuit.

FIG. 3 is a circuit configuration diagram of a conventional Gilbert cell type mixer circuit.

[Explanation of symbols]

Reference Signs List 10 mixer circuit 11, 12 differential signal input terminal (high-frequency signal input terminal) 13, 14 differential local signal input terminal (local oscillation clock signal input terminal) 15, 16 differential output terminal 20 mixing unit 21-24 first Fourth MOS-FET 30, 40 Active filter section 31, 41 Operational amplifier (op amp) 32, 33, 34, 42, 43, 44 Input resistance 35, 45 Feedback resistance 36, 37, 46, 47 For generating a positive feedback signal Resistance 38, 39, 48, 49 Capacitor

Claims (1)

[Claims] 1. A drain of a first MOS-FET and a second
The first input signal is supplied to the drain of the third MOS-FET, and the drain of the third
The phase of the first input signal to the drain of the FET is 180
The first MOS-FE is supplied with a second input signal different from the first MOS-FE
A first local signal is supplied to the gate of T and the gate of the fourth MOSFET, and the first local signal is supplied to the gate of the second MOSFET and the gate of the third MOSFET in phase with each other. Supplies a second local signal that differs by 180 degrees, and the source of the first MOS-FET and the third MOS-F
A first output signal in which an input signal and a local signal are mixed is obtained from a connection point with a source of the ET, and an input signal is input from a connection point between a source of the second MOS-FET and a source of the fourth MOS-FET. A mixing unit configured to obtain a second output signal in which the signal and the local signal are mixed; and a mixing unit connected to a stage subsequent to the mixing unit, wherein the first output signal is input to pass a signal component of the local signal. A first active filter unit for blocking the signal, and a second active filter unit connected to a stage subsequent to the mixing unit and configured to block the signal component of the local signal when the second output signal is input. A mixer circuit characterized by the above.