JPH1154728A - Construction for dynamic random access memory and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the occupied area of an element, and to raise the density of integration by arranging bit-line transistors vertical to capacitors. SOLUTION: Bit line 16 constructions are formed by forming a first insulating film 12 on a semiconductor substrate 10, forming a large number of trenches 14 in the first insulating film 12 by etching, depositing conductive films on them, then removing unnecessary conductive films on the first insulating film 12 by anisotropic etching, and leaving conductive films behind in the trenches 14. And a second insulating film 18 is formed on the first insulating film 12 and the bit lines 16, a flat surface is formed, and buried bit line 16 constructions are formed. Next, a first conductive film 20 and a thin silicon oxide film 22 are laminated successively on the second insulating film 18, a spacer 24 is deposited on the side surface of the first conductive film 20, a third insulating film 26 is deposited, and a large number of thin element holes 28b are formed by etching. Accordingly, it becomes possible to raise the density of integration reducing occupied areas of elements by capacitor constructions arranged vertically.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic random access memory (Dynamic Random Access Memory).
In particular, the present invention relates to a structure of a dynamic random access memory having a vertically arranged capacitor structure, which reduces an element occupying area and improves an integration density, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In order to realize a structure of a high-density dynamic random access memory and a microminiaturization of a sub-micron scale or smaller element, a manufacturing process technology of the dynamic random access memory is constantly improved. Such device miniaturization process technology has already been realized in a special manufacturing process, and for example, a lithography technology and a dry etching technology correspond thereto. Further, by using a precise exposure camera or a photoresist material having better sensitivity, the pattern transfer accuracy of the photoresist film can be improved. Also,
Significant progress has also been made in dry etching technology in the formulation of tools and etchants, and high-density semiconductor devices that precisely transfer submicron scale figures on the photoresist film to the material under the photoresist film Can be produced.

[0003]

However, the fabrication of dynamic random access memory devices with 256 Mbits or more of integration density requires significant advances in fabrication process technology. Usually, the area required by the memory cell of one dynamic random access memory is a minimum scale (Minimu
m Feature) and is described as “8F ² ”.
Currently, there are also those which can be produced at four times the area of the smallest scale, has become of 4F ² dynamic random access memory cells of the memory. The element area is mainly occupied by two basic parts, a bit line transistor and a capacitor.

In general, 4F ² memory cell of a dynamic random access memory, occupies a position that its bit line transistor and a capacitor are different on the semiconductor substrate. If these two parts are superimposed in one place and one area can be used, that is, a structure in which the bit line transistor is arranged perpendicular to the capacitor, the 4F ² dynamic random access memory can be used. An element having a smaller occupied area than that of the memory cell can be manufactured.

In view of the above problems, the present invention provides
A main object of the present invention is to provide a structure of a dynamic random access memory in which a bit line transistor and a capacitor are overlapped to reduce an element occupying area and improve an integration density, and a method of manufacturing the same.

[0006]

In order to solve the above-mentioned problems and achieve the above object, the present invention provides a method for forming a first silicon oxide film on a semiconductor substrate, comprising the steps of: Forming a plurality of trenches thereon, forming a bit line structure in each trench, forming a second silicon oxide film on the bit lines and the first silicon oxide film, and embedding the bit lines Forming a first polysilicon film on the second silicon oxide film; forming a first polysilicon film on the second silicon oxide film; Forming a thin polysilicon oxide film on the film; patterning the thin polysilicon oxide film and the first polysilicon film to form a word line structure on the second silicon oxide film; Forming, forming a spacer made of metal silicide on the side surface of the word line, removing the thin polysilicon oxide film, and forming a third silicon oxide film on the word line and the second silicon oxide film The third silicon oxide film, the substantially central portion of the word line, the second silicon oxide film, and the first silicon oxide film are sequentially etched by lithography and etching until the surface of the bit line is exposed, thereby forming a thin element hole. Forming, forming a gate oxide film on a portion of the side wall of the element hole where the word line is exposed, depositing a first amorphous silicon film in the element hole, and forming a pattern on the first amorphous silicon film.
Etching the amorphous silicon film to form an amorphous silicon sidewall on the sidewall of the element hole, depositing a second polysilicon film in the element hole, performing ion implantation, setting the implantation angle to 0 degree, 3
Doping ions into the second polysilicon film on the silicon oxide film and doping ions into the second polysilicon film at the bottom of the device hole,
A step of not doping the second polysilicon film on the side wall of the element hole with ions, a step of depositing a second amorphous silicon film in the element hole and filling the element hole, and a step of annealing the second amorphous silicon film. , The second conductive film and the first amorphous silicon film are monocrystalline silicon films, and the first deeply doped source / drain is sequentially formed from bottom to top in the element hole by a plurality of times of ion implantation with different doses. Forming a region, a first lightly doped source / drain region, a monocrystalline silicon film, and a second heavily doped source / drain region, wherein the first heavily doped source / drain region has a buried bit line structure. Corresponding to the word line on which the single crystal silicon film is exposed A step of forming the transistor structure, forming a third polysilicon film on the second dark doped source / drain region, third
Patterning a polysilicon film to form a storage node, and disposing the storage node over a second heavily doped source / drain region;
Depositing a dielectric film on the storage node; depositing a fourth polysilicon film on the dielectric film; patterning the fourth polysilicon film to form an upper electrode; Forming a capacitor structure with the upper electrode; and
An object of the present invention is to provide a structure of a dynamic random access memory manufactured by this manufacturing method.

[0007]

In brief, the function of the present invention is provided with a capacitor structure made of polysilicon arranged perpendicular to the word line structure and a bit line structure arranged perpendicular to the word line structure. Thereby, the bit line transistor and the capacitor, which occupy different positions in the prior art, are overlapped in one place to share one area, that is, the bit line transistor is arranged perpendicular to the capacitor. With the structure, an element having a smaller occupied area can be manufactured, and the integration density can be further improved.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments according to the present invention will be described below with reference to the drawings. In FIG. 1, the semiconductor substrate 10 can be, for example, a P-type silicon substrate having a crystal orientation of <100>, but can be applied to an N-type silicon substrate. Then, on this semiconductor substrate 10, for example, a first silicon oxide film
The insulating film 12 is formed by a method of forming a temperature of about 950 to 110 by thermal oxidation.
The temperature is set to 0 ° C., and the silicon on the semiconductor substrate 10 is reacted with oxygen using oxygen as a reaction gas to form the first insulating film 12 as a silicon oxide film.
The range is 500 to 5500 ° (angstrom). Next, lithography and etching are performed, and a large number of trenches 14 are formed in the first insulating film 12 using methane trifluoride (CHF ₃ ) as an etching agent. Trench 1
4 is approximately 3500-4 from the surface of the first insulating film 12.
500 °. The photoresist (not shown) used in this step is plasma oxygen ashing (Plazma Oxyge).
n Ashing).

In FIG. 2, an anisotropic dry etching is performed after depositing a conductive film (not shown) on the first insulating film 12 and the trench 14, and chlorine (Cl ₂ ) is used as an etching agent. As a result, a bit line (Bit Line) 16 is formed in the trench 14. Tungsten metal can be mentioned as a conductive film material to be deposited, and the deposition method is a low pressure chemical vapor deposition (Low Pres
sure Chemical Vapor Deposition = LPCVD), the ambient temperature is in the range of about 300-600 ° C, and the thickness for depositing tungsten hexafluoride as a reactant is about 2000-40.
00 °. In addition, the material of the conductive film may be tungsten silicide (Tungsten Silicide), and tungsten hexafluoride and silane (Silane monosilane Monosilicide) may be formed by low pressure chemical vapor deposition (LPCVD).
lane) as the reactant and the temperature is about 300 to 600
C., and the deposited thickness is in the range of about 2000-4000.degree. For anisotropic etching, the first insulating film 1
2 to remove the unnecessary conductive film and leave the conductive film in the trench 14. The depth of the conductive film is set in the range of about 1000 to 2000 ° from the surface of the first insulating film 12. To form

In FIG. 3A, a second insulating film 18 is formed on the first insulating film 12 and the bit line 16, and a silicon oxide film is preferable. The formation method is tetraethyl orthosilicate (Tetra-Ethyl-Ortho-Silicate =
Low pressure chemical vapor deposition (LPCVD) using TEOS as a reaction gas
) Or plasma enhanced chemical vapor deposition (Plazma EnhancedCh)
emical Vapor Deposition = PECVD)
In the range of 00 to 600 ° C., and the deposition thickness is about 500 to 15
The range is 00 °. And planarization (Planarization)
) Process is performed, but the chemical mechanical polishing (Chemical Mech
(anical Polishing = CPM) so that the second insulating film 18 has a flat surface. Thereby, the bit line 16
Can be a buried bit line 16 structure buried with the second insulating film 18. Next, the first insulating film 18 is formed on the second insulating film 18.
The conductive film 20 is formed, and is preferably a polysilicon film. As a forming method, a monosilane doped with arsenic or phosphorus is used as a reactive gas by a simultaneous doping method (In-Situ Doping Procedures), and a temperature is about 600 to 650 ° C. using a low pressure chemical vapor deposition method.
And the deposition thickness is in the range of about 3000-4000 °. Then, a thin silicon oxide film 22 is formed on the first conductive film 20 by thermal oxidation. Next, conventional photolithography and dry etching are performed. When etching the thin silicon oxide film 22, methane trifluoride (CHF ₃ ) is used as an etching agent, and when etching the first conductive film 20, chlorine (Cl ₂ ) is used as an etching agent. And
To remove the photoresist film (not shown), both plasma oxygen ashing (Plazma Oxygen Ashing) and wet etching are performed.

FIG. 3B shows a cross section obtained by rotating FIG. 3A by 90 degrees. It is preferable that a spacer 24 is formed on the side surface of the first conductive film 20 and the material is metal tungsten. . As a forming method, first, a deposition thickness is about 500 to 1 by sputtering.
A metal tungsten film is deposited in the range of 000 °. Anisotropic Reacti etching
ve Ion Etching), but sulfur hexafluoride (SF ₆ )
Is used as an etchant to form spacers 24 on the side surfaces of the first conductive film 20. At this time, the first conductive film 20 can be prevented from being etched by the thin silicon oxide film 22 on the first conductive film 20.

4 (a) and 4 (b), FIG.
FIG. 4A is a view obtained by rotating FIG. 4A by 90 degrees.
In the washing step, a buffered hydrofluoric acid solution (Bu
ffered Hydrofluoric Acid Solution), the thin silicon oxide film 22 can be removed. And
A third insulating film 26 is deposited on the first conductive film 20. As a method, tetraethylorthosilicate (TTEOS) is used as a reaction gas by plasma-enhanced chemical vapor deposition, the temperature is in the range of about 300 to 600 ° C., and the deposition thickness is about 1000.
Å2000Å. Next, as a precise pattern forming step, a photoresist 28a is formed on the third insulating film 26.
Is formed, and a large number of thin element holes 28b are formed by etching according to the formed pattern. In this step, first, a photoresist 28a is formed, and a large number of openings are formed in the photoresist 28a. The width of the opening is set in a range of about 0.20 μm to 0.30 μm. Then, each film under the opening is etched by dry etching using the photoresist 28a as a mask until the bit line 16 is exposed to form a thin element hole 28b, which has a diameter in the range of about 0.20 μm to 0.30 μm. And
The third insulating film 26 is etched by methane trifluoride (CHF).
3) is used as an etching agent, and the first conductive film 20 is etched using chlorine (Cl2) as an etching agent.
The etching of the second insulating film 16 uses methane trifluoride, and finally the buried bit line 16 serves as a stop film. Then, the photoresist 28a is removed (see FIG. 4A). The method is to perform both plasma oxidizing ashing and wet etching.

In FIG. 5, element holes 2 are formed by thermal oxidation.
A vertical gate insulating film 30 is formed in the first conductive film 20 serving as the 8b side wall. The forming method is to set the temperature in the range of about 900 to 950 ° C. in the atmosphere filled with oxygen and the thickness to be deposited in the range of about 70 to 120 °. Next, a first amorphous silicon (Amorphous Silicon) film 32 perpendicular to the side wall of the element hole 28b is formed. First, the temperature is in the range of about 500 to 550 ° C. and the deposition thickness is about 200 to 550 ° C. by low pressure chemical vapor deposition.
The range is 400 °. Thereafter, the element hole 28 is formed by anisotropic etching using chlorine as an etching agent.
a first amorphous silicon film 3 perpendicular to the side wall of b
2 is etched. Then, as a cleaning step, when immersed in a buffered hydrofluoric acid solution, the oxide film remaining on the buried bit line 16 can be removed.

In FIG. 6, a second conductive film 34a is deposited in and around the element hole 28b, but a polysilicon film is preferable. As a forming method, the temperature is set in a range of about 600 to 650 ° C. by low pressure chemical vapor deposition, and the thickness to be deposited is set in a range of about 500 to 1000 °. Next, ion implantation is performed on the second conductive film 34a. Arsenic ions or phosphorus ions are implanted, the implantation angle is set to 0 degree, the implantation dose is set to a range of about 1E15 to 5E15 atoms / cm ² , and the implantation energy Is in the range of about 50-100 keV. Since the implantation angle is 0 degree, ion implantation is performed on the third insulating film 26 and the second conductive film 34a at the bottom of the device hole 28b, but ion implantation is performed on the second conductive film 34a on the sidewall of the device hole 28b. Is not injected. Therefore, the second conductive film 34a can be divided into the N-type implanted region 34b and the remaining second conductive film 34a.

In FIG. 7, the second amorphous silicon film 3 is formed on the second conductive film 34a and in the element hole 28b.
6 is deposited. The formation method is such that the temperature is in the range of about 500-550 ° C. and the deposition thickness is in the range of about 1500-2000 ° C. by low pressure chemical vapor deposition. The element holes 28b are filled with the second amorphous silicon film 36. Then, a precise annealing (Anneal) step is performed, and the temperature is set in the range of about 600 to 800 ° C. and in the atmosphere filled with nitrogen for about 2 to 8 hours, whereby the second amorphous silicon film 3 is formed.
6, the second conductive film 34a, and the N-type implanted region 34b are recrystallized to become a single crystal silicon film.

In FIG. 8, ions are implanted into the single-crystal silicon film after the annealing process is completed. N-type ions are implanted, and a first deep doping region 36a and a first thin doping region 36b are sequentially formed. , A second heavily doped region 36d is formed. At this time, the single crystal region 36
N-type ions are not implanted in c, and are located between the first and second heavily doped regions 36a and 36d, and the first conductive film 20, the first and second heavily doped regions 36a and The vertical transfer transistor (Vertical Transfer Tran)
sistor) structure. The first heavily doped region 36a and the second heavily doped region 36d become source / drain regions, and
The conductive film 20 serves as a gate electrode, and the single crystal region 36c serves as a channel region. This single crystal region 36c
Is the length of the provided channel region, approximately
The range is 30 to 0.40 μm.

In FIG. 9, a third conductive film 38 is formed on the second heavily doped region 36d, preferably a polysilicon film. As a forming method, monosilane is used as a reactive gas by low pressure chemical vapor deposition, and at the same time, arsenic ions and phosphorus ions are doped to adjust the temperature to a range of about 600 to 650 ° C. and a deposition thickness of about 4,000 to 4,000.
The range is 8000 °. Then, after a photoresist film 40 is formed on the third conductive film 38, the photoresist film 40 is patterned, and the storage node (Stor
age Node) is determined.

In FIG. 9 and FIG. 10A, an etching process is performed using the photoresist film 40 as a mask.
By etching the third conductive film 38, a polysilicon storage node 42 is formed. The formation method is to use chlorine as an etching agent by anisotropic dry etching. Polysilicon storage node 4
2 and the second heavily doped region 36d serving as source / drain regions are interconnected. Then, the photoresist film 40 is removed. As the method, both plasma oxidation ashing and wet etching are performed. Next, a dielectric film 44 is formed on the polysilicon storage node 42 by using tantalum oxide (Tantalum O2).
xide) or silicon oxide / silicon nitride / silicon oxide film (Silicon Oxide / Silicon Nitride / Silicon Oxide)
xide = ONO). In this method, a silicon oxide film is first formed by heating, then a silicon nitride film is formed, and then a silicon oxide film is formed on the silicon nitride film by thermal oxidation.
The range is 0 to 100 °. Then, the fourth conductive film 46a is formed on the dielectric film 44, and is preferably a polysilicon film. The formation method is performed at a temperature in the range of about 600 to 650 ° C. by low pressure chemical vapor deposition, and a deposition thickness in the range of about 1000 to 3000 °.

In FIG. 10B, FIG.
Although a cross-sectional view rotated by 0 degrees is shown, a pattern of the fourth conductive film 46a is formed by photolithography and an etching process using chlorine as an etching agent to form an upper electrode 48 of the capacitor. The aforementioned polysilicon
The storage node 42, the dielectric film 44, and the upper electrode 48 form a capacitor structure. In this capacitor structure, polysilicon storage node 42 is interconnected with source / drain region 36d of the vertical transfer transistor structure.

Although the present invention has been disclosed above with reference to the preferred embodiments, it is not intended to limit the present invention, but, as will be understood by those skilled in the art, Since many changes in form and detail can be made, the scope of protection of the present invention is based on the matters described in the claims.

[0021]

With the structure described above, the structure of the dynamic random access memory according to the present invention and the method of manufacturing the same can reduce the element occupying area and improve the integration density by the vertically arranged capacitor structure. Very high industrial utility value.

[Brief description of the drawings]

FIG. 1 shows a trench 1 according to a DRAM manufacturing method of the present invention.
4 is a process cross-sectional view showing the formation of Step 4.

FIG. 2 shows a bit line 1 according to the DRAM manufacturing method of the present invention.
6 is a process cross-sectional view showing the formation of Step 6.

3A and 3B are process cross-sectional views showing the formation of a spacer 24, and FIG. 3B is a process cross-sectional view rotated 90 degrees with respect to FIG.

FIG. 4 is a process cross-sectional view showing the formation of the element hole 28b, and FIG. 4B is a process cross-sectional view rotated 90 degrees with respect to FIG.

FIG. 5 is a process sectional view showing the formation of the gate insulating film 30;

FIG. 6 is a process sectional view for explaining the ion implantation step.

FIG. 7 is a process cross-sectional view for explaining the annealing step.

FIG. 8 is a process sectional view showing the formation of a vertical transfer transistor by ion implantation.

FIG. 9 is a process cross-sectional view showing a preparation step for forming a storage node.

FIG. 10 is a process sectional view showing the formation of the capacitor structure, and FIG. 10B is a process sectional view obtained by rotating the capacitor structure by 90 degrees with respect to FIG.

[Explanation of symbols]

 Reference Signs List 10 semiconductor substrate 12 first insulating film 14 trench 16 bit line 18 second insulating film 20 first conductive film 22 thin silicon oxide film 24 spacer 26 third insulating film 28a photoresist 28b element hole 30 gate insulating film 32 first amorphous silicon Film 34a Second conductive film 34b N-type implanted region 36a First heavily doped region 36b First thinly doped region 36c Single crystal region 36d Second heavily doped region 40 Photoresist film 42 Polysilicon storage node 44 Dielectric film 46a Fourth conductive film

Claims (18)

[Claims] 1. A capacitor structure and a transistor structure are formed on a semiconductor substrate, wherein the capacitor structure is positioned perpendicular to the transistor structure. (A) A first structure is formed on the semiconductor substrate. Forming an insulating film; (b) forming a plurality of trenches on the first insulating film; (c) forming a conductive film in the trench; and (d) forming the conductive film. Partially etch the surface of
Forming a plurality of bit line structures by leaving the conductive film only in the trenches; and (e) depositing a second insulating film on the bit lines and the first insulating film, and planarizing the second insulating film. Making the second insulating film have a flat surface; (f) forming a first conductive film on the second insulating film; and (g) forming a thin film on the first conductive film. (H) forming a word line structure on the second insulating film by patterning the thin silicon oxide film and the first conductive film, and (i) forming a word line structure on the second insulating film. (J) a step of depositing a third insulating film on the word line and the second insulating film; and (k) a third step by lithography and etching. (1) forming a thin element hole by patterning an insulating film, the word line, the second insulating film, and the first insulating film, and sequentially etching until the bit line is exposed; Forming a gate insulating film on a portion of the side wall of the element hole where the word line is exposed; and (m) depositing and patterning a first amorphous silicon film in the element hole and forming the first amorphous silicon film. Etching the film to form an amorphous silicon sidewall on the sidewall of the device hole; (n) forming a second conductive film in the device hole; and (o) ion-implanting the third conductive film. The second conductive film on the insulating film is doped with ions, and the second conductive film on the bottom of the device hole is doped with ions. Doping and not doping ions into the second conductive film on the side wall of the device hole; and (p) depositing a second amorphous silicon film in the device hole and filling the device hole. And (q) forming the second amorphous silicon film, the second conductive film, and the first amorphous silicon film by annealing into a single-crystal silicon film, and performing the ion implantation by a plurality of times at different doses. A first heavily doped source / drain region, a first lightly doped source / drain region, a single crystal silicon film, a second heavily doped source / drain region in a device hole in order from bottom to top Is formed by interconnecting the single-crystal silicon film and the side surfaces of the word lines. Forming a transistor structure; (r) depositing a third conductive film on the second heavily doped source / drain region; and (s) patterning the third conductive film. Forming a storage node and disposing the storage node on the second heavily doped source / drain region; (t) depositing a dielectric film on the storage node; (u) A method of manufacturing a dynamic random access memory, comprising: depositing a fourth conductive film on the dielectric film; and (v) forming a capacitor structure by patterning the fourth conductive film. 2. A capacitor structure, a buried bit line structure, and a transistor structure are formed on a semiconductor substrate, wherein the capacitor structure is arranged vertically with respect to the transistor structure, and the buried bit line structure is also formed on the transistor structure. A occupied area on the semiconductor substrate is reduced by a dynamic random access memory structure configured to be vertically arranged with respect to the semiconductor substrate; (a) forming a first silicon oxide film on the semiconductor substrate; (B) forming a plurality of trenches on the first silicon oxide film; (c) forming a bit line structure in each of the trenches; (d) forming the bit line and the first Forming a second silicon oxide film on the silicon oxide film so that the bit line has a buried bit line structure; (E) flattening the second silicon oxide film to have a flat surface; and (f) forming a first polysilicon film on the second silicon oxide film. (G) forming a thin polysilicon oxide film on the first polysilicon film; and (h) patterning the thin polysilicon oxide film and the first polysilicon film to form the second polysilicon film. Forming a word line structure on a silicon oxide film; (i) forming a spacer made of metal silicide on a side surface of the word line, and removing the thin polysilicon oxide film; Depositing a third silicon oxide film on the formed word line and the second silicon oxide film; and (k) lithography and etching to form the third silicon oxide film. Silicon film, a substantially central portion of said word lines, said the second silicon oxide film, by etching until the said bit line surface of the first silicon oxide film in order to expose,
Forming a thin device hole; (l) forming a gate oxide film on a portion of the side wall of the device hole where the word line is exposed; and (m) forming a first amorphous silicon film in the device hole. Depositing and patterning, etching the first amorphous silicon film to form an amorphous silicon sidewall on the sidewall of the device hole; and (n) depositing a second polysilicon film in the device hole. Depositing; (o) performing ion implantation, setting the implantation angle to 0 degree, performing ion doping on the second polysilicon film on the third silicon oxide film, and forming the ion implantation on the bottom of the element hole. A certain second polysilicon film is doped with ions, and the second polysilicon film on the side wall of the device hole is formed. (P) depositing a second amorphous silicon film in the device hole and filling the device hole; and (q) annealing the second amorphous film by annealing. The silicon film, the second conductive film, and the first amorphous silicon film are formed as a single crystal silicon film, and the first film is formed in order from the bottom to the top in the element hole by ion implantation with different doses a plurality of times. Forming a first heavily doped source / drain region, a first lightly doped source / drain region, a single crystal silicon film, and a second heavily doped source / drain region. The source / drain region is located on the buried bit line structure, and Configuring a vertical transistor structure corresponding to the word line where the crystalline silicon film is exposed; and (r) depositing a third polysilicon film on the second heavily doped source / drain regions. (S) patterning the third polysilicon film to form a storage node and disposing the storage node on the second heavily doped source / drain region; t) depositing a dielectric film on the storage node; (u) depositing a fourth polysilicon film on the dielectric film; and (v) patterning the fourth polysilicon film. Forming an upper electrode, and forming a capacitor structure by the storage node, the dielectric film, and the upper electrode. Bei the method for manufacturing a dynamic random access memory. 3. The method of forming a third silicon oxide film according to claim 1, wherein said third silicon oxide film is formed by plasma-enhanced chemical vapor deposition using tetraethylorthosilicate (TEOS).
3. A method for manufacturing a dynamic random access memory according to claim 2, wherein the temperature is in the range of about 300 to 600 [deg.] C. and the deposition thickness is in the range of about 1000 to 2000 [deg.]. 4. A capacitor structure, a buried bit line structure, and a word line structure are formed on a semiconductor substrate, wherein the capacitor structure is vertically arranged above the word line structure, and the buried bit line structure also has the word line structure. A buried bit line structure vertically disposed below the structure, the buried bit line structure being disposed in a plurality of trenches in the first silicon oxide film; and a buried bit line structure formed on the first silicon oxide film. A silicon dioxide film; a word line structure formed on the second silicon oxide film; a spacer made of metal silicide formed on a side surface of the word line; The third silicon oxide film and the word line structure are formed so that the formed third silicon oxide film and the surface of the buried bit line are exposed. A central element portion, a thin element hole penetrating the first silicon oxide film, a gate oxide film covering the word line structure on the element hole side wall, and a single crystal silicon film completely filling the element hole. A channel region interconnected with the single-crystal silicon film in the single-crystal silicon film in the device hole; a first region disposed above the bit line in the single-crystal silicon film in the device hole; And a single-crystal silicon film in the device hole above the first heavily doped source / drain region and below the channel region. A first lightly doped source / drain region and a single crystal silicon film A second heavily doped source / drain region located above the channel region; and a second source / drain region above the second heavily doped source / drain region and with respect to the word line structure. A dynamic random access memory comprising a vertically arranged capacitor structure. 5. The word line structure has a thickness of about 30.
5. The structure of a dynamic random access memory according to claim 4, wherein said dynamic random access memory is in the range of 00-4000. 6. The structure of a dynamic random access memory according to claim 4, wherein said narrow element hole has a diameter of about 0.20 to 0.30 μm. 7. The gate oxide film has a thickness of about 50.
The structure of a dynamic random access memory according to claim 4, wherein the structure is in the range of ~ 75 °. 8. The fabrication of a dynamic random access memory according to claim 1, wherein said bit line is made of metal tungsten and has a thickness in a range of about 2000 to 3000 °. The method and its structure. 9. The method of manufacturing a dynamic random access memory according to claim 1, wherein said bit line is made of tungsten silicide and has a thickness in a range of about 2000 to 3000 °. The method and its structure. 10. In the step (f), the first conductive film or the first polysilicon film is formed of a polysilicon film, and a reaction is performed by reacting monosilane doped with arsenic or phosphorus by a simultaneous doping method. Gas, the temperature is in the range of about 600 to 650 ° C. by low pressure chemical vapor deposition, and the deposition thickness is about 300
3. The method of manufacturing a dynamic random access memory according to claim 1, wherein the range is 0 to 4000 degrees. 11. The method of manufacturing a dynamic random access memory according to claim 1, wherein in the step (h), the method of forming the word line is dry etching and using chlorine as an etching agent. Method. 12. In the step (k), the element hole has a diameter in a range of about 0.20 to 0.30 μm, and the formation step is performed by first converting the third insulating film to methane trifluoride. Etching the first conductive film using chlorine as an etching agent after etching as an etching agent, and finally etching the second insulating film and the first insulating film using methane trifluoride as an etching agent 3. The method for manufacturing a dynamic random access memory according to claim 1, wherein 13. In the step (l), the gate insulating film or the gate oxide film is formed at a temperature of about 900 to 9 in an atmosphere filled with oxygen.
In the range of 50 ° C. and the thickness formed is about 70-120 °
3. The method for manufacturing a dynamic random access memory according to claim 1 or 2, wherein: 14. In the step (m), the method for depositing the first amorphous silicon film and the method for forming the amorphous silicon side wall include: setting a temperature in a range of about 500 to 550 ° C. by low pressure chemical vapor deposition; 3. The method for manufacturing a dynamic random access memory according to claim 1, wherein dry etching is performed using chlorine as an etching agent after the deposition thickness is in the range of about 200 to 400 [deg.]. 15. In the step (n), the second conductive film or the second polysilicon film is formed of a polysilicon film, and a method for forming the second conductive film or the second polysilicon film is performed at a temperature of about 600 to 650 by low pressure chemical vapor deposition. 3. A method as claimed in claim 1 or 2, wherein the temperature is in the range of ℃ and the deposition thickness is in the range of about 500-1000 °. 16. The step (o) includes implanting arsenic ions or phosphorus ions, setting the implantation angle to 0 degree, setting the implantation dose in the range of 1E15 to 5E15 atoms / cm 2, and the implantation energy amount of about 50 to 100 ke.
3. The method for manufacturing a dynamic random access memory according to claim 1, wherein the range is V. 17. In the step (p), the method for forming the second amorphous silicon film includes the steps of: setting a temperature in a range of about 500 to 550 ° C. by low pressure chemical vapor deposition; 3. The method for manufacturing a dynamic random access memory according to claim 1, wherein the range is 2000 [deg.]. 18. In the step (q), the substance is recrystallized into single-crystal silicon by the annealing step, and the temperature is set to about 600 to 800 ° C.
The method according to claim 1 or 2, wherein the method is performed in an atmosphere filled with nitrogen for about 2 to 8 hours.