JPH1154363A - Laminated chip parts and their manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide laminated chip parts the capacitance value, of which can be adjusted finely by a simple method. SOLUTION: A conductor for capacitor D4 is divided into two patterns (conductors for capacitor) D4A and D4B. Since each pair of conductors for capacitors D1 and D4A, conductors D1 and D4B for capacitor, conductors for capacitor D4A and D5, conductors for capacitor D4B and D5, and conductors for capacitor D5 and D2 yields a capacitance value C0/2, a capacitance value C0 is obtained as a whole. Consequently, a capacitor having the capacitance value of 3C0 is obtained. The capacitance value of the capacitor can be adjusted, by changing the connection between the divided conductor patterns D4A and D4B and the conductor pattern D2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer chip component such as a multilayer chip capacitor and a multilayer chip EMI removal filter, and a method of manufacturing the same, and more specifically to an improvement with respect to a change in an obtained capacitance value. .

[0002]

2. Description of the Related Art An example of a laminated chip component, for example, a laminated LC composite component, has a laminated structure as shown in FIG. This background art is an example of a laminated structure of LC composite parts constituting a so-called T-type filter as shown in an equivalent circuit in FIG. As shown in the figure, a capacitor (capacitor) unit 10 is constituted by upper layers, and an inductor (coil) unit 12 is constituted by lower layers.
Is configured. The sheets A1 to A6 forming the capacitor section 10 are formed of, for example, a dielectric material, and the sheets A2 to A5 are formed with capacitor conductors. On the other hand, sheet B1 forming inductor section 12
To B8 are formed of, for example, a magnetic material (magnetic ferrite or the like), and conductors for inductors are formed on the sheets B2 to B7. A sheet 14 is provided between the capacitor section 10 and the inductor section 12 as a dissimilar joining material. Each of the above sheets is laminated, formed, crimped,
By firing and forming a terminal electrode for external extraction on the laminate, a laminated LC composite component is obtained.

[0003] Describing the capacitor section 10, the sheet A1 is a protective layer. One of the capacitor conductors D1 is formed on each of the sheets A2 and A4. These capacitor conductors D1 are exposed on the front and rear sides of the laminated sheet, and are connected to the GND electrodes (side terminals) 16 shown in FIG. 5B or 5C. The other capacitor conductor D2 is formed on each of the sheets A3 and A5. These capacitor conductors D2 are connected by via holes D3 (indicated by connection lines) near the center. That is, a window is provided in the central portion of the above-described capacitor conductor D1, and the via hole D passing through this portion is provided.
3 connects the upper and lower sides of the capacitor conductor D2. These capacitor conductors D1 and D2 are further laminated if necessary. Sheet A6 is also a protective layer. The capacitor C shown in the equivalent circuit of FIG. 5D is constituted by the capacitor conductors D1 and D2.

Next, the inductor portion 12 will be described. The sheet B1 is a protective layer. On the sheets B2 to B7, coil conductors are formed. A substantially U-shaped coil conductor E1, F1 is formed on the sheet B2. These coil conductors E1 and F1 are continuous in a substantially inverted S-shape.
The connection portion is connected to the capacitor section 10 via hole D3 penetrating through the sheets A6, 14, B1.

[0005] A substantially U-shaped coil conductor E2, F2 is formed on the sheet B3 so that the opening faces the opposite side. One end of each of the via holes G1, H1
Are connected to the coil conductors E1 and F1, respectively. Similarly, a substantially U-shaped coil conductor E3, F3 is formed on the next sheet B4 so that the opening faces. One end of each of the via holes G2, H2
Are connected to the coil conductors E2 and F2, respectively. The following sheet B5 is provided with coil conductors E2 and F2 similar to the sheet B3. Also,
Sheet B6 has the same coil conductor E as sheet B4.
3, F3 are formed. These inductor conductors E
2, F2 and E3, F3 are further multilayered if necessary. On the sheet B7, coil conductors E4 and F4, each of which has a substantially U-shaped pattern extended and exposed to the left and right sides, respectively, are formed. The hole connection is the same as that of the sheet. The lowermost sheet B8 is a protective layer.

[0006] Of the above-mentioned components, the coil conductors E1, E2, E3, E4 and the via holes G1, G2 which are continuous in a spiral form constitute a coil LA of an equivalent circuit shown in FIG. 5 (D). In addition, the coil conductors F1, F2, F3, F4 and the via holes H1, H2 that continue in a spiral form constitute the coil LB of the equivalent circuit shown in FIG. 5D. Then, the coil conductors E4 and F4 of the sheet B7 are left and right exposed from the laminated sheet, and are connected to the input / output electrodes 18 and 20 of FIGS. 5B and 5C, respectively.

The sheets on which the conductors for capacitors, conductors for inductors, and via holes are formed as described above are stacked in the order shown in FIG. Then, it is molded, pressed and fired to form a laminate. Then, electrodes 16, 18, and 20 are formed on the front, rear, left and right sides of the laminated body, and the rectangular parallelepiped laminated LC shown in FIGS.
Obtain composite parts. The external structure shown in FIGS. 5B and 5C is G
The difference is that the ND electrode 16 is located before and after the side surface of the laminated chip or on the entire periphery of the side surface. FIG. 6A shows FIG.
(B) and (C) show cross sections along the input / output electrode direction. As shown in the cross-sectional view, the pillar of the via hole D3 traverses substantially the center of the component, thereby connecting the inductor element and the capacitor element inside the component.

Here, focusing on the capacitor section 10,
The conductor pattern D1 connected to the GND electrode 16 and the conductor pattern D2 connected to the inductor portion 12 are alternately stacked. Here, the outermost (upper side in FIG. 6A) G
In general, a conductor pattern D1 connected to the ND electrode 16 is arranged, and a conductor pattern D2 connected to the inductor portion 12 is arranged on the opposite side (the lower side in FIG. 6A). .

This is for the following reason. If cracks are formed on the surface of the chip body and these cracks grow toward the inside, moisture and the like enter the inside of the component from this portion, and the moisture resistance and the pressure resistance (insulation) decrease. However, if the conductor pattern D1 is arranged outside, even if moisture enters from such a crack, the conductor pattern D1 will be G
Since it is connected to ND and has the GND potential, deterioration of moisture resistance and pressure resistance is reduced. On the other hand, on the opposite inductor side, when a conductor pattern having a potential different from that of the inductor conductor is arranged at a position closest to the inductor section 12 of the capacitor section 10, a potential difference between them becomes large. For this reason, considerable care must be taken to ensure the pressure resistance between them.
However, if the capacitor conductor D2 having the same potential as the inductor conductor is arranged, it is not necessary to consider such a pressure resistance. For the above reasons, the conductor pattern D1 connected to GND is arranged on the outside, and the conductor pattern D2 having the same potential is arranged on the inductor side.

In particular, as the miniaturization of component shapes progresses,
Since the ratio of the internal electrodes to the volume of the entire component increases, the reliability level of the entire component also deteriorates. But,
By using the above-described conductor arrangement for the capacitor portion, such a decrease in reliability can be prevented.

[0011]

However, the above background art has the following disadvantages. (1) As a method for obtaining the capacitance required for the laminated structure of the conductor patterns, there is a method of adjusting the number of layers of the conductor patterns D1 and D2. However, as mentioned above,
From the viewpoint of reliability, the conductor patterns on the outer side and the inductor side are limited. Therefore, even if the number of layers is adjusted,
The combination of the number of layers of two types of conductor patterns is 2 layers →
The number is limited to an even number such as 4 layers → 6 layers →. FIG.
(B) to (D) show the situation. First, FIG. 6 (B)
Is an example of a two-layer structure, and a capacitor having a capacitance C0 is constituted by the conductor patterns D1 and D2. FIG. 6C shows an example of a four-layer structure, in which a capacity of 3C0 is obtained as a whole. Fig. 6 (D) shows 6
In the example of the layer structure, a total capacity of 5C0 is obtained. Thus, only by adjusting the number of layers, 1C0, 3C0, 5
.., And only a stepwise capacitance value is obtained, and it is difficult to finely adjust the capacitance value.

(2) As another method of adjusting the capacitance value, there is a method of adjusting the sheet thickness. However, in this case, sheets having various thicknesses must be prepared. (3) As still another adjustment method, there is a method of adjusting with the area of the conductor pattern. However, in this case, several types of screens must be prepared for printing the conductor pattern, which is not a good idea from the viewpoint of productivity and the like.

The present invention focuses on the above points,
It is an object of the present invention to provide a multilayer chip component capable of obtaining a desired capacitance value by performing a minute capacitance value adjustment by a simple method and a method of manufacturing the same.

[0014]

In order to achieve the above object, a laminated chip component according to the present invention is characterized in that at least one of the capacitor conductors is divided into a plurality of pieces in a sheet, and at least one of the divided conductor patterns is formed. The one corresponding to the acquired capacity value is connected. One of the main modes includes a capacitor portion and an inductor portion, and at least one of the capacitor conductors having the same potential as the inductor portion is divided, and the corresponding divided conductor patterns are connected by holes. I do. Another form is GN
At least one of the capacitor conductors connected to D is divided, and the corresponding divided conductor patterns are connected to external electrodes.

In the method of manufacturing a chip component according to the present invention, at least one of the capacitor conductors is divided into a plurality of portions in a sheet; a hole for connecting one of the divided conductor patterns corresponding to the obtained capacitance value. Forming a pattern. Another manufacturing method includes a step of forming an external electrode for connecting one of the divided conductor patterns corresponding to the obtained capacitance value.

According to the present invention, the conductor pattern for the capacitor is divided and formed in the sheet. Then, the one corresponding to the obtained capacitance value is selected and connected by a hole or an external electrode. Thereby, depending on the presence or absence of connection, it is possible to acquire a capacitance value that cannot be obtained only by increasing or decreasing the number of stacked layers, and it is possible to finely adjust the acquired capacitance value,
The degree of freedom in design is improved. The above and other objects, features, and advantages of the present invention will be apparent from the following detailed description and the accompanying drawings.

[0017]

Embodiments of the present invention will be described below in detail. Note that the same reference numerals are used for components corresponding to the above-described background art.

(1) First Embodiment First, a first embodiment will be described with reference to FIGS. 1A, 2A, and 3. FIG. FIG. 2A shows a laminated structure of this embodiment, and FIG. 1A shows a cross section in the direction of input / output electrodes. This form also, as shown in FIG.
This is an example of an LC composite component constituting a so-called T-type filter. The basic laminated structure is the same as the background art.
That is, the capacitor section 30 is constituted by the upper layer, and the inductor section 32 is constituted by the lower layer. Between the capacitor part 30 and the inductor part 32,
A sheet 14 is provided as a dissimilar joining material.

Next, each part will be described in order. First,
Explaining from the capacitor section 30, the sheet A1 is a protective layer. One of the capacitor conductors D1 and D5 is formed on each of the sheets A2 and A4. These capacitor conductors D1 and D5 are exposed on the front and rear sides of the laminated sheet, and are connected to the GND electrodes 16 shown in FIGS. 5B and 5C. The other conductors D4 and D2 for capacitors are formed on the sheets A3 and A5, respectively. These capacitor conductors D2 and D4 are conductors connected to the inductor side by via holes.

In the present embodiment, the capacitor conductor D4 is 2
Are divided into two patterns D4A and D4B, and are connected to the capacitor conductor D2 by via holes D3A and D3B, respectively. That is, the left and right ends of the above-described capacitor conductor D5 are free, and the upper and lower portions of the capacitor conductors D2 and D4 are connected by via holes D3A and D3B passing through this portion. These capacitor conductors D4 and D5 are stacked in a larger number if necessary. Sheet A6 is a protective layer. The above components constitute the capacitor C shown in FIG.

Next, the inductor section 32 will be described. The basic configuration is the same as that of the background art described above. However, the difference is that sheets B9 and B10 on which conductive patterns similar to those of sheets B5 and B6 are formed are stacked.

Next, with reference to the cross section of FIG. 1A, the capacitance value obtainable in this embodiment will be described. According to this embodiment, first, the outermost (upper side in the figure) capacitor conductor D
1 and the next conductor D4A form a capacitor having a capacitance value C0 / 2. Similarly, the capacitor conductor D
1 and the next conductor D4B form a capacitor having a capacitance value C0 / 2. Next, the capacitor conductor D4
A and the conductor D5 form a capacitor having a capacitance value of C0 / 2, and the conductor D4B and the conductor D5 form a capacitance value of C0.
/ 2 capacitors are formed. Further, conductors D5 and D2
Thus, a capacitor having a capacitance value C0 is formed. Therefore, a capacitor having a capacitance value of 3C0 can be obtained as a whole. That is, in the present embodiment, although the second conductor pattern D4 is divided into D4A and D4B, both are connected to the conductor pattern D2 through via holes D3A and D3B, and as a result, FIG. It becomes the same.

In this embodiment, it is assumed that one of the via holes D3A and D3B, for example, the via hole D3A is not formed and only the via hole D3B is connected. Then, the divided conductor pattern D4A
And no capacitor is formed between the upper and lower conductors D1 and D5. Therefore, the capacitance value of the entire capacitor is 2C0. As described above, by dividing a part of the conductor pattern and adjusting the via hole connection, the capacitance value can be adjusted.

Next, examples of various capacitance values will be described with reference to FIG. First, FIG. 3A shows a case where a capacitance value C0 is obtained with a two-layer structure, which is the same as in the background art described above. next,
FIG. 3B shows a case where a capacitance value of 2C0 is obtained. This capacitance value cannot be obtained by the background art. However, according to the present embodiment, the four-layer structure and the divided conductor pattern D4
A, D4B, only one of the conductive patterns D
A capacitance value of 2C0 can be obtained by making a hole connection with 2. Next, FIG. 3C shows a case where a capacitance value 3C0 is obtained. This can be obtained by making the divided conductor patterns D4A and D4B both hole-connected to the conductor pattern D2. This is substantially equivalent to FIG.

Next, FIG. 3D shows a case where a capacitance value of 4C0 is obtained. This capacitance value cannot be obtained by the background art. However, according to the present embodiment, a capacitance value of 4C0 is obtained by forming a six-layer structure and not connecting any one of the divided conductor patterns D4A, D4B, D6A, and D6B, for example, D4A, to the conductor pattern D2 by hole. be able to. Next, FIG. 3E shows a case where a capacitance value of 5C0 is obtained. this is,
Each of the divided conductor patterns D4A, D4B, D6A, D6B can be obtained by making a hole connection with the conductor pattern D2. This is substantially equivalent to FIG.

As described above, according to the present embodiment, 1C0, 2C0, 3C0, 4C0, 5C
0, ... are obtained. That is, an even-numbered capacitance value such as 2C0, 4C0,... That cannot be obtained by the background art can be obtained. Moreover, such a capacitance value can be easily obtained only by the presence or absence of the hole connection without adjusting the sheet thickness and the electrode area.

(2) Second Embodiment Next, a second embodiment will be described with reference to FIGS. 1 (B), 2 (B), and 4. FIG. 2B shows a laminated structure of this embodiment, and FIG. 1B shows a cross section in the direction of input / output electrodes. This form is also an example of an LC composite component constituting a so-called T-type filter as shown in FIG. The basic laminated structure is the same as in the background art.
That is, the capacitor section 40 is constituted by the upper layer, and the inductor section 32 is constituted by the lower layer. Between the capacitor section 40 and the inductor section 32,
A sheet 14 is provided as a dissimilar joining material.

In this embodiment, the capacitor conductor D4 is divided into three, and is constituted by conductor patterns D4C, D4D and D4E. These divided conductor patterns D4
C, D4D and D4E are all conductors D5 for capacitors.
Are connected to the capacitor conductor D2 by via holes D3C, D3D, and D3E passing through. Other components are the same as in the first embodiment.

Next, referring to the cross section of FIG. 1B, the capacitance value that can be obtained in this embodiment will be described. According to this embodiment, first, a capacitor having a capacitance value C0 / 3 is formed by the outermost capacitor conductor D1 and the next conductor D4C. Similarly, a capacitor having a capacitance value C0 / 3 is formed by the capacitor conductor D1 and the next conductor D4D. Further, a capacitor having a capacitance value C0 / 3 is formed by the capacitor conductor D1 and the next conductor D4E. That is, the conductor D1 and the three-segmented conductors D4C, D4
Capacitors each having a capacitance value C0 / 3 are formed between the capacitors 4D and 4E.

Next, capacitor conductors D4C, D4D,
D4E and the conductor D5 form capacitors having a capacitance value C0 / 3, respectively. Further, a capacitor having a capacitance value C0 is formed by the conductors D5 and D2. Therefore,
As a whole, a capacitor having a capacitance value of 3C0 can be obtained. That is, in this embodiment, the second conductor pattern D4
Is divided into D4C, D4D, and D4E,
Since all of them are connected to the conductor pattern D2 through via holes D3C, D3D, and D3E, the result is the same as FIG. 6C.

By the way, in this embodiment, any one of the via holes D3C, D3D, and D3E, for example, the via holes D3C and D3D is not formed, and the via hole D3 is not formed.
Assume that only E is connected. Then, no capacitor is formed between the divided conductor patterns D4C and D4D and the upper and lower conductors D1 and D5. Therefore, the capacitance value of the entire capacitor is (1 + 2/3) C0. As described above, the capacitance value can be finely adjusted by further dividing the conductor pattern and adjusting the via hole connection.

Next, examples of various capacitance values will be described with reference to FIG. First, FIG. 4A shows a case where a capacitance value C0 is obtained with a two-layer structure, which is the same as in the background art described above. Next, FIG.
(B) is a case where a capacitance value (1 + 2/3) C0 is obtained. According to the present embodiment, the capacitance value (1) is obtained by forming a four-layer structure and connecting only one of the divided conductor patterns D4C, D4D, and D4E to the conductor pattern D2 through a hole.
+2/3) C0 can be obtained. Next, FIG. 4C shows a case where a capacitance value (2 + ／) C0 is obtained. This can be obtained by connecting any two of the divided conductor patterns D4C, D4D, D4E to the conductor pattern D2 by holes. FIG. 4D shows divided conductor patterns D4C and D4.
D and D4E are both connected to the conductor pattern D2, so that a capacitance value of 3C0 can be obtained. This is substantially equivalent to FIG.

Next, FIG. 4E shows the capacitance value (3 + 2/3) C0.
Is the case. According to the present embodiment, a six-layer structure is used, and only one of the divided conductor patterns D4C, D4D, and D4E, for example, D4E is connected to the conductor pattern D.
2 and the other divided conductor pattern D
By connecting all of 7C, D7D, and D7E to the conductor pattern D2, a capacitance value (3 + 2/3) C0 can be obtained. Next, FIG. 4F shows a case where a capacitance value (4 + ／) C0 is obtained. This can be obtained by making the divided conductor pattern D4D into a hole connection with the conductor pattern D2 as compared with FIG. 4E. In addition, when the divided conductor pattern D4C is further connected to the conductor pattern D2 by a hole, a capacitance value 5C0 can be obtained as shown in FIG. This is substantially equivalent to FIG.

As described above, according to the present embodiment, since the conductor pattern is divided into three, it is possible to adjust the capacitance value in units of 2C0 / 3 depending on the presence or absence of the hole connection of the one-divided conductor pattern. That is, 1C0, (1 + 2 /
3) C0, (2 + ／) C0, 3C0, (3 + ２)
The capacitance value can be finely changed step by step as C0, (4 + ／) C0, 5C0,..., And the degree of freedom in design increases.

(3) Third Embodiment Next, a third embodiment will be described with reference to FIG. In each of the embodiments described above, the conductor for the capacitor to be connected in the hole is divided, but in this embodiment, the conductor for the capacitor to be externally connected is divided. As shown in FIG. 7 (A), the sheet A2 of the capacitor section 50 has a laminated structure.
The capacitor conductor D1 of A4 is D1A, D1
B. The conductor D2 for the capacitor and the inductor portion to be connected in the hall are the same as in the background art.
FIG. 7B shows a stacked state. As shown in the figure, for example, when only the divided conductor pattern D1B is connected by the GND electrode 16B, C0 / 2 is formed between the divided conductor pattern D1B and the adjacent conductor pattern D2, and thus 3C0 is formed as a whole. / 2 can be obtained. According to this embodiment, since the capacitance value can be adjusted depending on whether or not the external electrode is connected, there is an advantage that the adjustment operation can be performed after the chip is formed.

The present invention has many embodiments and can be variously modified based on the above disclosure.
For example, the following is also included. (1) The pattern shape and the number of layers of the conductors in the capacitor portion and the inductor portion may be appropriately changed as necessary. For example, in the above-described embodiment, the capacitor conductor pattern D2 closest to the inductor portion is not divided, but may be divided. When the conductor pattern D2 is divided, the connection with the inductor portion is made by a plurality of holes.
Also, the number of divisions of the conductor pattern may be appropriately set as needed. The division area does not need to be equally divided, and may be appropriately set according to the capacitance value to be adjusted.

(2) In the above embodiment, the present invention is applied to a multilayer chip EMI removal filter, but can be applied to various multilayer chip components. Also, the configuration of the filter
The present invention is applicable to various types such as a π-type filter and a double π-type filter other than the T-type filter.

(3) The first and second embodiments may be combined with the third embodiment. In this case, the two opposing capacitor conductors may be divided in the same direction or in orthogonal directions. In this case, more various capacitance values can be obtained.

[0039]

As described above, according to the present invention,
The following effects are obtained. (1) Since the capacitor conductor was divided and formed,
The obtained capacitance value can be easily and finely adjusted only by the presence or absence of the hole connection and the external electrode. (2) Even in a composite component including an inductor, the capacitance value can be satisfactorily adjusted without lowering the reliability.

[Brief description of the drawings]

FIG. 1 is a diagram showing a cross-sectional configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a laminated structure of the embodiment.

FIG. 3 is a diagram showing an example of various capacitance values according to the first embodiment.

FIG. 4 is a diagram showing an example of various capacitance values according to the second embodiment.

FIG. 5 is a diagram showing an example of a laminated chip component of the background art.

FIG. 6 is a diagram showing a change in capacitance value according to the cross-sectional configuration and the number of layers of the background art.

FIG. 7 is a diagram showing a third embodiment.

[Explanation of symbols]

10, 30, 40, 50: Capacitor section 12, 32: Inductor section 14: Dissimilar bonding sheet 16: GND electrode 18, 20: Input / output electrode A1 to A6, B1 to B10: Sheet D1, D2, D4, D5: Capacitor Conductors D3, D3A to D3E, G1, G2, H1, H2: Via holes E1 to E4, F1 to F4: Conductors for inductors D1A, D1B, D4A to D4E, D6A, D6B, D
7C-D7E: divided conductor pattern

Claims (5)

[Claims] 1. A laminated chip component in which sheets having capacitor conductors formed thereon are laminated, wherein at least one of the capacitor conductors is divided into a plurality of pieces in the sheet, and the obtained capacitance of the divided conductor pattern is obtained. A multilayer chip component characterized by connecting components corresponding to values. 2. A semiconductor device according to claim 1, further comprising a capacitor portion and an inductor portion, wherein at least one of the capacitor conductors having the same potential as the inductor portion is divided, and the corresponding divided conductor patterns are connected by holes. 2. The laminated chip component according to 1. 3. The method according to claim 1, wherein at least one of the capacitor conductors connected to GND is divided and the corresponding divided conductor patterns are connected to external electrodes.
Or the laminated chip component according to 2. 4. A method of manufacturing a laminated chip component in which a sheet on which a conductor is formed is laminated to form a capacitor portion and an inductor portion, wherein at least one of the capacitor conductors is divided into a plurality of pieces in the sheet; Forming a hole pattern that connects the divided conductor patterns corresponding to the obtained capacitance value. 5. A method of manufacturing a laminated chip component in which a capacitor portion is formed by laminating sheets formed with conductors, wherein at least one of the capacitor conductors is divided into a plurality of portions in the sheet; Forming an external electrode for connecting a pattern corresponding to the obtained capacitance value of the patterns.