JPH1152546A - Pattern inspection apparatus and pattern inspection method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the inspection of patterns with simple constitution despite of intricate shapes added with specific patterns by providing the apparatus with graphic addition circuits for adding specific pattern data to the corner parts of the patterns for the design data of the patterns. SOLUTION: The design data of the patterns is sent from a magnetic disk device 9 through a control computer 10 to a bit pattern generating circuit 11. The data developed to graphics in the bit pattern generating circuit 11 is subjected to the detection of the corner parts of the patterns by the graphic addition circuit 120, by which the pattern data corresponding to a mask formed with the patterns for correcting light proximity effect is generated and the data added with such specific patterns to the corner parts is sent to a data comparator circuit 8. Design pattern image data is formed in the data comparator circuit 8 and the point where the design data and the observed data do not coincide is decided as a defect.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern inspection apparatus and a pattern inspection method for inspecting a pattern such as a photomask used when manufacturing a semiconductor device.
In particular, the present invention relates to a pattern inspection apparatus and a pattern inspection method for inspecting a pattern having a complicated shape.

[0002]

2. Description of the Related Art One of the major causes of a decrease in yield in the manufacture of large-scale integrated circuits (LSI) is a defect occurring in a photomask or a reticle used when manufacturing a device by photolithography. . In order to improve the yield, devices for inspecting such defects have been developed and put into practical use. Conventional mask defect inspection apparatuses are roughly classified into the following two methods.

(A) One is to examine an optical image of a pattern of two chips in which the same pattern is drawn on one mask, and detect pattern data by a predetermined optical detecting means and a predetermined light receiving element. This is a method called a die-to-die method in which the presence or absence of a defect is checked by comparing the two pattern data obtained by a predetermined data comparison processing means and checking the difference.

(B) In another method, an image of a pattern on a mask is detected by an optical detecting means and pattern image data is obtained by a predetermined light receiving element, while design data of the pattern is processed by a predetermined data processing means. To create design pattern data for comparison and reference, and process the pattern image data and the design pattern data by a predetermined comparison processing means to check for the presence or absence of a defect.
This is a method called an “e-to-database” method or “design data comparison method”.

In the die-to-die method, two chips on which the same pattern is drawn are compared with each other.
If there is a common defect, that is, the same defect at the same location,
There is a disadvantage that the defect cannot be detected. On the other hand, in the case of the design data comparison method (die-to-database method), such a problem does not occur because the absolute comparison with the design data of the pattern is performed. For this reason, there is a tendency that an inspection using a design data comparison method is required for a mask having higher accuracy. In this design data comparison method, a highly reliable inspection can be performed as described above, but a high-speed digital processing technique for processing design data at high speed is required. In other words, fine patterns are formed on the mask at a high density, and the amount of pattern data is enormous.

As an apparatus for performing an inspection using the design data comparison method, for example, literatures, electronic materials, September 1983,
Apparatus shown on page 47, or Japanese Patent Publication No. 1-4048
No. 9 discloses a technique. 10 and 11 show the inspection method and the configuration of the apparatus. The inspection enlarges a mask pattern image on the inspection target (mask) 2 using an optical system or the like. That is, as shown in FIG. 10, the measurement is performed while scanning a thin strip-shaped portion having a width of about several hundred μm on the mask 2 by continuously moving a table on which the mask 2 is mounted. The inspection method will be briefly described with reference to the schematic configuration diagram of FIG. A mask 2 is placed on an XY table 1 and a pattern is irradiated by a suitable light source 3. A pattern image is formed on the photodiode array 5 using the objective lens 4, and the pattern image is observed by the sensor circuit 6. This observation data is A / D converted and sent to the data comparison circuit 8 together with the position data from the position circuit 7. On the other hand, the pattern design data is sent from the magnetic disk device 9 to the bit pattern generation circuit (bit expansion circuit) 11 through the control computer 10, and is sent to the data comparison circuit 8 as data expanded into a figure. In the preceding stage of the data comparison circuit 8, appropriate data processing is performed on the developed graphic data to create design pattern image data corresponding to the optical point spread function. This is because the observation data is in a state where the filter is actuated due to the resolution characteristics of the objective lens 4 and the aperture effect of the photodiode array 5, whereas the original design data does not include this information. It is. That is, by performing data processing, it is possible to obtain design pattern image data that matches the observation data. The two are compared at a subsequent stage of the data comparison circuit 8 according to a predetermined algorithm, and a portion where the design data and the observed data do not match is determined as a defect. Note that, in the above method, as shown in FIG. 10, while continuously moving the XY table on which the inspection object (mask) 2 is mounted on average, the above series of data processing is performed almost in real time to inspect the entire mask. .

As shown in the examples shown in FIGS. 10 and 11, the handling of design data in the conventional design data system is to process data compressed and described by a certain rule using a digital circuit. It is developed into binary or multi-valued digital data to create reference data for comparison. This data processing is usually performed in real time because the amount of expanded data is enormous. That is, the mask pattern is cut out at an appropriate width, the data of the pulse pattern image of that width is obtained, and the corresponding design data is sequentially developed to create reference data.
The pattern image data is compared with the reference data.

On the other hand, as the pattern becomes finer,
In order to improve the resolution performance of optical lithography, photomasks to which optical proximity effect correction patterns 42 to 45 are added as shown in FIG. 12 have been frequently used (for example, R, Pfour). (R. Pforr,
et. al. ) By S.P.I.E. (S
PIE) 2440, pp. 150-170, 1995 and the like.

[0009]

In the above-described design data comparison method, since a predetermined processing is performed in real time, even if a high-speed digital processing circuit is used as the data processing circuit, the data processing circuit naturally has a limit depending on the scale of data to be handled. There is.

In particular, when inspecting a mask to which the optical proximity effect correction patterns 42 to 45 are added as shown in FIG. 12 using an existing inspection apparatus based on a design data comparison method, the amount of design data increases. The original graphic pattern 31 indicated by the symbol a has the number of rectangles 1, whereas the optical proximity effect correction patterns 42 to 45 have the rectangles b, c, d, e, e, f, t, j, and d.
There are nine rectangular patterns with eight of them added, and the data amount is nine times as large. For this reason, the mask to which the optical proximity effect correction patterns 42 to 45 are added takes a long time to process data, causing a problem that the processing capability is exceeded. That is, since the optical proximity effect correction patterns 42 to 45 are added, there is a problem that the processing time of the data processing circuit described above increases and real-time processing cannot be satisfied.

In view of the above problems, the present invention increases the memory capacity in a data processing circuit and the complexity of hardware even in a special and complicated shape to which a specific pattern such as a pattern for optical proximity effect correction is added. It is an object of the present invention to provide a pattern inspection apparatus capable of inspecting a pattern with a simple configuration without any modification.

Another object of the present invention is to provide a pattern inspection apparatus capable of inspecting a pattern in a short time and accurately even if the pattern has a complicated shape because a specific pattern is added.

Still another object of the present invention is to provide a pattern inspection method capable of accurately measuring an inspection object having a complicated pattern to which a specific pattern is added in a short time.

Still another object of the present invention is to provide a pattern inspection method capable of easily and quickly performing high-precision inspection even when the size and shape of a specific pattern are different.

[0015]

In order to achieve the above object, the present invention irradiates a pattern-formed inspection object with light having a predetermined wavelength and transmits or reflects the transmitted light or reflected light to a predetermined optical system and a light receiving element. In addition to obtaining observation data corresponding to the pattern image by detecting the pattern data, the design data of the pattern substantially corresponding to the pattern is input, and binary or multi-valued design pattern image data is created based on the pattern design data. This is a design data comparison type pattern inspection system that performs pattern defect inspection by comparing design pattern image data with observation data, and automatically creates pattern pattern image data required for comparison. Diagram of adding specific pattern data to corners of detected pattern data A first feature in that an additional circuit is a pattern inspection apparatus characterized by at least.

According to the configuration of the first aspect of the present invention,
As design pattern data to be inputted, design data to which the specific pattern is not added may be inputted, so that the amount of design data does not increase. That is, even with a mask on which a specific pattern such as a pattern for optical proximity effect correction is formed, the data to be handled may be the same as the conventional one. No problem occurs. Also, when creating design pattern image data from input design data, it automatically detects the corners of the pattern and adds specific pattern data to the corners of the detected pattern data. Is equivalent to using pattern data corresponding to the pattern formed in the mask pattern. Therefore, the inspection cannot be performed because the input data is different from the actual mask pattern, and the number of pseudo defects does not increase, so that the same inspection as that of the mask on which the normal pattern is formed can be performed.

More specifically, the figure adding circuit according to the first feature of the present invention includes a corner pattern detecting window circuit,
The decorative pattern data generating circuit connected to the output terminal of the corner pattern detecting window circuit, and the graphic synthesizing circuit connected to both the input terminal of the corner pattern detecting circuit and the output terminal of the decorative pattern data generating circuit are included. It is desirable. Logical OR (O
R) By performing the operation, the original graphic pattern to which the specific pattern is not added and the additional bit pattern corresponding to the specific pattern are combined.

A second feature of the present invention relates to a method of inspecting a pattern defect to be inspected such as a semiconductor lithography mask having a circuit pattern formed by adding a specific pattern to a corner portion. That is, the second feature of the present invention is to irradiate the inspection object with light of a predetermined wavelength, detect the transmitted light or the reflected light with a predetermined optical system and a light receiving element, and obtain observation data corresponding to the pattern image. Automatically detects corners where specific patterns should be added from design data to which specific patterns have not been added, and adds specific pattern data to the detected corners. This is a pattern inspection method that creates design pattern image data and compares the design pattern image data with acquired observation data. Here, as the specific pattern added to the corner portion, an optical proximity effect correction pattern or the like can be used.

According to the second feature of the present invention, since design data to which a specific pattern is not added is input as design pattern data to be input, the amount of data to be processed may be small. That is, even with a mask to which a specific pattern such as a pattern for optical proximity effect correction is added,
Since the data to be handled may be the same as when there is no specific pattern, there is no problem that the data processing time is too long due to an increase in the design data amount and the processing capacity is exceeded.
Also, when creating design pattern image data from the input design data, the corners of the pattern are automatically detected, and specific pattern data is added to the corners of the detected pattern data. Is equivalent to using pattern data corresponding to the pattern formed in the mask pattern. Therefore, the inspection cannot be performed because the input data is different from the actual mask pattern, and the number of pseudo defects does not increase, so that the same inspection as that of the mask on which the normal pattern is formed can be performed.

In the second aspect of the present invention, it is preferable that the shape and size of a specific pattern added to a corner portion can be changed by an external setting. For this external setting, a plurality of figure adding circuits for adding specific pattern data to the corners of the pattern data are prepared, and a desired figure is added from among them so as to match the shape and size of the specific pattern. What is necessary is just to select a circuit.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic diagram showing an outline of a pattern inspection apparatus according to an embodiment of the present invention. The pattern inspection apparatus according to the present invention relates to an improvement of the conventional pattern inspection apparatus shown in FIG. 11, in which a figure adding circuit 120 is inserted between a bit pattern generation circuit (bit expansion circuit) 11 and a data comparison circuit 8. It is characterized by.

That is, the pattern inspection apparatus according to the present invention detects an XY table 1 on which a mask 2 to be inspected is placed, a light source 3 for irradiating inspection light to the XY table 1, and a photodiode array or the like for detecting this. The vessel 5 is the basis of the optical inspection means. Then, a mask 2 is placed on the XY table 1.
And the pattern of the mask 2 is irradiated by the light source 3. The light is condensed by the condensing lens 13 and is irradiated on the mask 2. The light that has passed through the mask forms a pattern image on the photodiode array 5 using the objective lens 4 arranged below the XY table 1. The position of the objective lens 4 is adjusted by the piezo element 70 and the focal length is controlled. The movement of the mask 1 is measured by a laser length measuring system 71.
The output of the laser length measuring system 71 is input to a position circuit 7 connected to the laser length measuring system.

The photodiode array 5 is connected to a sensor circuit 6, and the sensor circuit 6 is connected to a data comparison circuit 8. The data comparison circuit 8 is connected to a position circuit 7. The pattern image formed on the photodiode array is observed as a pattern image by the sensor circuit 6, and outputs observation data. This observation data is A / D converted,
Data comparison circuit 8 together with the position data from position circuit 7
Sent to

The pattern inspection apparatus according to the embodiment of the present invention further has a control computer (CPU) 10. The control computer 10 is connected to the magnetic disk device 9, the magnetic tape device 91, the floppy disk device 9 via the bus 61.
2. A bit pattern generation circuit (bit expansion circuit) 11 is connected. Further, the control computer 10 has an autoloader control circuit 81 and a table control circuit 8 via a bus 62.
2, auto focus control circuit 83, data comparison circuit 8, position circuit 7, console 93, pattern monitor 9
4. A magnetic card device 95, a mini printer 96 and the like are connected. The above-described graphic adding circuit 120 is connected between the bit pattern generating circuit 11 and the data comparing circuit 8.

The pattern design data is sent from the magnetic disk drive 9 to the bit pattern generation circuit 11 through the control computer 10. The data developed into the graphic by the bit pattern generating circuit 11 is generated by the graphic adding circuit 120 to generate pattern data corresponding to the mask on which the pattern for optical proximity effect correction is formed, and the data to which the specific pattern is added is compared with the data. It is sent to the circuit 8. In the preceding stage of the data comparison circuit 8, appropriate data processing is performed on the developed graphic data to create design pattern image data corresponding to the optical point spread function. This is because the observation data is in a state where the filter is actuated due to the resolution characteristics of the objective lens 4 and the aperture effect of the photodiode array 5, whereas the original design data does not include this information. It is. In other words, by performing data processing, it is possible to obtain design pattern image data that matches the observation data. The two are compared at a subsequent stage of the data comparison circuit 8 according to a predetermined algorithm, and a portion where the design data and the observed data do not match is determined as a defect. Note that, in the pattern inspection apparatus according to the embodiment of the present invention, the X on which the inspection target (mask) 2 is mounted is set.
While continuously moving the Y table 1 in a plane by the table control circuit 82, the above series of data processing is performed almost in real time, and the entire mask is inspected.

The details of the figure adding circuit will be described below. As shown in FIG. 2, the figure adding circuit of the present invention includes a corner pattern detecting window circuit 21, a decorative pattern data generating circuit 22 for adding a corner portion, and a figure synthesizing circuit 23.

Corner pattern detection window circuit 21
Is to determine whether or not a pattern to which a decorative pattern should be added to a corner is included by operating a corner pattern detection plate having a predetermined bit configuration every time the original figure pattern data C serving as a reference for inspection is sequentially input. Is detected. When a pattern to which a decorative pattern is to be added is detected, the corner pattern detection window circuit 21 sets a flag I indicating that the feature coincides, together with a graphic code H indicating the graphic whose coincidence has been detected. The decoration pattern data generation circuit 22
When the flag I of the corner pattern detection window circuit 21 is set, the corner pattern detection window circuit 2
1 generates a decorative pattern J corresponding to the graphic code H output. Note that these graphic codes H are distinguished by the direction of the corner of the pattern, the type of unevenness, and the like. The decoration pattern data generation circuit 22 sets the data “1” at the position of the bit to which the decoration pattern is to be added in the original graphic pattern before the decoration pattern addition processing, and sets the other data as the data “0”. Generate.

FIG. 3A shows an original figure pattern 31.
FIGS. 3B to 3E show corner patterns detected by the corner pattern detection window circuit 21 with respect to the original graphic pattern 31. FIG. 3 (f) to 3 (i)
5 illustrates decorative patterns 32-35 corresponding to the original graphic pattern 31 generated by the decorative pattern data generating circuit 22. The graphic synthesizing circuit 23 includes an original graphic pattern 31 and additional bit patterns (decorative patterns) 32 to 3.
5 and a logical sum (OR) operation for each bit. That is, the decorative patterns 32 to 35 are obtained by inverting only the bits of the corner pattern shown in FIGS. 3B to 3E whose bits are “1” into black and white (inverting data “0” and “1”). It almost corresponds. The processing result of the pattern shown in FIG. 3 is as shown in FIG.

According to the concept shown in the block diagram of FIG.
FIG. 5 shows an example of a specific circuit configuration for performing 1-bit decoration addition processing, and FIG. 6 shows an operation example thereof. Here, "n-bit decoration" is a value obtained by dividing the length from the corner end of the original figure pattern 31 to the end of the decoration pattern 32, 33, 34, 35 by the figure bit (minimum unit) as shown in FIG. Is defined as As shown in FIG. 5, the figure adding circuit according to the embodiment of the present invention includes a ROM (read only memory) 51.
And a latch 52 connected to the address side of the ROM 51.
a, 52b, 52c, latches 52d, 52e connected to the data side of the ROM 51, and OR gates 54a-54.
c, 55a to 55c, and OR gates 56a to 56c connected to the output sides of the OR gates 55a to 55c. OR gate 55 is connected to OR gates 56a to 56c.
The output of the latch 52c is input together with the outputs of a to 55c. The output of the latch 52c corresponds to the original figure pattern.
Further, a shift clock oscillator 53 is connected to the latches 52a to 52e.

In FIG. 5, the ROM 51 and the latches 52a to 52a.
The corner pattern detection window circuit 21 is constituted by 52c, the decorative pattern data generation circuit 22 is constituted by the ROM 51, latches 52d and 52e, and the OR gates 54a to 54c and 55a to 55c, and the OR gates 56a to 56c.
Constitutes the graphic synthesizing circuit 23. The corner pattern detection window circuit 21 has a function of detecting two-dimensional pattern matching, and any means can be applied to the configuration method. Here, an example using the ROM 51 will be described. When the ROM 51 is used, both the corner pattern detection function and the masking pattern data generation function can be realized at one time. The required capacity of the ROM 51 is determined by the number of bits for detecting a corner pattern. That is, 3
In order to detect a pattern with × 3 bits, a ROM having a 9-bit address line and a 9-bit data output is required. When a 4 × 4 bit window is configured, 16-bit data output is required. When the size (the number of bits) of the corner pattern is represented by the number of bits on the corner side, the corner pattern detection window according to the embodiment of the present invention has n + 2 bits as shown in FIG. Is required. FIG. 3 shows an example of 4 × for 2 bit decoration addition processing.
4 shows a 4-bit window. The circuit shown in FIG. 5 is a case of 1-bit decoration addition processing, and is a ROM having 3 × 3 bits = 9 bits of input / output. The state of data written to the ROM 51 used in the configuration of FIG.
Shown in In the original figure pattern, white is determined as “0” and black is determined as “1”. When a pattern for scanning detection is supplied to the address lines A0 to A8 of the ROM 51, the address in the ROM 51 is uniquely determined by the input pattern. When a predetermined bit configuration is obtained, decorative pattern data corresponding to the figure pattern is written in advance at the address. That is, the design data includes information on whether or not to perform the decoration process. If the input pattern does not correspond to the pattern to be decorated, all bits of the decoration pattern data are “0”. In FIG. 5, the stripe data of the original figure pattern is
According to the third clock, the data is latched by the data latch 52a. A latch 52 is connected to an address line of the ROM 51.
a to 52c are connected, and 3 × 3 bit 2
Can test dimensional patterns. Therefore, 3
Scanning is performed while shifting the pattern of × 3 bits one bit at a time. Then, the decoration pattern data as a result of the detection is obtained at a time of 3 × 3 bits, but is temporarily stored in the delay latches 52d and 52e three bits at a time in order to match the timing with the original figure pattern by pipeline processing. And an OR gate 56 having a function of a graphic synthesis circuit.
a to 56c. That is, the mask pattern corresponding to the bits input to the address lines A0 to A2 of the ROM 51 is output from the data lines D6 to D8, and the OR gate 5 serving as the graphic synthesizing circuit 23 within the same clock cycle.
6a to 56c. Also, address lines A3 to A5
Are output from the data lines D3 to D5, delayed by one stage of clock by the delay latch 52e, and then input to the OR gates 56a to 56c. The mask patterns corresponding to the bits input to the address lines A6 to A8 are output from the data lines D0 to D2, and after being delayed by two clocks by the delay latches 52d and 52e, input to the OR gates 56a to 56c. I do. In the OR gates 54a to 54c and 55a to 55c, the corner detection window circuit 21 performs a decoration adding process on the separately detected adjacent bits during scanning. FIG.
Then, a 3 × 3 bit corner pattern is detected and 1
Although the example in which the bit decoration addition process is performed has been described, in the case of a process with a plurality of bits, a ROM having a predetermined number of bits for address lines and data lines is prepared, and the number of stages for delay latching is also arranged in a predetermined number. Processing can be performed in the same manner. Also, a plurality of circuits having the same circuit configuration as that shown in FIG. 5 are provided so as to be able to cope with a plurality of additional patterns, and a desired circuit can be selected from the plurality of circuits so that additional patterns having different sizes and shapes of additional patterns are provided. It is also possible to arbitrarily select a pattern and correspond to a wide range of patterns.

As described above, according to the present embodiment, as the design pattern data to be input, only the design data to which the specific pattern such as the decoration pattern is not added is input, and the corner pattern detection window circuit 21 and the decoration pattern The figure adding circuit 12 including the pattern data generating circuit 22 and the figure synthesizing circuit 23 can generate pattern data corresponding to a mask on which a pattern for optical proximity effect correction is formed. In other words, even with a mask on which a pattern for optical proximity effect correction is formed, the data to be handled may be the same as the conventional one, so that there is a problem that the data processing takes too much time and exceeds the processing capability due to an increase in the design data amount. Absent.

The present invention is not limited to the above-described embodiment, but can be implemented with various modifications without departing from the scope of the invention. In the above-described embodiment, the logical sum processing is performed as the graphic synthesizing circuit. However, any circuit may be used as long as the decorative pattern is added through appropriate processing from the reference pattern data. Also, if a plurality of figure adding circuits are prepared as described above and a desired figure adding circuit is selected from among them, the sizes and shapes differ as shown in FIGS. 9A and 9B. It is also possible to arbitrarily select the additional pattern.

[0033]

According to the present invention, even with a mask on which a pattern for correcting the optical proximity effect is formed, the data to be handled can be the same as the conventional one, so that it takes too much data processing time due to an increase in the amount of design data. There is no problem of exceeding the processing capacity. In addition, an inspection equivalent to a mask on which a normal pattern is formed can be performed without increasing pseudo defects. Therefore, it becomes easy to put the mask having the optical proximity effect correction pattern formed into practical use. As a result, it greatly contributes to improving the performance of optical lithography.
As a result, the effects of the present invention are extremely large in the semiconductor manufacturing field.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing an outline of a pattern inspection apparatus according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a figure adding circuit according to the embodiment of the present invention;

FIG. 3 is a conceptual diagram for explaining the principle of the present invention.

FIG. 4 is a conceptual diagram showing a processing result (pattern) according to the embodiment of the present invention.

FIG. 5 is a circuit diagram showing a specific configuration example of the graphic adding circuit according to the embodiment of the present invention;

FIG. 6 is a conceptual diagram illustrating the operation of FIG.

FIG. 7 is a diagram illustrating the definition of “n-bit decoration”.

FIG. 8 is a conceptual diagram showing a state of data written in a ROM used in the embodiment of the present invention.

FIG. 9 is a diagram illustrating an example of a case where additional patterns having different sizes are used in the present invention.

FIG. 10 is a diagram illustrating movement (scanning) of a mask in the pattern inspection apparatus.

FIG. 11 is a conceptual diagram showing a schematic configuration of a conventional pattern inspection apparatus.

FIG. 12 is a diagram illustrating an example of a photomask pattern to which a proximity effect correction pattern is added.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 XY table 2 Inspection object (mask) 3 Light source 4 Objective lens 5 Photodiode array 6 Sensor circuit 7 Position circuit 8 Data comparison circuit 9 Magnetic disk drive 10 Control computer (CPU) 11 Bit pattern generation circuit (Bit development circuit) 13 Collection Optical lens 21 Corner pattern detection window circuit 22 Decorative pattern data generation circuit 23 Graphic composition circuit 31 Original graphic pattern 32 to 35 Decorative pattern 42 to 45 Optical proximity correction pattern 61, 62 Bus 70 Piezo element 71 Laser length measurement system 81 Autoloader Control circuit 82 Table control circuit 83 Auto focus control circuit 91 Magnetic tape device 92 Floppy disk device 93 Console (CRT) 94 Pattern monitor 95 Magnetic card device 96 Mini printer 120 With graphics Additional circuit

Claims (5)

[Claims] An object to be inspected is irradiated with light having a predetermined wavelength, transmitted light or reflected light is detected to obtain observation data corresponding to a pattern image of the object to be inspected, and a design pattern substantially corresponding to the pattern is obtained. In a pattern inspection apparatus that creates image data and inspects the pattern by comparing the design pattern image data with the observation data, a pattern corner is automatically detected and detected for the pattern design data. A pattern inspection apparatus comprising at least a figure adding circuit for adding specific pattern data to a corner portion. 2. The figure adding circuit includes a corner pattern detection window circuit, a decoration pattern data generation circuit connected to an output terminal of the corner pattern detection window circuit, an input terminal of the corner pattern detection circuit, and decoration pattern data. 2. The pattern inspection apparatus according to claim 1, further comprising a graphic synthesizing circuit connected to an output terminal of the generating circuit. 3. An inspection object is irradiated with light of a predetermined wavelength, and the transmitted light or the reflected light is detected to obtain observation data corresponding to the pattern image of the inspection object, and to specify from the design data of the corresponding pattern. Automatically detecting a corner to which the pattern is to be added, adding specific pattern data to the detected corner, generating design pattern image data from the design data to which the specific pattern is added, A pattern inspection method characterized by inspecting a pattern by comparing data with the observation data. 4. The pattern inspection method according to claim 3, wherein the specific pattern is an optical proximity effect correction pattern. 5. The shape and size of the specific pattern,
5. The method according to claim 3, wherein the setting can be changed by an external setting.
The pattern inspection method described.