JPH1152025A - Vodule for memory module connection test - Google Patents

Abstract

PROBLEM TO BE SOLVED: To connect a memory control circuit and a memory module socket to each other reliably by providing a plurality of pins with data input terminals, address input terminals, and a power source terminal and a circuit connected to the input terminals of the pins except the power source terminal so as to generate a signal according to a predetermined data pattern to each of the pins except the power source terminal. SOLUTION: A module 101 for test is used for testing the connection between a substrate and a socket. The module 101 is constituted of 20 pins, and terminals OE. WE, CAS, RAS, A0-A5, and D0-D7 are alternately connected with repeating HIGH and LOW by a pull-up resistor R1 and a pull-down resistor R2 connected to a power source terminal VCC and a grounding terminal GND. When the module 101 is mounted and supplied with power from a memory control circuit via the power source terminal VCC and a grounding terminal GND, the terminals OE, CAS, A0, A2,... should be LOW, and the terminal WE, RAS, A1, A3... should be HIGH. Otherwise, connection anomaly is determined.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a module used for testing a circuit board using a semiconductor memory module.

[0002]

2. Description of the Related Art In general, a circuit board for information equipment uses a circuit board in which a semiconductor memory module is incorporated.
Then, the semiconductor memory module is mounted on the circuit board using a socket soldered to the circuit board.
In this case, even if the semiconductor memory module is complete, if the connection between the socket and the circuit board or the circuit pattern on the circuit board is incomplete, the operation of the device is hindered. Therefore, it is necessary to accurately grasp the problem of the circuit board and to deal with it.

For this purpose, it has been practiced to use an in-circuit tester to check a circuit pattern or a short-circuit or disconnection at a soldering point.

[0004] In recent years, the boundary scan method has been standardized, and if a part complies with IEEE-1149.1, inspection can be easily performed. That is, such components can be set and read out by controlling the operation of a chain of several scan-only lines to set the state of each terminal, thereby making it possible to inspect a circuit board for short-circuits and disconnections. It has become.

[0005] In addition, a method has been adopted in which a memory module is mounted on a circuit board and a memory test program is executed by a microprocessor or the like to perform a test.

[0006]

The above three methods have the following problems, respectively.

First, the method using the in-circuit tester requires a dedicated jig. In addition, a connection failure between the terminal of the memory control circuit or the module socket and the board cannot be inspected.

The following boundary scan method compensates for the disadvantage of the in-circuit tester method. However, it is necessary to incorporate a boundary scan circuit inside the component,
As a result, the internal circuit scale is increased, and there is a problem that the operation speed is reduced. In order to realize the boundary scan function, four (or five) dedicated terminals are required. However, it is difficult to increase the number of pins in a high-density mounting component such as a dynamic memory, and therefore, it is necessary to incorporate a boundary scan circuit. And the boundary scan method cannot be applied.

Furthermore, the method of testing with a memory test program requires that a microprocessor operate at least, and there is a problem that a memory test program cannot be executed if there is a connection failure of a memory module.

The present invention has been made in view of the above points, and has as its object to provide a connection test module capable of reliably testing the connection between a memory control circuit and a memory module socket.

[0011]

In order to achieve the above object, according to the present invention, a data input terminal, an address input terminal and a power supply have a structure similar to that of a semiconductor memory module manufactured according to a standard according to claim 1. 3. A test module, comprising: a plurality of pins having terminals; and a circuit connected to each input terminal of the pins except for the power supply terminal so as to generate a signal according to a predetermined data pattern. The module in the test module according to claim 1, wherein each of the input terminals except the power supply terminal has a plurality of switching contacts for generating a signal according to a predetermined data pattern, A test module having a circuit connected to the switch and the test module according to claim 1 or 2. A test terminal having a control terminal to which a control signal is supplied, and a state switching element connected to at least a part of each of the input terminals except the power supply terminal and supplying a signal in a different state according to the control signal. 5. The boundary scan signal to which the boundary scan signal is applied in the test module according to claim 4, and the boundary scan signal which is connected to each of the input terminals except for the boundary scan terminal and the power supply terminal. A test module including a check circuit that generates a signal corresponding to each of the input terminals except for the power supply terminal.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION

(Structure of Embodiment) FIG. 1 shows a first embodiment of the present invention. In FIG. 1, a test module 1
01 is connected to the substrate in place of the semiconductor memory module to be originally mounted in order to inspect the connection relationship between the substrate and the socket. This module has a 20-pin configuration. The terminals OE, WE, CAS, RA are connected by a pull-up resistor R1 and a pull-down resistor R2 connected to the power supply terminal Vcc and the ground terminal GND.
S, A0-A5, and D0-D7 are connected so as to alternately go high and low.

Therefore, the test module is mounted and a memory control circuit (not shown) supplies a power supply terminal Vcc,
When power is supplied via the ground terminal GND, the terminals OE, CAS,
A0, A2,..., D0, D2,.
AS, A1, A3,... D1, D3,. When the module socket is abnormal and the potential of each terminal does not become like this, it is understood that the connection is abnormal.

FIG. 2 shows a second embodiment of the present invention. In FIG. 2, the test module 201
Has a changeover switch 202 in addition to the configuration of the test module of FIG. 1 in which the terminals OE and WE are not connected. The changeover switch 202 is configured using an 8-bit DIP switch in the case of FIG. 2, and the terminals OE, WE, CA
The difference from the first embodiment shown in FIG. 1 is that the potentials of S, RAS, A0-A5 and D0-D7 can be either high or low.

In the state shown in FIG. 2, the terminals CAS, A0, A
, D0, D2,... Are high and terminals RAS, A1, A
3,... D1, D3,. By switching the DIP switch 202, the potential of each terminal can be inverted between high and low, and all terminals can be set to the same potential, either high or low.

FIG. 3 shows a third embodiment of the present invention. In FIG. 3, the test module 301
Is provided with a combinational circuit, that is, a circuit 302 configured so that input and output signals are in correspondence with each other. The input terminal IN of the combinational circuit 302 is connected to the terminals OE, WE, CAS, RAS, and A0-A5 of the test module. And the three-state driver 30 is connected to the output terminal 0 of the combinational circuit 302.
3, terminals D0 to D7 of the test module are connected. An operation terminal 304 is provided for operating the three-state driver 303.

At least some of the input and output terminals may be connected without passing through the combinational circuit 302 and the three-state driver 303.

The three-state driver 303 includes an operation terminal 304
The state switching is controlled by a signal from
When the operation terminal 304 is high, the three-state driver 303 is enabled and the result of the logical operation is output to the data terminal.

FIG. 4 shows a fourth embodiment of the present invention. In FIG. 4, a test module 401
Is known, for example, as SN74BCT8374.
Three memories 402 that can perform boundary control are used. The internal configuration of the memory 402 is as shown in FIG. 5, and the terminals CLK, OC, DI-D8, Q1-
Q8, TDI, TD as boundary control terminal
It has O, TCK, and TMS. Then, all the terminals can be boundary-controlled.

On the substrate 401, TDO, TDI, TCK, TMS,
TRES are provided, and these terminals are connected to each memory 4
02. However, the boundary control terminal TRES can be omitted, and in the case shown in the figure, a memory that does not need to be connected to the terminal TRES is used, so that it is not connected to the terminal TRES.

Here, the terminals TMS and TCK are commonly connected to all the memories 402, the terminal TDI is connected to the first one of the three memories, and the terminal TDO is connected to the third one. As a result, the input pins and the output pins of the memory 402 are connected, and the signals are individually connected to all the address, control and data pins. The memories 402 are chained by the boundary scan signal. (Inspection Using Embodiment) FIG. 6 explains the inspection of the first and second embodiments shown in FIG. 1 and FIG. In FIG. 6, a test module 501 is represented as a test module that represents the test module 101 in FIG. 1 and the test module 201 in FIG. The inspection module 501 is connected to the memory control circuit 50 by a signal line 510.
2 and further connected to a boundary tester 503 via the memory control circuit 502. Therefore, boundary scan control of the inspection module 501 can be performed by the boundary scan tester 503.

If the signal line 510 is to be tested now,
The boundary scan tester 503 includes the inspection module 50
According to which one of the above-mentioned four types, 1 is considered as a preset circuit configuration, and a test is performed. That is, the signal appearing on the signal line 510 differs depending on which of the first to fourth embodiments the inspection module 501 is. The inspection module is determined using this.

First, when the inspection module 501 is the inspection module 101 in the first embodiment, the inspection operation is performed on the assumption that every other terminal receives a pull-up or pull-down signal. Then, prepare multiple inspection modules with different data patterns,
An inspection is performed for each inspection module. As a result, the signal passed through the test module 101 returns to the memory control circuit 502, and the test is performed based on the returned signal. As a result, even when the memory control circuit 502 does not have the boundary scan function and is not included in the scan chain, the connection state of the terminal can be inspected.

When the test module 501 is the test module 201 in the second embodiment, a signal corresponding to the setting of the switch 202 built in the test module 201 appears on the signal line 510.

Therefore, the switch 201 is set in a plurality of states, and a test is performed with various data patterns. As a result, the inspection can be performed without the memory control circuit 502 having the boundary scan function.

FIG. 7 shows a connection state when the inspection module 501 is the inspection module 301 in the third embodiment. In this case, the boundary scan tester 503 controls the scan signal and
4 is given "1". The inspection module 301 performs an operation using a combinational circuit whose input and output are in correspondence, and generates an output at a data output terminal. This signal is taken into the boundary scan circuit 502 and input to the boundary scan tester 503 via the boundary scan signal to check whether a correct result has been obtained. Then, by variously changing the inspection signal, the signal relating to the inspection module 301 can be inspected.

FIG. 8 shows a connection state when the inspection module 501 is the inspection module 401 in the fourth embodiment. In this case, a signal is set to each terminal of the inspection module by a boundary scan signal, and reading is performed. In this case, the inspection module 401 uses the boundary scan tester 503 to
The built-in memory 402 is connected to the signal line 510 and is recognized as a circuit chained by the boundary scan signal. Then, in response to the recognition result, a test signal is output from the boundary scan circuit to the memory 402 on the test module 401 via the signal line 510 and is fetched from the test module 401. The inspection signal may be output from the inspection module 401 and taken in from the boundary scan circuit 502.

The inspection result is taken into the boundary scan circuit, and is input to the boundary scan tester 503 via a boundary scan signal, and is inspected for a correct result. By changing the inspection signal in various ways, the transmission status of the signal transmitted and received between the memory controller 502 and the inspection module 401 is inspected. (Other application examples)
The present invention can be applied to a CPU module and an option card module, and can also be applied to a PCMCIA card and the like.

[0029]

As described above, the present invention can be mounted in place of the memory module to reliably check the connection between the memory control circuit and the memory module socket.

According to the first aspect of the present invention, the test module is connected so as to generate a signal according to a predetermined data pattern, so that it is suitable for a test based on a uniform input / output relationship.

According to the test module of the second aspect, the inspection can be performed by changing the data pattern by operating a plurality of changeover switches.

According to the test module of the third aspect, signals in different states can be given according to the state control signal.

Further, according to the test module of the fourth aspect, the test can be performed by the boundary scan signal.

[Brief description of the drawings]

FIG. 1 is a connection diagram showing a first embodiment of the present invention.

FIG. 2 is a connection diagram showing a second embodiment of the present invention.

FIG. 3 is a connection diagram showing a third embodiment of the present invention.

FIG. 4 is a connection diagram showing a fourth embodiment of the present invention.

FIG. 5 is a block diagram showing an internal configuration of a memory used in the embodiment of FIG. 4;

FIG. 6 is a diagram showing connections between elements for inspecting the embodiment shown in FIGS. 1 and 2;

FIG. 7 is a diagram showing connections between elements for inspecting the embodiment shown in FIG. 3;

FIG. 8 is a diagram showing connections between elements for inspecting the embodiment shown in FIG. 4;

[Explanation of symbols]

 Reference Signs List 101 Inspection module 201 Inspection module 202 Changeover switch 301 Inspection module 302 Combination circuit 303 3-state driver 304 Operation terminal 401 Inspection module 402 Dynamic RAM 502 Memory controller 503 Boundary scan tester

Claims (4)

[Claims] A plurality of pins having a data input terminal, an address input terminal, and a power supply terminal; and a plurality of input terminals excluding the power supply terminal. ,
A test module including a circuit connected to generate a signal according to a predetermined data pattern. 2. The test module according to claim 1, wherein the module is connected to each input terminal except the power terminal, and has a plurality of switching contacts for generating a signal according to a predetermined data pattern. A test module with a switch and a circuit connected to the switch. 3. The test module according to claim 1, wherein a control terminal to which a control signal is supplied, and a signal which is connected to at least a part of each input terminal except the power supply terminal and has a different state according to the control signal. A test module with a given state switching element. 4. A test module according to claim 1, wherein said boundary scan terminal is supplied with a boundary scan signal, and said boundary scan terminal is connected to each of said input terminals except for said boundary scan terminal and said power supply terminal. A test module including a check circuit that generates a signal corresponding to a signal at each input terminal except the power supply terminal.