JPH11510013A - Conversion between one internal cell and multiple standard asynchronous transfer mode cells - Google Patents

Abstract

(57) Abstract: An exchange control module (16) for converting between an internal cell (23) and a first standard asynchronous transfer mode cell (34) and a second standard asynchronous transfer mode cell (36) is provided. You. The internal cell (23) includes an internal header (42), payload information (44), and various information (46). The first standard asynchronous transfer mode cell (34) includes an internal header (42) of the internal cell (23) and various information (46). The second standard asynchronous transfer mode cell (44) contains the payload information (44) of the internal cell (23).

Description

DETAILED DESCRIPTION OF THE INVENTION Patent Application Related to Conversion Between One Inner Cell and Multiple Standard Asynchronous Transfer Mode Cells This application is filed in US Provisional Patent Application No. 60 / 001,498, filed July 19, 1995. is connected with. TECHNICAL FIELD OF THE INVENTION The present invention relates generally to communication systems, and more particularly, to converting between an internal cell and a plurality of standard asynchronous transfer mode cells. BACKGROUND OF THE INVENTION Communication systems include a collection of components that communicate, manipulate, and process information in various ways. The system supports a variety of access technologies for communicating information such as data, voice, and video, such as frame relay, circuit services, and new and evolving connection-based or connectionless services. A switch in a communication system uses hardware and software to route information generated by the access technology to a desired destination. Various types of information cells are used to relay information by the telecommunication switch. One type of cell is an internal cell transmitted over a connection or link in a switch. Other types of cells, such as standard asynchronous transfer mode (ATM) cells, can be used to send information to devices outside the switch. Internal cells may have a larger number of bytes of information than standard ATM cells. If the information in such an internal cell needs to be used outside the switch, a single standard ATM cell will not be sufficient to transfer all the information contained in the internal cell. SUMMARY OF THE INVENTION Accordingly, there is a need for a system and method for converting between an internal cell and a plurality of standard asynchronous transfer mode (ATM) cells. According to one embodiment of the present invention, there is provided an exchange control module for converting between one internal cell and first and second standard asynchronous transfer mode cells. The internal cell includes an internal header, payload information, and various information. The first standard asynchronous transfer mode cell includes an internal header of the internal cell and various information. The second standard asynchronous transfer mode cell contains the payload information of the inner cell. In accordance with another embodiment of the present invention, there is provided a system for converting between an internal cell and a plurality of standard asynchronous transfer mode (ATM) cells. The system includes a switch terminating port processor that receives an internal cell having an internal header, payload information, and various information. The switch control module is coupled to the switch terminating processor. The exchange control module inserts the internal header and various information of the internal cell into the payload of the first standard asynchronous transfer mode cell. The switch control module inserts the payload information of the internal cell into the payload of the second standard asynchronous transfer mode cell. According to yet another embodiment of the present invention, there is provided a method for converting between an internal cell and a plurality of standard asynchronous transfer mode cells. The method includes receiving an inner cell having an inner header, payload information, and various information. The internal header and various information are inserted into the first standard asynchronous transfer mode cell. The payload information is inserted into a second standard asynchronous transfer mode cell. Significant technical advantages of the present invention include conversion between a single internal cell and multiple standard asynchronous transfer mode cells. According to one aspect of the present invention, the internal header and various information are extracted from the internal cell. This internal header and various information are inserted into the payload of the first standard ATM cell. The payload information of the inner cell is extracted and inserted into the payload of the second standard ATM cell. According to another aspect of the invention, information from the payloads of the first and second standard ATM cells in a two-cell format is used to complete the technique of converting one internal cell into two standard ATM cells. By extracting and building the internal cells, these two ATMs can be converted to one internal cell. Other significant technical advantages will be apparent to one skilled in the art from the following figures, descriptions, and claims. BRIEF DESCRIPTION OF THE DRAWINGS For a more complete understanding of the present invention and for further features and advantages, reference is now made to the following description taken in conjunction with the accompanying drawings. FIG. 1 is a diagram illustrating a system for converting between a single internal cell and a plurality of standard ATM cells. FIG. 2 is a diagram showing a single internal cell and a plurality of standard ATM cells corresponding thereto. FIG. 3 is a flowchart illustrating a method of converting one internal cell extracted from a link or a connection into a plurality of standard ATM data cells. FIG. 4 is a flowchart of a method for converting a plurality of standard ATM data cells in a two-cell format into a single internal cell for insertion into a connection. DETAILED DESCRIPTION OF THE INVENTION The preferred embodiment of the present invention and its advantages are best understood by referring to FIGS. 1 to 4, corresponding similar parts are denoted by similar reference numerals. FIG. 1 shows a system 10 for converting between a single internal cell and a plurality of standard ATM cells in a telecommunications switch. The system 10 operates in a normal mode or a two-cell mode. Normal mode operation comprises all the processing typical of a telecommunications switch. In the following description, mainly the operation in the two-cell mode will be described. The system 10 includes at least one To Switch Port Processor (TSPP) 12, at least one From Switch Port Processor (FSPP) 14, a Switch Control Module (SCM) 16, and The switch body 18 is included. Each TSPP 12 may be implemented as an application specific integrated circuit (ASIC). Each TSPP 12 includes a plurality of links 20. Each link 20 includes ATM cell relay (OC-12, OC-30, 155 Mbps UTP), frame relay (T1, E1, T3, E3, V.35), circuit emulation (T1, E1, T3, E3), It supports Ethernet, Fast Ethernet, internetwork using Internet Protocol (IP) or IP over ATM, and other communication protocols or access technologies. In one embodiment, each TSPP 12 supports eight links 20. The TSPP 12 receives various cells such as ATM cells 22 on any of the links 20. The ATM cell 22 comprises a "packet" of information that is converted by the TSPP 12 into an internal cell 23. In one embodiment, the internal cell comprises 56 bytes of information. Each TSPP 12 also includes a plurality of TSPP queues 24 corresponding to each link 20. The TSPP queue 24 has a function of holding or containing the internal cell 23 received by the TSPP 12. Each FSPP 14 can also be implemented as an ASIC. Each FSPP 14 includes a plurality of links 26. Link 26 is substantially similar to link 20. In one embodiment, one FSPP 14 supports 26 links. Each FSPP 14 is associated with a particular TSPP. The associated TSPP 12 and FSPP 14 are contained in a single input / output module (IOM) (not shown). Each FSPP 14 includes a plurality of FSPP queues 28 and 29 corresponding to each link 26 of the FSPP 14. The FSPP queue 28 is used for normal cell processing. The control software reserves an FSPP queue 29 for each of the links 26. The reserved queue inserts operation and maintenance (OAM) cells into the cell stream. The SCM 16 has a function of processing and routing information cells extracted from connections including the connections 20 and 26 of the system 10 and inserted into the connections. The SCM 16 operates both the internal cell 22 and other cells, such as standard ATM cells 34 and 36. The SCM 16 receives the internal cell 22 from the TSPP 12. As will be described in more detail below, the SCM 16 has a function of converting some of these internal cells 22 such as those relating to operation and maintenance (OAM) into a plurality of standard ATM cells in a two-cell format. doing. These standard ATM cells are used inside the SCM 16 or transmitted to external devices of the system 10 by the SCM 16. Further, the SCM 16 receives standard ATM cells in a two-cell format, such as standard ATM cells 34 and 36, from sources external to the system 10. SCM 16 converts these standard ATM cells into a single internal cell that can be inserted into switch 10 at TSPP 30. The SCM 16 includes a TSPP 30 and an FSPP 32. The TSPP 30 stores an internal cell 23 converted from a plurality of standard ATM cells in a two-cell format. The TSPP 30 includes a plurality of queues 31. The FSPP 32 receives and stores the internal cells 23 extracted from the TSPP 12 and reformats them into a plurality of standard ATM cells. The FSP P32 has a plurality of queues 33. The exchange body 18 connects the TSPP 12, the FSPP 14, and the SCM 16. The exchange body 18 has a function of relaying any information between the TSPP 12, the FSPP 14, and the SCM 16. The switch body 18 can be implemented as an ECL crosspoint device. FIG. 2 shows the internal cell 23 and the corresponding standard ATM cells 34 and 36 in a two-cell format. In one embodiment, internal cell 23 comprises 60 bytes of information and standard ATM cells 34 and 36 each comprise 53 bytes of information. The internal cell 23 includes an internal header 42, payload information 44, and various information 46. The internal header 42 includes a virtual channel identification (VCI) field, a virtual path identification (VPI) field, and other information. The payload information 44 includes control information for the exchange. The various information 46 is used, for example, to specify the link 20 and the TSPP 12 from which the internal cell 23 was received. The first standard ATM cell 34 includes an ATM header 48. The ATM header 48 has a cell loss priority (CLP) bit. In the two-cell format, the CLP bit of the ATM header 48 of the first ATM cell 34 is set to “0”. The first ATM cell 34 includes a part of information contained in the internal cell 22. In particular, the payload of the first ATM cell 34 contains an internal header 42 and various information 46. The second ATM cell 36 includes a header 50. The header 50 also has a CLP bit. In the two-cell format, the CLP bit of the second ATM cell 36 is set to “1”. The second ATM cell 36 also contains a portion of information from the internal cell 23. Specifically, the payload of the second ATM cell 36 includes the payload information 44. FIG. 3 is a flowchart of a method 100 for extracting an internal cell 23 from a communication switch connection 20 and converting the cell into a plurality of standard ATM cells in a two-cell format, such as ATM cells 34 and 36. Method 100 begins at step 102. In step 102, TSPP 12 receives internal cell 23. In step 104, the TSPP 12 determines whether or not the received internal cell 23 is a special operation cell such as an OAM. If a negative determination is made, in step 106, the TSPP 12 routes the internal cell 23 to the normal queue 28 of the FSPP 14 of the appropriate IOM via the switch body 18. The normal FSPP queue 28 converts the internal cell 23 so that the internal cell 23 is output to the link 26 corresponding to the normal FSPP queue 28. If it is determined in step 104 that the received internal cell 23 is a special operation cell, in step 108 the TSPP 12 routes the internal cell to the appropriate FSPP queue 33 on the SCM 16. Next, in step 110, the FSPP 32 extracts the internal header 42 and various information 46 from the internal cell 23, inserts this information into the payload of the first ATM cell 34 and, at the same time, extracts the ATM header of the first ATM cell 34. Is set to “0”. In step 112, FSPP 32 extracts payload information 44 from internal cell 23 and inserts that information into the payload of second ATM cell 36. The FSPP 32 sets the CLP bit of the header 50 of the second ATM cell 36 to “1”. Thus, the FSPP 32 generates the ATM cells 34 and 36 in the two-cell format. At step 114, FSPP 32 transfers ATM cells 34 and 36 to network control software for processing. Since cells 34 and 36 are standard ATM cells, they can be used on lines outside links 20 and 26 of the telecommunications exchange. FIG. 4 is a flowchart of a method 200 for converting two standard ATM cells, such as ATM cells 34 and 36, in a two-cell format into a single internal cell 23 for insertion into link 26. Method 200 begins at step 202. In step 202, ATM cells 34 and 36 are received at SCM 16. In step 204, the SCM 16 determines whether or not it is operating in the two-cell mode. If a negative determination is made, in step 206, the SCM 16 processes the received ATM cell in the normal mode. The TSPP 30 performs a function of checking the validity of the first and second ATM cells 34 and 36 by executing each step. As mentioned above, for the two relevant ATM cells in the two-cell format, the CLP bit of the first cell must be set to "0" and the CLP bit of the second cell must be set to "1". In step 208, the TSPP 30 determines whether the CLP of the first ATM cell 34 is set to “0”. If a negative determination is made, the TSPP 30 discards the first ATM cell 34 in step 210. On the other hand, if the CLP bit is set to “0”, the TSPP 30 extracts the internal header 42 and various information 46 from the payload of the first ATM cell 34 in step 212. After the extraction, in step 213, the TSPP 30 determines whether or not the CLP bit of the second ATM cell 36 is set to “1”. If a negative determination is made, in step 210, the TSPP 30 discards the cell. On the other hand, if the CLP bit is set to “1”, the TSP P30 extracts the payload information 44 from the payload of the second ATM cell 36 in step 214. The extracted information is used to construct a single internal cell 23 that can be inserted into the switch body 18 of the system 10. In step 216, the exchange main body routes the internal cell 23 to the FSPP queue 29 in which an appropriate IOM is secured. The FSPP queue 29 converts the internal cell 23 into an ATM cell 22 and allows it to be directly inserted into the cell flow on the link 26. While the invention and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made without departing from the spirit and scope of the invention as defined by the appended claims. It is.

[Procedure of Amendment] Article 184-8, Paragraph 1 of the Patent Act [Submission date] February 19, 1997 [Correction contents]                                The scope of the claims 1. Internal cell with internal header, payload information, and various information of internal cell To the first standard asynchronous transfer mode cell and the second standard asynchronous transfer mode cell. Operable to place the first standard asynchronous transfer mode cell in the internal cell. The second standard asynchronous transfer mode, comprising: Cell is a switch originating side processing comprising said payload information of said internal cell An exchange control module operable to convert an internal cell having a port. 2. The switching originating processing port is connected to the internal cell from the internal cell. A header and the various information are transferred to the payload of the first standard asynchronous transfer mode cell. And further operable to insert into the exchange originating processing port. The port transfers the payload information of the internal cell to the second standard asynchronous transfer mode. The switching system of claim 1, further operable to insert into a payload of the cell. Your module. 3. The switching originating processing port is connected to the first standard asynchronous transfer mode. Further operable to set the CLP bit of the load cell to "0", and The switching originating processing port is connected to the second standard asynchronous transfer mode cell. 2. The exchange of claim 1, further operable to set a CLP bit of the CLP bit to "1". Machine control module. 4. The switching originating processing port is connected to the first and second standard asynchronous 2. The method of claim 1, wherein the transfer mode cell is routed to an external system element for processing. Switch control module. 5. The processing port on the switch originating side requires an internal cell to convert to 2 cells 2. The apparatus according to claim 1, further operable to determine whether or not the cell is a special operation cell. Switch control module. 6. A first standard asynchronous transfer comprising a first header, an inner header, and various information Mode cell and second standard asynchronous transfer with second header and payload information A mode cell includes the internal header, the payload information, and the various information. Exchange terminating processing port operable to convert to a single internal cell Switch control module with 7. The switch terminating processing port is connected to the first standard asynchronous transfer mode. Extracting the internal header and the various information from the payload of the load cell. Operable, and wherein the switch terminating processing port is the second standard non-processing port. Operable to extract the payload information from the payload of the synchronous transfer mode cell And the exchange receiving side processing port is The switch of claim 6, further operable to combine the information into a single internal cell. Control module. 8. The switch terminating processing port is connected to the first standard asynchronous transfer mode. To determine whether the value of the CLP bit of the load cell is set to “0”. And the switching-end-side processing port is connected to the second Whether the value of the CLP bit of the standard asynchronous transfer mode cell is set to "1" The switch control module of claim 6, further operable to determine. 9. The switch terminating processing port is connected to the first standard The first header of the asynchronous transfer mode cell and the second standard asynchronous transfer mode; 7. The exchange of claim 6, further operable to discard the second header of the load cell. Machine control module. 10. The switch terminating processing port is connected to the first and second standard non-switching ports. 7. The exchange according to claim 6, operable to perform a validity check on a synchronous transfer mode cell. Exchange control module. 11. An internal cell including a first information unit and a second information unit; and the first information unit A first standard asynchronous transfer mode cell comprising: and a second standard asynchronous transfer mode cell comprising: Exchange originator operable to convert between two standard asynchronous transfer mode cells Switch control module with processing port. 12. The first information section includes an internal header and various information,   The exchange control module according to claim 11, wherein the second information section includes payload information. Rules. 13. The value of the CLP bit of the first standard asynchronous transfer mode cell is set to "0". And further operable to determine the second standard asynchronous transfer mode cell. The system of claim 11, further operable to set the value of the CLP bit to "1". Switch control module. 14． Performing a validity check on the first and second standard asynchronous transfer mode cells; An exchange control module according to claim 11, operable to operate as follows. 15. Convert between one internal cell and multiple standard asynchronous transfer mode cells A device,   Generate internal cells with internal header, payload information and various information An operable exchange receiving port processing port,   Coupled to the switch terminating processing port and from the internal cell Header and the various information are inserted into the payload of the first standard asynchronous transfer mode cell. Receiving the payload information of the internal cell in a second An exchange control mode operable to insert into the standard asynchronous transfer mode cell payload. Jules,   Coupling the switch control module to the switch terminating processing port And an exchange body. 16. The switch control module is adapted to control the C of the first standard asynchronous transfer mode cell. The switch is further operable to set the value of the LP bit to "0"; The control module sets the value of the CLP bit of the second standard asynchronous transfer mode cell to " 16. The apparatus of claim 15, further operable to set to "1". 17． The processing port on the receiving side of the exchange is connected to the internal cell by the exchange. Further operation to determine whether the cell is a special operation cell addressed to the control module 16. The device according to claim 15, which is capable. 18. At least one special operation queue and at least receiving the internal cell At least one exchange terminating processing port having one normal queue 17. The apparatus of claim 16, comprising a device. 19. Convert between one internal cell and multiple standard asynchronous transfer mode cells The method   Receives an internal cell with an internal header, payload information, and various information,   A first standard asynchronous transfer mode for the internal header and the various information; Insert into cell,   Inserting the payload information into a second standard asynchronous transfer mode cell. Way. 20. The value of the CLP bit of the first standard asynchronous transfer mode cell is set to "0". ,   Set the value of the CLP bit of the second standard asynchronous transfer mode cell to "1" 20. The method of claim 19, further comprising: 21. Determine whether the internal cell is a control cell,   For each cell that is not a control cell, the cell is passed for call processing. 20. The method of claim 19, further comprising a floor. 22. Convert between one internal cell and multiple standard asynchronous transfer mode cells The method   Receiving an internal cell comprising a first information section and a second information section;   Determine whether the internal cell is a special operation cell,   For the internal cell that is not a special operation cell, the first information section is first standard asynchronous. Insert into the transfer mode cell,   The second information section is transmitted to a second standard asynchronous cell for an internal cell which is a special operation cell. A method comprising the steps of inserting into a transfer mode cell. 23. The first information section includes an internal header and various information,   23. The method according to claim 22, wherein said second information part comprises payload information. 24. The value of the CLP bit of the first standard asynchronous transfer mode cell is set to "0". ,   The value of the CLP bit of the second standard asynchronous transfer mode cell is 23. The method of claim 22, further comprising each step of setting to "1". 25. Performs conversion between multiple standard asynchronous transfer mode cells and one internal cell The method   A first standard asynchronous transfer mode cell having an internal header and various information; Receiving a second standard asynchronous transfer mode cell comprising   The internal header and the various information from the first standard asynchronous transfer mode cell; Extract,   Extracting the payload information from the second standard asynchronous transfer mode cell;   Insert the extracted internal header, various information, and payload information into the internal cell A method comprising the steps of: 26. Performing a validity check on the first and second standard asynchronous transfer mode cells; 26. The method of claim 25, further comprising the step of: 27. The value of the CLP bit of the first standard asynchronous transfer mode cell is set to "0". ,   Set the value of the CLP bit of the second standard asynchronous transfer mode cell to "1" 26. The method of claim 25, further comprising:

────────────────────────────────────────────────── ─── Continuation of front page    (81) Designated countries EP (AT, BE, CH, DE, DK, ES, FI, FR, GB, GR, IE, IT, L U, MC, NL, PT, SE), OA (BF, BJ, CF) , CG, CI, CM, GA, GN, ML, MR, NE, SN, TD, TG), AP (KE, LS, MW, SD, S Z, UG), UA (AM, AZ, BY, KG, KZ, MD , RU, TJ, TM), AL, AM, AT, AU, AZ , BB, BG, BR, BY, CA, CH, CN, CU, CZ, DE, DK, EE, ES, FI, GB, GE, H U, IL, IS, JP, KE, KG, KP, KR, KZ , LK, LR, LS, LT, LU, LV, MD, MG, MK, MN, MW, MX, NO, NZ, PL, PT, R O, RU, SD, SE, SG, SI, SK, TJ, TM , TR, TT, UA, UG, UZ, VN (72) Inventor Hauser, Stephen A             Massachusetts, United States             01803, Burlington, Farms Dora             Eve 106 (72) Inventors Manning, Thomas A             Massachusetts, United States             01532, Northborough, Summer Street               26th

Claims (1)

[Claims] 1. An internal cell including an internal header, payload information, and various information A first standard asynchronous transfer mode comprising the internal header of the unit cell and the various information Cell and a second standard asynchronous transfer mode comprising said payload information of said internal cell. An exchange control module operable to convert to a cell. 2. The internal header and the various information from the internal cell are stored in the first standard. Further operable to insert into the payload of an asynchronous transfer mode cell; and The payload information of the internal cell to the second standard asynchronous transfer mode cell The switch control module of claim 1, further operable to insert into a payload. Rules. 3. Set the CLP bit of the first standard asynchronous transfer mode cell to "0" And a CLP of the second standard asynchronous transfer mode cell. The switch control module of claim 1, further operable to set a bit to "1". Jules. 4. The switch control module of claim 1 implemented as an application specific integrated circuit. Rules. 5. Claim further operable to determine whether the internal cell is a special operation cell Item 2. The exchange control module according to Item 1. 6. A first standard asynchronous transfer mode cell comprising an internal header and various information; A second standard asynchronous transfer mode cell comprising erase information; The payload information, and to convert to a single internal cell comprising the various information Operable exchange control mode Jules. 7. From the payload of the first standard asynchronous transfer mode cell to the internal header and And further operable to extract the various information and the second standard Operable to extract the payload information from the payload of the expected transfer mode cell And further operable to combine the extracted information into a single internal cell 7. The switch control module according to claim 6, wherein the switch control module is capable of being operated. 8. The value of the CLP bit of the first standard asynchronous transfer mode cell is set to "0" And further operable to determine whether the second standard Determines whether the value of the CLP bit of the synchronous transfer mode cell is set to "1" 7. The switch control module of claim 6, further operable to: 9. A first header of the first standard asynchronous transfer mode cell; and a second header of the second standard asynchronous transfer mode cell. Claims further operable to discard the second header of the standard asynchronous transfer mode cell. 6. The exchange control module according to 6. 10. Performing a validity check on the first and second standard asynchronous transfer mode cells; 7. The switch control module of claim 6, operable to: 11. An internal cell including a first information unit and a second information unit; and the first information unit A first standard asynchronous transfer mode cell comprising: and a second standard asynchronous transfer mode cell comprising: An exchange control mode operable to convert between two standard asynchronous transfer mode cells. Jules. 12. The first information section includes an internal header and various information,   The exchange control module according to claim 11, wherein the second information section includes payload information. Rules. 13. The value of the CLP bit of the first standard asynchronous transfer mode cell is set to "0". And further operable to determine the second standard asynchronous transfer mode cell. The system of claim 11, further operable to set the value of the CLP bit to "1". Switch control module. 14． Performing a validity check on the first and second standard asynchronous transfer mode cells; An exchange control module according to claim 11, operable to operate as follows. 15. Convert between one internal cell and multiple standard asynchronous transfer mode cells A device,   To receive internal cells with internal header, payload information, and various information An operable exchange receiving port processing port,   Coupled to the switch terminating processing port and from the internal cell Header and the various information are inserted into the payload of the first standard asynchronous transfer mode cell. Receiving the payload information of the internal cell in a second An exchange control mode operable to insert into the standard asynchronous transfer mode cell payload. An apparatus comprising: 16. The switch control module is adapted to control the C of the first standard asynchronous transfer mode cell. The switch is further operable to set the value of the LP bit to "0"; The control module sets the value of the CLP bit of the second standard asynchronous transfer mode cell to " 16. The apparatus of claim 15, further operable to set to "1". 17． In the processing port on the receiving side of the exchange, the internal cell has a special operation cell. The apparatus of claim 15, further operable to determine whether the event is a rule. 18. At least one special operation queue and at least one normal queue 16. The system of claim 15, comprising at least one switch terminating processing port. The described device. 19. Convert between one internal cell and multiple standard asynchronous transfer mode cells The method   Receives an internal cell with an internal header, payload information, and various information,   Inserting the internal header and the various information into a first standard asynchronous transfer mode cell ,   Inserting the payload information into a second standard asynchronous transfer mode cell. Way. 20. The value of the CLP bit of the first standard asynchronous transfer mode cell is set to "0". ,   Set the value of the CLP bit of the second standard asynchronous transfer mode cell to "1" 20. The method of claim 19, further comprising: 21. Determining whether the internal cell is a control cell. Item 19. The method according to Item 19. 22. Convert between one internal cell and multiple standard asynchronous transfer mode cells The method   Receiving an internal cell comprising a first information section and a second information section;   Inserting the first information section into a first standard asynchronous transfer mode cell;   Inserting the second information section into a second standard asynchronous transfer mode cell; How to be. 23. The first information section includes an internal header and various information,   23. The method according to claim 22, wherein said second information part comprises payload information. 24. The value of the CLP bit of the first standard asynchronous transfer mode cell is set to "0". ,   Set the value of the CLP bit of the second standard asynchronous transfer mode cell to "1" 23. The method of claim 22, further comprising the steps of: 25. Performs conversion between multiple standard asynchronous transfer mode cells and one internal cell The method   A first standard asynchronous transfer mode cell having an internal header and various information; Receiving a second standard asynchronous transfer mode cell comprising   The internal header and the various information from the first standard asynchronous transfer mode cell; Extract,   Extracting the payload information from the second standard asynchronous transfer mode cell;   Insert the extracted internal header, various information, and payload information into the internal cell A method comprising the steps of: 26. Performing a validity check on the first and second standard asynchronous transfer mode cells; 26. The method of claim 25, further comprising the step of: 27. The value of the CLP bit of the first standard asynchronous transfer mode cell is set to "0". ,   Set the value of the CLP bit of the second standard asynchronous transfer mode cell to "1" 26. The method of claim 25, further comprising: