JPH1145883A - Manufacture of wiring of semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing the wiring of a semiconductor integrated circuit, in which the generation of defects in a planarizing processing by CMP can be prevented, and damascene microwiring whose damage is small can be formed simply. SOLUTION: A groove is formed by a dielectric film 2, and a conductive film 4 is formed on the dielectric film 2. Then, the conductive film 4 outside the groove is removed by a chemical machine polishing method, so that a planarized surface in which the conductive film 4 is embedded in the groove can be formed. In this case, the surface roughness of the conductive film 4 formed on the dielectric film 2 is larger than a pattern difference in level by the dielectric film 2. Thus, the surface roughness of the conductive film is made large, so that planarizing by CMP can be made satisfactory and simple, and defects due to excessive polishing can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a wiring of a semiconductor integrated circuit, and more particularly to a flattening process for forming a groove wiring.

[0002]

2. Description of the Related Art In recent years, there has been a demand for faster and finer functions of integrated circuits formed on silicon semiconductor substrates.
For this reason, the EM resistance of submicron wiring has become more severe, and there has been a strong demand for the development of wiring having a groove structure called a damascene wiring having high EM resistance. This damascene wiring means that a groove corresponding to a wiring pattern is formed in an insulating film in advance, a conductive film is embedded in the groove, and a conductive film is formed only in the groove by a chemical mechanical polishing method (hereinafter referred to as CMP). It is a wiring obtained by performing a flattening process (Japanese Patent Laid-Open No. 62-102543). FIG. 6 (a)
As shown in (b), the conductive film formed on the dielectric film (insulating film) 7 is composed of a soft low-resistance metal film 8 and a hard metal film 9 and is subjected to chemical mechanical polishing. A technique for performing the method is also known (JP-A-6-84826, etc.).

[0003]

FIG. 4 is a schematic cross-sectional view showing an ideal state (b) of a damascene wiring when CMP is performed and an actual state (c) having a defect.

As shown in FIG. 4A, in a method of manufacturing a damascene wiring, when a groove corresponding to a wiring pattern is formed with a dielectric film (insulating film) 2 and a conductive film 4 is formed thereon, it is usually Then, a step is generated at the region interface between the groove and the flat surface outside the groove. In addition, the conductive film 4 is excessively polished due to the selectivity between the conductive film 4 serving as a wiring and the dielectric film 2 serving as an interlayer film, and a sufficient flat surface cannot be obtained.

In reality, as shown in FIG.
Excessive polishing occurs in a groove having a large pattern width. In addition, as shown in FIG. 4B, the corners of the dielectric film 2 where the film thickness of the conductive film 4 has changed due to local steps are polished and rounded. Also,
As shown in FIG. 4B, a defect in which the conductive film 4 remains locally is observed.

In order to eliminate such a defect,
Before the dielectric film 2 appears, the steps formed in the conductive film 4 must be flattened, and the CMP time must be shortened as much as possible to remove the conductive film 4 other than the grooves.

Further, in the method of planarizing a damascene wiring described in Japanese Patent Application Laid-Open No. 6-84826, since two types of films are used, the number of steps is increased and extra cost and time are required for facilities and the like. become.

An object of the present invention is to provide a method for manufacturing a wiring of a semiconductor integrated circuit, which can prevent the occurrence of a defect in the above-described planarization step by CMP and can form a damascene fine wiring with small damage in a simple step. It is in.

[0009]

SUMMARY OF THE INVENTION The present invention comprises a step of forming a groove corresponding to a wiring pattern with a base dielectric film, a step of forming a conductive film on the base dielectric film, and a chemical mechanical polishing method. Forming a flat surface in which the conductive film is buried in the groove by removing the conductive film in a portion other than the inside of the groove, thereby forming a wiring of the semiconductor integrated circuit. A method of manufacturing a wiring for a semiconductor integrated circuit, wherein a surface roughness of a conductive film formed on a dielectric film is larger than at least a pattern step caused by the underlying dielectric film.

In the method of the present invention, by increasing the surface roughness of the conductive film, planarization by CMP can be made good and easy, and defects due to excessive polishing can be reduced. Further, the method of the present invention can be carried out without greatly increasing the number of steps, so that the increase in cost is small.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below.

In the present invention, a conductive film having a desired surface roughness can be formed by, for example, a CVD method or a PVD method.

In the case of the CVD method, in order to increase the surface roughness of the conductive film, for example, there is a method of growing crystal grains in multiple directions. Specifically, there is a method of increasing the probability of generation of crystal nuclei, and a method of intentionally attaching metal atoms to the surface of the dielectric film. The attached metal atoms increase the growth nucleus density and have a variety of crystal planes, thereby changing the growth rate of the conductive film and increasing the surface roughness of the conductive film.

In the case of the PVD method, the degree of vacuum and the sputtering temperature may be set so that the columnar crystals grow more. In particular, a columnar structure having a convex shape with a tapered tip is desirable.

In order to randomize the growth (irregularities) of the clusters grown by the PVD method and the CVD method, there is also a method of giving various (111, 100, 101, etc.) crystal plane directions. In other words, this is a method in which a pseudo pattern is formed on the surface of a sample on which a conductive film is grown, and an oblique component of a crystal plane obtained by the edge of the pattern is intentionally generated.

Next, a first embodiment of the present invention using metal growth CVD will be described with reference to FIG.

First, as shown in FIG.
The dielectric film 2 on the substrate 1 formed with an FET or the like as a base (not shown) is flattened by CMP or the like. Next, a dielectric film 2 is formed on the substrate 1 by a CVD method, a PVD method, a coating method, or the like. As the dielectric film 2, for example, a silicon inorganic compound such as a BPSG film, a SiO film, and a SiOF film by a CVD method, a film in which R group is mixed with silicon, a pure organic film, and the like can be used. The thickness of the dielectric film 2 may be the same as the thickness of a desired wiring, and is preferably, for example, about 0.3 to 1 μm.

Next, a resist pattern is formed on the dielectric film 2. The resist includes, for example, quinonediazide (DNQ) -novolak-based resist (hereinafter abbreviated as DQ / N) for g- and i-line exposure, Krf, EB exposure, X
In the line exposure, a three-component chemically amplified resist obtained by adding an acid generator and hexamethylolmelamine to a novolak resin can be used. The resist pattern width may be the same as the desired wiring width, and is preferably, for example, about 0.2 to 10 μm.

Next, a resist pattern is transferred to the dielectric film 2 by a dry etching method using a mixed gas of oxygen, carbon, fluorine, ammonia, etc., thereby forming a groove. When etching the dielectric film 2, a film (stopper film) 3 for preventing the microloading effect in advance
May be formed. For example, when the dielectric film 2 is made of an inorganic silicon oxide film and an organic film is used for the stopper film 3, the dielectric film 3 is etched with a fluorine-based gas, and the stopper film 3 which prevents the opening of a through hole between the upper and lower wirings is formed.
Is preferably etched with an oxygen-based gas.

Next, for example, by CVD or PVD,
The conductive film 4 having a desired surface roughness is formed. The conductive film 4 may be a single layer of Al or the like,
For the purpose of improving the resistance, a film of Ti / TiN or the like may be simultaneously formed to form a multilayer. Also, the film to be multilayered is
As long as a sufficient barrier property can be obtained for the dielectric film 2, low-resistance, high-stress-resistant Cu, Ti, Fe, or the like may be used. Further, for improving SM, EM, etc., TiN or W may be used as a single-layer wiring material.

In this embodiment, FIGS. 1 (b) to 1 (d)
As described above, first, an alkali metal atom, for example,
For example, Al, Ni, Fe, Na, K, etc. are formed on the surface of the dielectric film 2.
10 ¹³atoms / cm^TwoTo a degree. Next, CV
By the method D, for example, at a growth temperature of about 300 ° C., Al,
High-density islands of Cu, W, Ti, TiN, etc. (conductive film
4) grow. The thickness of this high density island is 0.
About 2 μm is preferable. This high density island
Due to the influence of the film surface, a random crystal surface is formed. Destination
Under the Al-CVD growth conditions described in
The growth rate differs depending on the type. Thereby, the CVD grown film
Irregularities of at least 0.3 μm are formed on the surface of
You. Also, the grown Al grains erode each other.
Together, the size is further increased. Therefore, the underlying dielectric film
Step that is absorbed by the influence of
And a desired surface roughness can be obtained.

This phenomenon can be confirmed by visual observation that the surface of the CVD film is clouded. That is, a large step is formed such that light cannot be sufficiently reflected. In this way, by high density island and high temperature thin film CVD,
A metal film surface with large surface irregularities can be obtained.

Next, as shown in FIG. 1E, flattening is performed by CMP. When a hard pad (JIS-A: hardness of about 90 degrees) is used, there is a difference in the flattening speed depending on the roughness of the surface to be flattened. FIG. 5 is a graph showing the relationship between surface roughness and flattening speed. The present invention utilizes this phenomenon to perform planarization by CMP. At this time, if only the flattening is required for the CMP, only a hard pad, for example, about 90 degrees in JIS-A hardness may be used. Alternatively, a two-stage CMP method using a soft pad having a JIS-A hardness of 50 degrees or less may be used. If only a hard polishing pad is used, a high pressure of, for example, 0.04 kg / cm ² or more during flattening, and a low pressure of, for example, 0.04 kg at the start and end of polishing.
Pressure change CMP that changes pressure to 3 kg / cm ² or less
Method may be used. In this way, a damascene wiring with a shape close to the ideal shown in FIG. 4B and low damage can be obtained.

Next, with reference to FIG. 2, a second embodiment of the present invention for forming irregularities on a metal surface by forming a dummy pattern will be described.

The second embodiment may be implemented in the same manner as the first embodiment except that a dummy pattern is formed. That is, first, the dielectric film 2 on the substrate 1 formed with a MOS-FET or the like as a base (not shown) is flattened by CMP or the like. Next, a dielectric film 2 is formed on the substrate 1 by CVD.
It is formed by a method, a PVD method, a coating method, or the like. As the dielectric film 2, for example, a BPSG film formed by a CVD method, Si
An inorganic compound of silicon such as an O film and a SiOF film, a film in which R groups are mixed with silicon, a pure organic film, and the like can be used. The thickness of the dielectric film 2 may be the same as the thickness of a desired wiring, and is preferably, for example, about 0.3 to 1 μm.

Next, a resist pattern is formed on the dielectric film 2. As the resist, for example, a three-component chemically amplified resist obtained by adding an acid generator and hexamethylol melamine to a novolak resin for Krf, EB exposure, and X-ray exposure is used, such as DQ / N for g and i-ray exposure. it can. The resist pattern width may be the same as the desired wiring width, and is preferably, for example, about 0.2 to 10 μm.

Next, a resist pattern is transferred to the dielectric film 2 by a dry etching method using a mixed gas of oxygen, carbon, fluorine, ammonia, etc., thereby forming a groove.

In this example, FIGS.
As shown in (b), a dummy pattern 6 is also formed on a base (a dielectric film or the like). In this example, the dummy pattern 6 may be formed on the dielectric film 2 by the same forming method as the groove. In the present invention, the shape of the dummy pattern 6 may be any shape as long as the conductive film 4 formed thereon can have a desired surface roughness. For example, a pattern shape in which surface convex patterns are provided at uniform intervals is exemplified, but the present invention is not limited to this.

At the corners of the dummy pattern 6, islands having multidirectionality (110, 111, 011 etc.) are generated by CVD, and when these polycrystalline plane islands grow, the surface irregularities increase, and the surface irregularities are increased by CVD or PVD. If a conductive film is grown, a conductive film having large surface irregularities can be obtained as shown in FIG. Next, as shown in FIG. 2 (d), if a planarization process is performed by CMP, a damascene wiring having an almost ideal shape shown in FIG. 4 is obtained.

Next, with reference to FIG. 3, a third embodiment of the present invention in which the surface roughness of the conductive film is increased by the PVD method will be described.

The third embodiment may be implemented in the same manner as the first embodiment except that a conductive film having a large surface unevenness is formed by the PVD method. That is, first, MOS-
The dielectric film 2 on the substrate 1 formed with an FET or the like as a base (not shown) is flattened by CMP or the like. Next, a dielectric film 2 is formed on the substrate 1 by a CVD method, a PVD method, a coating method, or the like. As the dielectric film 2, for example, a silicon inorganic compound such as a BPSG film, a SiO film, and a SiOF film by a CVD method, a film in which R group is mixed with silicon, a pure organic film, and the like can be used. The thickness of the dielectric film 2 may be the same as the thickness of a desired wiring, and is preferably, for example, about 0.3 to 1 μm.

Next, a resist pattern is formed on the dielectric film 2. As the resist, for example, a three-component chemically amplified resist obtained by adding an acid generator and hexamethylol melamine to a novolak resin for Krf, EB exposure, and X-ray exposure is used, such as DQ / N for g and i-ray exposure. it can. The resist pattern width may be the same as the desired wiring width, and is preferably, for example, about 0.2 to 10 μm.

Next, a resist pattern is transferred to the dielectric film 2 by a dry etching method using a mixed gas of oxygen, carbon, fluorine, ammonia, etc., thereby forming a groove.

In this example, FIGS.
As shown in (b), a conductive film having large surface irregularities is formed by a PVD method. This FIG.
It is an on-Movchan-Demichishin model. According to Thorton et al., The crystal structure by PVD is a film formation temperature T / Tm standardized by a melting point Tm. At this time, the crystal state suitable for planarization by CMP is Zone
1 is a tapered columnar crystal. By forming a conductive film using such tapered columnar crystals, a conductive film having large surface irregularities can be obtained. Next, by performing a planarization process by CMP, a damascene wiring having an almost ideal shape shown in FIG. 4 can be obtained.

[0035]

According to the present invention described above, by increasing the surface roughness of the conductive film, the occurrence of defects in the planarization step by CMP can be prevented, and damascene fine wiring with small damage can be formed in a simple step. .

Therefore, by using the method for manufacturing a wiring of a semiconductor integrated circuit according to the present invention, a large-scale system having a highly integrated transistor group can be wired on one chip, and a system requiring a plurality of chips is required. As compared with, the manufacturing cost is greatly reduced, and the functions can be diversified and the speed can be increased.

[Brief description of the drawings]

FIGS. 1A to 1E are schematic cross-sectional views illustrating a first embodiment of the present invention using metal growth CVD.

FIGS. 2A to 2D are schematic cross-sectional views for explaining a second embodiment of the present invention in which irregularities on a metal surface are formed by forming a dummy pattern.

FIGS. 3 (a) and 3 (b) are schematic cross-sectional views for explaining a third embodiment of the present invention in which the surface roughness of a conductive film is increased by a PVD method.

4A to 4C are schematic cross-sectional views showing an ideal state of a damascene wiring when CMP is performed and a real state having a defect.

FIG. 5 is a graph showing the relationship between surface roughness and flattening speed.

FIGS. 6A and 6B are schematic cross-sectional views illustrating an example of a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2 Dielectric film 3 Stopper film 4 Conductive film 5 Groove wiring (damascene wiring) 6 Dummy pattern 7 Dielectric film 8 Soft low resistivity metal film 9 Hard metal film

Claims (6)

[Claims] A step of forming a groove corresponding to a wiring pattern by a dielectric film; a step of forming a conductive film on the dielectric film; and a step of forming a conductive film on a portion other than the inside of the groove by a chemical mechanical polishing method. Forming a flat surface in which the conductive film is buried in the trench by removing the film, wherein a surface of the conductive film formed on the dielectric film is formed. A method for manufacturing a wiring of a semiconductor integrated circuit, wherein roughness is at least larger than a pattern step caused by the dielectric film. 2. The semiconductor according to claim 1, wherein a metal atom is attached to the dielectric film, and the conductive film is grown by CVD using the metal atom as a crystal nucleus to form the conductive film having the surface roughness. A method for manufacturing wiring of an integrated circuit. 3. The wiring of a semiconductor integrated circuit according to claim 1, wherein a dummy pattern having a surface convex pattern different from the wiring pattern is formed on the dielectric film, and a conductive film is formed on the dielectric film. Production method. 4. The dielectric film is a silicon oxide film, and when etching the dielectric film, a stopper film made of an organic film for preventing a microloading effect is formed in advance, and the dielectric film is 4. The method according to claim 1, wherein the etching is performed with a fluorine-based gas, and the stopper film is etched with an oxygen-based gas. 5. The semiconductor integrated circuit according to claim 1, wherein the chemical mechanical polishing is performed by polishing for planarization using a hard polishing pad and finish polishing using a soft polishing pad. Manufacturing method of circuit wiring. 6. The chemical mechanical polishing method according to claim 1, wherein the pressure for polishing for flattening the step is relatively high, and the pressure for polishing after the flattening is completed is relatively low. 9. The method for manufacturing a wiring of a semiconductor integrated circuit according to claim 1.