JPH114215A - Diversity circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute antenna switch diversity at high speed at the time of setting a packet communication mode and continuously receiving data in a TDMA system moving machine. SOLUTION: A diversity circuit is provided with a synchronism acquirement part 10 detecting a synchronous word from demodulation data, a timing generation part 11 operating by a bit clock based on a synchronous word detection pulse generated in the synchronism acquirement part 10, logic circuits (flip flop circuit 18 and exclusive OR circuit 19) for measuring a level from an antenna which is selected at present at the time of starting measurement and a selector 14 for switching a received level comparison result and a measured antenna selection signal by a measurement section signal. At the time of continuously receiving several slots in packet communication and the like, received level measurement and antenna selection for switching antenna diversity are executed at high speed in a synchronous word section which is not used for the collation of the synchronous word with demodulation data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a TDMA type mobile unit represented by a PDC (Personal Digital Cellular) type digital mobile phone, which sets a packet communication mode to perform continuous transmission / reception. 20Tb, 1Tb = 1 / bit clock = 1 / 42k
Hz, Tb: bit clock section length = term of
The present invention relates to a diversity circuit capable of performing antenna switching diversity faster than a conventional circuit so that antenna selection can be performed in a section of (bit).

[0002]

2. Description of the Related Art FIG. 5 shows a configuration of a conventional diversity circuit. In FIG. 5, reference numeral 50 denotes a synchronization acquisition unit that detects a synchronization word from demodulated data and generates a synchronization word detection pulse. Reference numeral 51 denotes a timing generator which operates based on a bit clock based on a synchronization word detection pulse. Reference numeral 54 denotes a selector for switching the reception level comparison result 55 and the measurement antenna selection signal 52 according to the measurement section signal 53. Reference numeral 58 denotes a flip-flop circuit (D-) for latching the level comparison result 55 based on the measurement section signal 53.
FF).

Next, the operation of the above conventional example will be described with reference to FIGS. When performing normal transmission and reception, there is an idle section of about 1 ms (42 Tb) between the transmission slot and the reception slot, and the reception level is measured in this section.
You are selecting an antenna. 5 and 6, when the measurement section signal 53 is at the H level, the reception level measurement and antenna selection are performed, the reception level comparison result 55 is latched at the falling edge, and output as the antenna selection signal 57. Also, the H level (7
(Tb or more), the RSSI information is charged and held at the falling edge. The order of antennas to be measured is from 1 system to 2 system.
Tb or more is required. Further, since it takes 1 Tb or more to determine the selection result by comparing the measured values, the minimum time required for antenna switching diversity is 23 Tb.
become.

[0004]

However, in the above-mentioned conventional diversity circuit, when packet communication used for data communication or the like is performed, transmission / reception processing may be performed for several slots at a time, and antenna switching diversity (reception level detection, The antenna cannot be switched until the reception is completed because there is no idle section for performing antenna selection). At this time, even if the antenna currently receiving due to a change in the usage environment of the terminal is deteriorated from the reception sensitivity of the other antenna, antenna switching diversity cannot be performed, and in the worst case, there is a problem that data is erroneous. .

The present invention solves the above-mentioned conventional problem. When receiving several slots continuously in packet communication or the like, a synchronization word (S) not used for synchronization word matching is used.
It is an object of the present invention to provide a diversity circuit capable of performing reception level measurement and antenna selection at high speed in a section W).

[0006]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a synchronization acquisition unit for detecting a synchronization word from demodulated data, and a bit clock based on a synchronization word detection pulse generated by the synchronization acquisition unit. , A logic circuit for measuring the level from the currently selected antenna when starting the reception level (RSSI) measurement, and a selector for switching the reception level comparison result and the measurement antenna selection signal according to the measurement section signal And As a result, when performing reception continuously for several slots in packet communication or the like, reception level measurement and antenna selection can be performed at high speed in a synchronization word (SW) section not used for synchronization word matching.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the first aspect of the present invention, a synchronization acquisition section for detecting a synchronization word from demodulated data, and a bit clock based on a synchronization word detection pulse generated by the synchronization acquisition section. An operating timing generator, a logic circuit for measuring the level from the currently selected antenna when starting the reception level (RSSI) measurement, and a selector for switching the reception level comparison result and the measurement antenna selection signal according to the measurement section signal A high-speed diversity level measurement and antenna selection in synchronization word (SW) section not used for synchronization word matching when receiving several slots consecutively in packet communication etc. It has the effect of being able to.

According to a second aspect of the present invention, there is provided the diversity circuit according to the first aspect, wherein the logic circuit includes a flip-flop circuit and an exclusive OR circuit.
The above operation can be obtained with a simple circuit configuration.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. (Embodiment) FIG. 1 shows a configuration of an embodiment of the present invention. In FIG. 1, reference numeral 10 denotes a synchronization acquisition unit that detects a synchronization word from demodulated data and generates a synchronization word detection pulse. Reference numeral 11 denotes a timing generation unit that operates based on a bit clock based on a synchronization word detection pulse. 14
Is a selector for switching the reception level comparison result 15 and the measurement antenna selection signal 12 according to the measurement section signal 13. Reference numeral 18 denotes a flip-flop circuit (D-FF) for latching a system (antenna) selected at the time of starting antenna measurement. Reference numeral 19 denotes an exclusive OR circuit (EXOR) for first measuring the system (antenna) selected at the time of starting the antenna measurement. Reference numeral 20 denotes a flip-flop circuit (D-FF) for latching the reception result level 15 based on the measurement section signal 13.

The operation of the diversity circuit configured as described above will be described below. As shown in the slot configuration of FIG. 2, even when the receiving slot becomes several consecutive slots due to packet communication or the like, it is necessary to perform antenna switching diversity (receiving level measurement and antenna selection). In the channel configuration shown in FIG. 2, in the synchronization word section SW (20Tb), the demodulated data and the synchronization word are collated for synchronization acquisition / holding. Synchronization word collation is performed at the time of continuous reception in packet communication or the like because the slot specified by the CPU (any of the three slots) is used in a synchronization word section in which synchronization word collation with received data is not performed. Receive level measurement and antenna selection can be performed. In the conventional configuration, at least 23 Tb (system 2 → system 1 → system 2 → selection) was required at least for reception level measurement and antenna selection. However, in this embodiment, reception level measurement and antenna selection are performed in the synchronization word (SW) section. Can be done within

The operation of this embodiment will be described below with reference to FIG.
This will be described with reference to FIG. At the rise of the measurement section signal 13, the D-FF 18 latches the antenna selection signal 17 (currently selected system). Measurement antenna signal 12
Are output in the order of 1 system (L) → 2 system (H).
When the antenna selection signal 17 latched by the FF 18 is the first system (L), the measurement antenna signal 12 is output as it is through the selector 14. When the antenna selection signal 17 latched by the D-FF 18 is the second system (H), the EXOR 19
Then, the measurement antenna signal 12 is inverted and output through the selector 14. After the measurement, the measurement section signal 13
At the falling edge of the signal, the reception level comparison result 15 is latched and output as the antenna selection signal 17. The first antenna switching time 4Tb can be omitted by performing the reception level measurement from the antenna whose currently selected antenna is to be measured in this way. As a result, in the synchronization word section not used for the synchronization word collation (19
At Tb), reception level detection and antenna selection are performed, and antenna switching diversity can be performed.

As described above, according to the embodiment of the present invention, the synchronization acquisition unit 1 for detecting a synchronization word from demodulated data.
0, a timing generation unit 11 that operates on a bit clock based on a synchronization word detection pulse generated by a synchronization acquisition unit 10, and a reception level measurement from an antenna that is currently selected when starting a reception level (RSSI) measurement. By providing a logic circuit (D-FF 18 and EXOR 19) for performing communication and a selector 14 for switching between a reception level comparison result and a measurement antenna selection signal according to a measurement section signal, so as to continuously receive several slots in packet communication or the like. In addition, the reception level measurement and the antenna selection can be performed at a high speed in the synchronization word (SW) section not used for the synchronization word comparison with the reception data.

[0013]

As described above, the present invention provides a synchronization acquisition section for detecting a synchronization word from demodulated data, and a timing generation section which operates on a bit clock based on a synchronization word detection pulse generated by the synchronization acquisition section. , Reception level (RS
SI) By providing a logic circuit for measuring the level from the currently selected antenna at the start of the measurement and a selector for switching the reception level comparison result and the measurement antenna selection signal according to the measurement section signal, several slots for packet communication or the like are provided. It is possible to provide a diversity circuit that can perform reception level measurement and antenna selection at high speed in a synchronization word (SW) section that is not used for synchronization word comparison with demodulated data when performing continuous reception. .

[Brief description of the drawings]

FIG. 1 is a block diagram of a diversity circuit according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a channel configuration according to an embodiment of the present invention.

FIG. 3 is a diagram showing a slot configuration according to the embodiment of the present invention;

FIG. 4 is a timing chart for explaining the operation of the embodiment of the present invention;

FIG. 5 is a block diagram of a conventional diversity circuit.

FIG. 6 is a timing chart for explaining a conventional operation.

[Explanation of symbols]

 10, 50 synchronization acquisition section 11, 51 timing generation section 12, 52 measurement antenna selection signal 13, 53 measurement section signal 14, 54 selector 15, 55 reception level comparison result 16, 56 reception level measurement signal 17, 57 antenna selection signal 18 Flip-flop circuit (D-FF) 19 Exclusive OR circuit (EXOR) 20 Flip-flop circuit (D-FF)

Claims (2)

[Claims] 1. A synchronization acquisition unit for detecting a synchronization word from demodulated data, a timing generation unit operating on a bit clock based on a synchronization word detection pulse generated by the synchronization acquisition unit, and a reception level (RSSI) measurement. A diversity circuit comprising: a logic circuit for level measurement from a currently selected antenna when starting; and a selector for switching a reception level comparison result and a measurement antenna selection signal according to a measurement section signal. 2. The diversity circuit according to claim 1, wherein the logic circuit comprises a flip-flop circuit and an exclusive OR circuit.