JPH114214A - Receiver for digital broadcasting - Google Patents

Abstract

PROBLEM TO BE SOLVED: To receive digital data in an optimum reception state by detecting the occurrence of the error of digital data through the use of an error detection code and supplying and displaying the result on a display element in a digital broadcasting receiver to which digital data and the error detection code are transmitted. SOLUTION: Audio data expanded to original data is taken out from a data expansion circuit 17. Audio data is D/A-converted into an analog/audio signal in a D/A converter circuit 18 and it is taken out to a terminal 19. Data of a high speed information block FIB is taken out from a viterbi decoder circuit 16 and it is supplied to a detection circuit 31. Thus, CRC is obtained from data FIDIT contained in the high speed information block FIB. CRC is compared with transmitted CRC and that the error does not exist is recognized by the matching of both CRC. The rate of the matching of CRC in a prescribed period is calculated, it is supplied to the display element 32 and the rate of matching is displayed by the change of light-emitting colors, green, yellow, orange and red, for example.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital broadcast receiver suitable for use in a digital audio broadcast receiver.

[0002]

2. Description of the Related Art In Europe, DAB (Digital Audio Broadcasting) according to the Eureka 147 standard is implemented. The signal processing on the transmitting side is as follows. (1) Digital audio data of a maximum of 64 channels is data-compressed by MPEG audio layer II for each channel. (2) Encode processing for error correction is performed on the data of each channel resulting from the term (1) by convolutional coding and interleaving on the time axis. (3) The result of item (2) is multiplexed into one channel. At this time, auxiliary data such as PAD is also added. (4) Interleave the result of item (3) on the frequency axis and add a symbol for synchronization. (5) The result of (4) is subjected to OFDM processing (orthogonal frequency division multiplexing processing) and further D / A converted. (6) The carrier signal is subjected to QPSK modulation (quadrature modulation) according to the result of the item (5), and this QPSK signal is transmitted.

FIG. 2 shows a frame structure of data subjected to the OFDM processing in the item (5), that is, baseband data. In this case, the DAB has four operation modes. FIG. 2 mainly shows the case of the mode II for terrestrial broadcasting. One frame of this data has a time length of 24 ms, and also includes a synchronization channel SC, a high-speed information channel FIC, and a main service channel MSC in order from the beginning.
Is divided into

[0004] The synchronization channel SC is used for basic processing such as frame synchronization and AFC. The high-speed information channel FIC is further divided into three high-speed information blocks FIB.
In the FIB, data FIDT such as time, date, type, data arrangement, traffic message control and the like are arranged, and their CRC is added as an error detection code. Further, digital audio data and various data are arranged in the main service channel MSC.

[0005]

SUMMARY OF THE INVENTION An object of the present invention is to make it possible to receive digital data in an optimum receiving state in a receiver for receiving digital data in the above-mentioned format, for example.

[0006]

Therefore, according to the present invention, in a digital broadcast receiver to which an error detection code is sent together with digital data, an error of the digital data is obtained by using the error detection code. Receiving a digital broadcast having a detection circuit for detecting occurrence of an error and a display element, supplying a detection result of the detection circuit to the display element, and displaying the error occurrence state on the display element. Machine. Therefore, the error state of the received digital data is displayed on the display element.

[0007]

In FIG. 1, a broadcast wave signal of DAB is received by an antenna 11, and the received signal is supplied to a front end circuit 12 configured in a superheterodyne format and converted into an intermediate frequency signal. This intermediate frequency signal is supplied to the A / D converter circuit 13 and converted into a digital signal.

[0008] The digital signal is supplied to a quadrature demodulation circuit 14 to demodulate baseband data. The data is supplied to an FFT circuit 15 for OFDM demodulation. The OFDM demodulated data is supplied to a Viterbi decoder circuit 16. To perform deinterleaving and error correction.

At this time, a predetermined selection signal is supplied from the system control microcomputer 40 to the decoder circuit 16 to perform channel selection (program selection), and digital audio data of a target channel is selected.
MPE is supplied to the selected data decompression circuit 17 and
G data decompression is performed.

In this way, the digital audio data of the target channel is expanded from the data expansion circuit 17 to the original data and extracted. Then, the extracted digital audio data is supplied to a D / A converter circuit 18 and D / A converted into an analog audio signal.

Further, a part of the data is supplied from the Viterbi decoder circuit 16 to the RDI circuit 22 to be converted into data of a predetermined transfer format. The data is output to the terminal 29 and is also supplied to the microcomputer 40. Further, for example, the synchronization processor 23 is configured by a DSP, AFC of the front end circuit 12 is performed, and processing such as synchronization in the FFT circuit 15 is executed.

The data of the high-speed information block FIB is extracted from the Viterbi decoder circuit 16 and supplied to a detection circuit 31. In the detection circuit 31, a CRC is obtained from the data FIDT included in the high-speed information block FIB. The CRC is compared with the CRC included in the high-speed information block FIB (the transmitted CRC). In this case, if there is no error in the transmitted data FIDT of the high-speed information block FIB, the results of the above comparison match, but if there is an error, they do not match.

Therefore, every predetermined period, for example, every two to three seconds, the coincident ratio DOK of both CRCs in that period is determined.
(= The number of matches / the number of comparisons) is calculated, and this ratio DOK is supplied to the display element 32 such as a color LED, and when the emission color of the display element 32 is, for example, DOK ≧ 80%, green When%> DOK ≧ 50%, yellow is controlled when 50%> DOK ≧ 30%, when orange 30%> DOK, red is controlled.

According to such a configuration, when an error occurs in the received data, an error occurs in the high-speed information block FIB at substantially the same rate, and the error rate of the high-speed information block FIB is determined by the display element 32 Is displayed. Therefore, it is possible to know the approximate error rate of the received data from the display of the display element 32.

Thus, according to this receiver, when DAB is received, the frequency of occurrence of errors in the received data can be displayed. For example, when the antenna 11 is adjusted in an optimal direction, Can be easily performed, and therefore, DAB can be received in an optimal state. Alternatively, when the receiver operates using a battery as a power source, if the voltage of the battery decreases, the error increases, so that it is possible to indicate that the battery is dead.

In the above description, the light emission color of the display element 32 is changed in accordance with the error rate. During this period. Further, when the presence or absence of a CRC error is detected in the decoder circuit 16, this is notified to the detection circuit 31 so that the error ratio can be similarly displayed.

Furthermore, in the above description, the present invention
The case where the present invention is applied to the receiver B is applicable to a digital broadcast receiver in which an error detection code is transmitted together with digital data.

[0018]

According to the present invention, when a digital broadcast is received, an error occurrence state can be displayed, so that the digital broadcast can be received in an optimum state.

[Brief description of the drawings]

FIG. 1 is a system diagram illustrating one embodiment of the present invention.

FIG. 2 is a format diagram for explaining the present invention.

[Explanation of symbols]

10: LSI, 12: front-end circuit, 13: A /
D converter circuit, 14: orthogonal demodulation circuit, 15: FFT
Circuit, 16 Viterbi decoder circuit, 17 data expansion circuit, 18 D / A converter circuit, 22 RDI circuit,
23: Synchronous processor, 31: Detection circuit, 32: Display element, 40: Microcomputer

Claims (1)

[Claims] 1. A digital broadcast receiver to which an error detection code is sent together with digital data, comprising: a detection circuit for detecting occurrence of an error in the digital data using the error detection code; A digital broadcast receiver, comprising: supplying a detection result of the detection circuit to the display element, and displaying the error occurrence state on the display element.