JPH114204A - Multiplex device/method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multiplex device which can supply packet data synchronized with plural different frequencies with simple constitution. SOLUTION: A multiplex part 40 multiplexing packet data and correcting time information on packet data accompanied by multiplex, a buffer 61 for writing and accumulating packet data and reading it synchronized with the frequency different from that at the time of writing packet data and a buffer controller 62 controlling time from the writing of packet data to the reading of it to be constant are provided. Thus, the multiplex device 31 which can supply packet data synchronized with the plural different frequencies is provided with simple circuit configuration.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[Table of Contents] The present invention will be described in the following order.

BACKGROUND OF THE INVENTION Prior Art (FIGS. 7 to 13) Problems to be Solved by the Invention Means for Solving the Problems Embodiments of the Invention (FIGS. 1 to 6) Effects of the Invention

[0003]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplexing apparatus and a multiplexing method, and is suitably applied to, for example, a multiplexing apparatus and a multiplexing method of a digital broadcasting system.

[0004]

2. Description of the Related Art In recent years, MPEG2 (Moving Picture Experts) has been used as a compression encoding method for video data and audio data.
There is a method called Group Phase 2). This MPEG
2 is based on the ITU-T (Internationa
l Telecommunication Union-Telecommunication Stande
rdization Sector: Standardization by organizations such as the International Telecommunication Union Telecommunication Standardization Sector (eg Recommendation H.222.0)
Etc.), compression encoding of video data and audio data,
This is standardized for the purpose of multiplexing, storing and transmitting.

[0005] Actually, according to the compression encoding method based on MPEG2, a data format called a program stream (PS) (hereinafter, referred to as PS) is used as a data format for multiplexing the compressed and encoded video data and audio data.
This is called a PS data format) and a data format called a transport stream (TS: Transport Stream) (hereinafter called a TS data format) is defined. Incidentally, the PS data format is applied when storing multiplexed video data and audio data in a predetermined digital storage medium, and the TS data format is used when transmitting multiplexed video data and audio data. Applied.

Here, in the TS data format, for example, video data and audio data that have been compression-encoded are transmitted in packets (hereinafter referred to as TS (Transport Strea
m) (called a packet) and the resulting TSs
It is defined that a TS packet sequence (so-called transport stream) is formed by time-division multiplexing packets. The TS packet includes a header section and a data section. The header section stores synchronization bytes, packet identifiers, and other various packet control data, and the data section includes compression-encoded video data or audio data. Is stored. Incidentally, the synchronization byte is data indicating the start of a TS packet, and the packet identifier is data indicating the content of information stored in the TS packet.

By the way, in recent years, the above-described MPEG
2. Description of the Related Art A digital broadcasting system has been considered in which video data and audio data are compression-encoded and multiplexed using a compression encoding method according to No. 2 and are broadcast using terrestrial waves, satellite waves, cables, or the like. In such a digital broadcasting system, it is conceivable that a plurality of television programs can be broadcasted on one line by compressing and encoding video data and audio data into TS packets and multiplexing them as described above. .

That is, this digital broadcasting system is actually applied to digital television broadcasting such as DVB (Digital Video Broadcasting). For example, when a broadcasting satellite is used as a transmission medium, an ordinary broadcasting satellite has about 20 to 30.
Of transponders and a bandwidth of about 30 [Mbps] per transponder. Therefore, it is assumed that one transponder has a bandwidth of about 36 [Mbps] and one television. Assuming a bandwidth of about 4 Mbps per program is used, it is believed that nine television programs can be broadcast simultaneously, as represented by 36/4 = 9 per transponder. This is called multi-channeling (or multiplexing).

In this digital broadcasting system, time information (hereinafter referred to as PCR (Program Clock Reference)) at the time when the TS packet data is formed is stored in the head of the TS packet data on the transmitting side, and the receiving side. The phase of the operating clock of P
By synchronizing with the operation clock phase on the transmission side based on the CR, video data and audio data can be reproduced accurately. The PCR is performed for all TS
It is not stored in packet data, but is stored for each predetermined TS packet data that can maintain accurate reproduction of video data and audio data on the receiving side. By the way, PC
R is stored, for example, for each TS packet data in which the head data of one frame of video data or audio data is stored.

[0010]

FIG. 7 shows an example of the configuration of such a digital broadcasting system 5. First, in the transmitting device 6, a television program supplied from each of the data output units 7A to 7N is provided. (E.g., video data D1A to D1N and audio data D
2A to D2N and the program information data D3A to D3N) are compression-encoded in the corresponding encoding devices 8A to 8N, respectively, and the thus obtained compression-encoded video data, audio data, and program information data are converted. TS packets are sequentially formed into TS packets for each predetermined block to form TS packet data D4A to D4N, which are sequentially supplied to the multiplexer 9.

Each of the encoding devices 8A to 8N is supplied with an operation clock CLK1A to CLK1N from a corresponding clock generation circuit 10A to 10N, and performs compression encoding and TS packetization at the timing of the operation clocks CLK1A to CLK1N. Execute the processing of

Each of the clock generating circuits 10A to 10N
Supplies the operation clocks CLK1A to CLK1N to the corresponding PCR generation circuits 11A to 11N, respectively, and the PCR generation circuits 11A to 11N sequentially count in synchronization with the corresponding operation clocks CLK1A to CLK1N. Encoding devices 8A corresponding to the value data as count value data D5A to D5N, respectively.
~ 8N.

Thus, as shown in FIG. 8, each of the encoding devices 8A to 8N includes a plurality of TS packet data D4.
When forming A to D4N, a predetermined TS to be stored in the PCR
The count value when these are formed in the packet data TS1 to TS3 is stored as PCR. In addition to this, each of the encoding devices 8A to 8N transmits the TS packet data TS1 to TS3 (that is, the TS packet data T1 to TS3).
(Between S1 and TS packet data TS2, or between TS packet data TS2 and TS packet data TS3)
Of the TS packet data D4A so that the time interval (count number) in which the PCR is stored coincides with the time interval at which these TS packet data TS1 to TS3 are supplied.
To D4N are supplied to the multiplexer 9 respectively.

Thus, the multiplexing device 9 includes the encoding devices 8
A transport stream D7 is formed by multiplexing the TS packet data D4A to D4N (including the TS packet data in which the PCR is stored) respectively input from A to 8N and supplied to the transmission circuit 12. The transmission circuit 12 converts the transport stream D7 into a transmission signal S1 of a predetermined format and transmits the signal.

On the other hand, in the receiving device 15, after the receiving circuit 16 receives the transmission signal S 1 and converts it into a transport stream D 7, it converts this into a data stream 7 A to 7 N provided for each of the data output units 7 A to 7 N of the transmitting device 6. Selection circuits 17A-1
7N. Each of the selection circuits 17A to 17N selects the corresponding TS packet data D4A to D4N from the transport stream D7, and extracts the corresponding TS packet data D4A to D4N from the corresponding TS packet data D4A to D4N.
To supply.

The extraction circuits 18A to 18N select the respective TS packet data D4A to D4N in which the PCRs are stored from the corresponding TS packet data D4A to D4N, extract the PCRs, and extract the PCRs.
D8N corresponding phase locked loop circuits (hereinafter referred to as PLL (Phase Locked Loop) circuits) 2
0A to 20N.

The PLL circuits 20A to 20N use the corresponding PCR data D8A to D8N, respectively, and synchronize the operation clocks CLK2A to CLK2N supplied from the clock generation circuits 10A to 10N in the transmitter 6 with the operation clocks CLK1A to CLK1N. It is generated and supplied to the corresponding decoding devices 19A to 19N.

Thus, in the receiving device 15, the decoding circuit 1
9A to 19N, the corresponding TS packet data D4A to D4N are transmitted to the encoding device 8A of the transmitting device 6.
8N, the decoded video data D1A to D1N and the audio data D2A to 8N are sequentially decoded at the timing of the operation clocks CLK2A to CLK2N synchronized with the operation clocks CLK1A to CLK1N.
D2N and program information data D3A to D3N can be reproduced.

Incidentally, in the digital broadcasting system 5 having such a configuration, the multiplexing device 9 includes the encoding devices 8.
Each of the TS packet data D4A to D4N supplied from A to 8N is sequentially read one by one in a predetermined order to be multiplexed.

That is, as shown in FIG. 9, the multiplexing device 9 comprises, for example, first to fifth television programs CH1 to C
When multiplexing the video data and the like respectively corresponding to H5, it is constituted by input units 27A to 27E and one multiplexing unit 28 corresponding to the first to fifth television programs CH1 to CH5. Thus, in the multiplexing device 9, for example, the TS packet data D15A corresponding to the first television program CH1 is input to the input unit 2 at the timing when the PCR is stored (for example, when the count value indicates "n").
7A, and the TS packet data D15B corresponding to the fifth television program CH5 is supplied so as to arrive at the input unit 27E at the timing when the PCR is stored therein (the timing at which the count value indicates "n + 1"). ,
Further, the TS packet data D15C corresponding to the second television program CH2 is also supplied so as to arrive at the input section 27B at the timing when the PCR is stored therein (the timing at which the count value indicates "n + 2").
The S packet data D15A to D15C are input to each input unit 27A.
The multiplexing process is performed by sequentially reading the data into the multiplexing unit 28 in the order of arrival at the 〜27E.

However, as shown in FIG. 10, in the multiplexing apparatus 9, for example, while the multiplexing unit 28 reads the TS packet data D15A, each of the TS packet data D15A is read.
B and D15C correspond to the input units 27E and 27, respectively.
7B, the TS packet data D15B and D15C are input to the corresponding input units 27E and 27B, respectively.
, And the supply time of each of the TS packet data D15B and D15C is delayed.

That is, each TS packet data D15B
The time interval at which these TS packet data D15B to D15D are supplied increases with respect to the count number between D15D and D15D, and the time interval cannot be represented by the count number, which is the time interval between PCRs.

Accordingly, in the digital broadcasting system 5 as shown in FIG.
1A to CLK1N and the operation clock CLK of the receiver 15.
2A to CLK2N are not synchronized, so that it becomes difficult for the receiving device 15 to accurately reproduce the video data, the audio data, and the program information data.

For this reason, in the multiplexer 9 shown in FIG. 7, the time when each of the TS packet data D15A to D15D has been in the standby state is detected, and the PCR for correcting the PCR of each of the TS packet data D15A to D15D is detected based on this time.
A CR correction circuit is required.

By the way, the TS packet interface, which is currently a standard for transmitting TS packets, mainly has a DV packet.
B-ASI (Digital Video Broadcasting-Asynchron
ouseSerial Interface) and DVB-Paralell (Digit
al Video Broadcasting-Paralell). DVB-ASI is a serial transmission, which transmits a TS packet at a frequency of 27 [MHz] as shown in FIG. The interval between packets is specified to be at least two clocks or more. DVB-Paralell is a parallel transmission, as shown in FIG. 12, for continuously transmitting TS packets at a frequency of 13.5 [MHz] or less.

DVB-ASI and DVB-Paralell have the following advantages and disadvantages, respectively. DV
Since B-ASI is serial transmission, the transmission possible distance can be made longer than that of DVB-Paralell, and a coaxial cable can be used, so that the handling at the time of installation is excellent. On the other hand, DVB-Paralell has a shorter transmission distance than DVB-ASI due to parallel transmission, and uses a thicker cable than DVB-ASI. However, the synchronization frequency is 13.5 [MHz] or less. A
Since the circuit operates at a frequency lower than that of the SI, circuit design is facilitated.

As described above, DVB-ASI and DVB-Pa
Since ralell has advantages and disadvantages, both are used in a mixed manner, and a multiplexing device used in a broadcasting station or the like needs to have two, DVB-ASI and DVB-Paralell.

Here, DVB-ASI and DVB-Paralell
Since the synchronization frequencies are different, dedicated multiplexing units for the DVB-ASI multiplexing unit and the DVB-Paralell multiplexing unit are required. For this reason, as shown in FIG. 13, when the multiplexing device 9 is provided with two interfaces of DVB-ASI and DVB-Paralell, the circuit scale of the multiplexing unit is doubled, and the circuit configuration becomes complicated. There was a disadvantage.

The present invention has been made in view of the above points, and has as its object to propose a multiplexer capable of supplying TS packet data synchronized with a plurality of different frequencies with a simple configuration.

[0030]

According to the present invention, a processing time required for multiplexing at least packet data storing time information is detected, and corresponding packet data is detected based on the processing time. The packet data can be supplied at two different frequencies by correcting the time information, and then writing and accumulating the packet data and reading out the data in synchronization with a frequency different from the frequency at which the data was written after a predetermined time.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. In FIG. 1 in which the same reference numerals are assigned to parts corresponding to those in FIG. 7, reference numeral 30 denotes a digital broadcasting system as a whole, and FIG.
Has the same configuration as the digital broadcasting system 5 shown in FIG.

The transmitting device 6 includes data output units 7A to 7N
(For example, video data D1A to D1N, audio data D2A to D2N, and program information data D3A to D3) corresponding to television programs supplied from
3N) are compression-encoded by the corresponding encoding devices 8A to 8N, and the compression-encoded video data, audio data, and program information data thus obtained are sequentially converted into TS packets for each predetermined block. TS
The packet data D4A to D4N are formed and sequentially supplied to the multiplexer 31.

The encoding devices 8A to 8N are supplied with operation clocks CLK1A to CLK1N from the corresponding clock generation circuits 10A to 10N, respectively, and perform compression encoding and TS packetization at the timing of the operation clocks CLK1A to CLK1N. Execute the processing of

Each of the clock generating circuits 10A to 10N
Supplies the operation clocks CLK1A to CLK1N to the corresponding PCR generation circuits 11A to 11N, respectively, and the PCR generation circuits 11A to 11N sequentially count in synchronization with the corresponding operation clocks CLK1A to CLK1N. Encoding devices 8A corresponding to the value data as count value data D5A to D5N, respectively.
~ 8N.

Thus, as shown in FIG. 1, each of the encoding devices 8A to 8N has a plurality of TS packet data D4.
When forming A to D4N, a predetermined TS to be stored in the PCR
The count value when these are formed in the packet data TS1 to TS3 is stored as PCR. In addition to this, each of the encoding devices 8A to 8N transmits the TS packet data TS1 to TS3 (that is, the TS packet data T1 to TS3).
(Between S1 and TS packet data TS2, or between TS packet data TS2 and TS packet data TS3)
Of the TS packet data D4A so that the time interval (count number) in which the PCR is stored coincides with the time interval at which these TS packet data TS1 to TS3 are supplied.
To D4N are supplied to the multiplexer 31.

In FIG. 2 where parts corresponding to those in FIG. 13 are assigned the same reference numerals, reference numeral 31 denotes a multiplexer as a whole.
A plurality of similarly configured input sections 32A to 32N are connected to the multiplexing section 40. The multiplexing unit 40 includes a DVB-ASI interface (hereinafter, DVB-ASI) passing through the parallel-serial conversion unit 60 and a DVB-Parallel interface (hereinafter, DVB-Paralell) not passing through the parallel-serial conversion unit 60. It is connected to the transmission circuit 12 (FIG. 1) via two interfaces. The multiplexing unit 40 is supplied with the parallel clock CLKp from the parallel clock generation circuit 63, and the multiplexing unit 40
Operate in synchronization with the parallel clock CLKp.

FIG. 3 is a detailed block diagram of the multiplexer 31. The TS packet data D4A to D4 are input from the encoding devices 8A to 8N to the corresponding input units 32A to 32N, respectively.
N is supplied. The TS packet data D4A supplied to the input unit 32A is supplied to a packet identification circuit 34A and a time stamp adding circuit 35A. The packet identification circuit 34A identifies the tail of each TS packet data D4A, and supplies the timing signal S10 to the time stamp addition circuit 35A when the tail reaches the input section 32A.

Here, the multiplexing section 40 is provided with a time stamp generating circuit 41, and the time stamp generating circuit 41 is supplied with the serial clock CLKs generated by the serial clock generating circuit 10. The time stamp generating circuit 41 performs a counting operation in synchronization with the serial clock CLKs, and supplies the count value to the time stamp adding circuit 35A as count value data D30.

The time stamp adding circuit 35A adds the TS packet data D4A to the end of the TS packet data D4A that has arrived sequentially based on the timing signal S10.
Is added as a first time stamp TM1 to the memory 42A as TS packet data D31A. The first time stamp TM1 indicates a time when the multiplexing device 31 starts the multiplexing process of the TS packet data D4A.

The memory 42A sequentially stores the input TS packet data D31A, and supplies the storage information to the readout circuit 43 of the multiplexing unit 40 as a storage signal S11.

The read circuit 43 determines the storage information of the TS packet data D31A in the memory 42A based on the storage signal S11, and supplies the read signal S12 to the memory 42A when the storage amount of the TS packet data D31A reaches a predetermined amount. I do.

The memory 42 that has received the read signal S12
Is the TS packet data D31 stored therein.
A is read and supplied to a time stamp identification circuit 44, a PCR identification circuit 45, and a PCR correction circuit 46 provided in the multiplexing unit 40, respectively.

The time stamp identification circuit 44 is provided with the first time stamp TM added to the TS packet data D31A.
1 is supplied to the arithmetic circuit 51 as the first time stamp data D35.

The count value data D30 is constantly supplied to the arithmetic circuit 51 from the time stamp generation circuit 41, and the count value at the time when the first time stamp data D35 arrives is taken in as the second time stamp TM2. This second time stamp TM2 is transmitted to the multiplexer 31
Means the time when the TS packet data D4A has completed the multiplexing process. Therefore, the arithmetic circuit 51 calculates the first time stamp TM1 and the second time stamp TM2 from
The multiplexing device 31 calculates a processing time T, which is a time required for multiplexing the TS packet data D4A, and uses the processing time T as processing time data D36 for the PCR correction circuit 46.
To send to.

The PCR identification circuit 45 identifies the presence or absence of a PCR in each TS packet data D31A, and
If the PCR is stored in the packet data D31A, the PCR correction circuit 46 executes the PCR correction processing operation. If the PCR is not stored in the TS packet data, the PCR correction circuit 46 executes the PCR correction operation.
Control signal S2 that stops the correction processing operation of
0 is sent to the PCR correction circuit 46.

As a result, the PCR correction circuit 46 adds P to the TS packet data D31A input from the memory 42A.
When the CR is stored, the PCR correction operation is executed, and the PC included in the TS packet data D31A is executed.
From R and the processing time data D36, a corrected PCR, which is a PCR obtained by adding the time required for the multiplexing processing to the PCR calculated at the beginning of encoding, is calculated, and the corrected PCR is stored in the PCR of the TS packet data D31A. After storing the TS packet data D31A in a predetermined position,
The data is supplied to the time stamp removing circuit 50 as packet data D40A. The TS input from the memory 42A
If the PCR is not stored in the packet data D31A, the PCR correction operation is stopped, and the TS packet data D31A is directly used as the corrected TS packet data D4.
It is supplied to the time stamp removal circuit 50 as 0A.

The time stamp removing circuit 50 uses the modified TS
From the packet data D40A to the first time stamp TM1
After removing the parallel TS packet data D4
5A to the parallel-serial conversion unit 60,
The signal is supplied to the transmission circuit 12 (FIG. 1) via the B-Paralell.

Here, the PCR is the serial clock CLK.
s is the value of the counter with the clock. The multiplexing section 40 operates in synchronization with the parallel clock CLKp, and the parallel TS packet data D45A also synchronizes with the parallel clock CLKp. However, the serial clock CLKs and the parallel clock CLKp are not always synchronized and have different frequencies. Therefore, as shown in FIG. 4, the modified PCR timing tpc (n) indicated by one modified PCR and the corresponding parallel PCR timing tpp (n) of PCR-p (n), which is the PCR of the parallel TS packet data D45A. ), An error of one clock or less occurs on the serial clock CLKs. This error is referred to as PCR correction error Tpc
Called e.

However, according to the DVB standard, this error is 13
Since it is within the allowable range within the clock, the PCR correction error Tpce poses no problem in practical use. Therefore, the modified PCR timing tpc (n)
Can be used as the parallel PCR timing tpp (n). Therefore, the value of the corrected PCR corrected in the PCR correction circuit 46 can be used as the PCR (PCR-p (n)) of the parallel TS packet data D45A.

Thus, the multiplexing unit 40 corrects the PCR of the TS packet data D31A storing the PCR based on the processing time of the multiplexing process, and supplies each parallel TS packet data D45A storing the corrected PCR. The interval is made to match the difference in the count number between the modified PCRs.

In the multiplexing section 40, each input section 3
Memory 42A-42N corresponding to each of 2A-32N
Supplies the storage signal S11 to the readout circuit 43, the readout circuit 43 determines the storage status of each of the TS packet data D31A to 31N in each of the memories 42A to 42N, and the storage amount of each of the TS packet data D31A to 31N becomes a predetermined amount. When it reaches, each memory 42A-42N is sequentially read out based on a preset reading order.
A read signal S12 is supplied to A to 42N. Thus, in the multiplexing unit 40, the readout circuit 43 sequentially reads out the TS packet data D31A to 31N one by one, so that the TS packet data D31A to 31N can be multiplexed.

The parallel TS packet data D45A sent to the parallel-serial conversion unit 60 is
1 and the buffer controller 62. The buffer controller 62 controls the parallel TS packet data D4.
5A, and monitors the parallel TS packet data D45.
When the supply of A is confirmed, a read / write signal S21 is sent to the buffer 61 to instruct the buffer 61 to write the parallel TS packet data D45A. Lead
The buffer 61 that has received the write signal S21 starts writing the parallel TS packet data D45A, and stores the parallel TS packet data D45A therein.

Further, the buffer controller 62 continues to monitor the parallel TS packet data D45A, and confirms that the buffer 61 has completed the writing of one packet of the TS packet data D45A.
1 sends a read / write signal S21 to the buffer 61.
Is instructed to read the stored parallel TS packet data D45A. The buffer 61 synchronizes the TS packet data D45A with the serial clock CLKs,
DVB- as serial TS packet data D50A
The data is transmitted to the transmission circuit 12 (FIG. 1) via the ASI.

FIG. 5 is a timing chart showing the write and read operations of the buffer 61. When the parallel TS packet data D45A arrives, the buffer 61 performs a write operation W in synchronization with the parallel clock CLKp, and performs the write operation W of the parallel TS packet data D45A. As soon as writing of one packet is completed, the serial clock C
The read operation R is performed in synchronization with LKs, and the serial TS
It is transmitted as packet data D50A.

Here, the modified PCR timing tpc (n) indicated by one modified PCR and the corresponding PCR of the serial TS packet data D50A
There is a delay between the serial PCR timing tps (n) of −s (n). This delay is called a conversion delay td.
As shown in FIG. 6, the conversion delay td is the delay tda and the delay td.
db.

The delay tda is the corrected PCR timing tp
This corresponds to the time from c (n) to the last tail timing tep (n) corresponding to the last tail of the corresponding parallel TS packet. Further, the delay tda is corrected from the corrected PCR timing tpc (n) to the parallel PCR timing tpp.
(N) and the parallel PCR timing tpp (n) ~
Consider the parallel end timing tep (n) separately. PCR between tpc (n) and tpp (n) shown in FIG.
correction error Tpce, which is practically negligible because it is less than one clock on the serial clock. tpp
The period from (n) to tep (n) is the time from the start of the PCR packet to the end of the parallel TS packet including the PCR packet, and is always constant. Therefore, the delay tda can always be regarded as practically constant.

The delay tdb corresponds to the time from the parallel end timing tep (n) corresponding to the end of the parallel TS packet to the serial PCR timing tps (n). Further, the delay tdb is calculated from the parallel end timing tep (n) to the serial start timing ths.
(N) and serial head timing ths (n) to
It is considered separately for the serial PCR timing tps (n). Between step (n) and ths (n), the buffer 61 completes writing one TS packet,
This is a delay until a packet is read out in synchronization with the serial clock CLKs, which is one clock or less on the serial clock, and can be practically ignored. ths
The period from (n) to tps (n) is the time from the beginning of the serial TS packet to the beginning of the PCR packet, and is always constant. Therefore, the delay tdb can always be regarded as practically constant.

Therefore, the conversion delay td can always be considered practically constant. For this reason, the PCR-p (n) shown in FIG.
CR-s (n), PCR-p (n + 1) and PCR-s
Since the interval between the corresponding parallel TS packet and the serial TS packet like (n + 1) is always constant, the PC
The interval between Rp (n) and PCR-p (n + 1), PCR
The interval between -s (n) and PCR-s (n + 1) is always the same. This means that serial TS packets are supplied at the same interval as parallel TS packets.

As described above, the corrected PCR corrected by the PCR correction circuit 46 is transferred to the serial TS packet data D50.
It can be used as A-D50N PCR.

Thus, the serial-parallel converter 60
Performs parallel-to-serial conversion (also called frequency conversion) for changing a TS packet from a parallel clock to a serial clock.

Thus, the multiplexing device 31 is provided with the encoding device 8
TS packet data D4A ~ supplied from A ~ 8N
D4N is multiplexed, the time required for the multiplexing process is calculated, and the PCR included in each TS packet data is corrected.
Parallel TS packet data D4 via VB-Paralell
Serial TS via 5A-D45N and DVB-ASI
Transmitting circuit 12 as packet data D50A to D50N
To be supplied.

The transmission circuit 12 selects either the parallel TS packet data D45A to D45N or the serial TS packet data D50A to D50N, converts it into a transmission signal S1 of a predetermined format, and transmits it.

On the other hand, in the receiving device 15, after the receiving circuit 16 receives the transmission signal S 1 and converts it into a transport stream D 7, it converts this into a transport stream D 7, which is provided for each of the data output units 7 A to 7 N of the transmitting device 6. Selection circuits 17A-1
7N. Each of the selection circuits 17A to 17N selects the corresponding TS packet data D4A to D4N from the transport stream D7, and extracts the corresponding TS packet data D4A to D4N from the corresponding TS packet data D4A to D4N.
To supply.

The extraction circuits 18A to 18N select the respective TS packet data D4A to D4N storing the PCRs from the corresponding TS packet data D4A to D4N, extract the PCRs, and extract the PCRs.
PLL circuits 20A-20 corresponding to D8N respectively
N.

The PLL circuits 20A to 20N use the corresponding PCR data D8A to D8N, respectively, and synchronize the operation clocks CLK2A to CLK2N supplied from the clock generation circuits 10A to 10N in the transmitter 6 with the operation clocks CLK1A to CLK1N. It is generated and supplied to the corresponding decoding devices 19A to 19N.

Thus, the receiving device 15 is provided with the decoding circuit 19
A to 19N, the corresponding TS packet data D4A to D4N are transmitted to the encoding device 8A of the transmitting device 6.
8N, the decoded video data D1A to D1N and the audio data D2A to 8N are sequentially decoded at the timing of the operation clocks CLK2A to CLK2N synchronized with the operation clocks CLK1A to CLK1N.
D2N and program information data D3A to D3N can be reproduced.

In the above configuration, the multiplexing device 31
Each of the TS packet data D in the input units 32A to 32N
After adding the first time stamp TM1 indicating the timing at which the 4A to D4N arrive at the corresponding time stamp adding circuits 35A to 35N, the packet is multiplexed as TS packet data D31A to D31N according to the instruction of the read signal S12 supplied from the read circuit 43. Time stamp identification circuit 44, PCR identification circuit 45, and PCR
It is supplied to a correction circuit 46.

The time stamp identification circuit 44 identifies the first time stamp TM1 added to the TS packet data D31A to D31N, and supplies this to the arithmetic circuit 51 as first time stamp data D35.

The arithmetic circuit 51 supplies the second time stamp TM2 indicating the end time of the multiplexing process and indicating the timing at which the first time stamp data D35 arrives at the arithmetic circuit 51 by the time stamp generating circuit 41. Obtained from the count value data D30.

The arithmetic circuit 51 has a first time stamp TM
The processing time T, which is the time required for the multiplexing by the multiplexing device 31, is calculated from the first time stamp TM2 and the second time stamp TM2, and the processing time T is supplied to the PCR correction circuit 46 as processing time data D36.

The PCR correction circuit 46 calculates a corrected PCR by adding the time required for multiplexing to the PCR calculated at the beginning of encoding from the PCR included in the TS packet data D31A to D31N and the processing time data D36. After replacing with the PCR of the TS packet data D31A to D31N, it is supplied to the time stamp removing circuit 50 as modified TS packet data D40A to D40N.

The time stamp removing circuit 50 uses the modified TS
After removing the first time stamp TM1 from the packet data D40A to D40N, the first time stamp TM1 is used as the parallel TS packet data D45A to D45N, and the buffer 61 and the buffer controller 62 of the parallel-serial converter 60.
And to the transmission circuit 12 via DVB-Paralell.

The buffer controller 62 is a parallel TS
The packet data D45A to D45N are monitored, and the parallel TS packet data D45A to D45N are written into the buffer 61 in response to the start of the supply of the parallel TS packet data D45A to D45N as shown in FIG. Upon completion, the parallel TS packet data D45A to D45N are synchronized with the serial clock CLKs to make the serial TS packet data D50A to D50N.
A read / write signal S21 is supplied so as to read out the data.

Here, as shown in FIG.
Packets and their corresponding serial TS packets, eg, PCR-p (n), PCR-s (n), PCR-p
Since the interval between (n + 1) and PCR-s (n + 1) is always constant, the interval between PCR-p (n) and PCR-p (n + 1) and the interval between PCR-s (n) and PCR-s (n + 1) The intervals are always the same. This means that the serial TS packet is supplied at the same interval as the parallel TS packet.
R is the serial TS packet data D50A to D50N
Can be used as PCR.

Thus, under the control of the read / write signal S21, the buffer 61 writes the parallel TS packet data D45A to D45N, and the serial clock CL.
Serial TS packet data D50A-
The data is read out as D50N to perform parallel-serial conversion, and is supplied to the transmission circuit 12 via DVB-ASI.

According to the above configuration, the input units 32A to 32N that add the first time stamp TM1 indicating the start time of the multiplexing process to the TS packet data D4A to D4N to make the TS packet data D31A to D31N, and T
A second time stamp TM2 indicating the time at which the S packet data D31A to D31N was multiplexed is fetched, and these TS packet data D31A to D31 are based on the first time stamp TM1 and the second time stamp TM2.
N calculates the processing time required for the multiplexing process, corrects the PCRs of the TS packet data D31A to D31N for the TS packet data D31A to D31N based on the processing time required for the multiplexing process, and calculates the parallel clock CLKp.
And the parallel TS packet data D45A-D4
5N, and a parallel-serial converter for writing the parallel TS packet data D45A to D45N and reading out the serial TS packet data D50A to D50N synchronized with the serial clock CLKs after a delay of a predetermined time. With the simple circuit configuration, DVB-ASI and DVB-Parallel
A multiplexer with two output interfaces can be realized.

In the above embodiment, the buffer controller 62 is used to control the writing and reading of the buffer 61, the timing at which the parallel TS packet data D45A to D45N is started to be supplied to the buffer 61, and the parallel TS packet data D45A. ~
Although the description has been given of the case where the writing and reading of the buffer 61 are controlled based on the timing at which D45N has completed writing to the buffer 61, the present invention is not limited to this, and the parallel TS packet data D45A in the buffer 61 is not limited to this.
Other control means that can fix the time from writing to reading of D45N to D45N may be applied.

Further, in the above embodiment, the case where the present invention is applied to the multiplexing device 31 used in the digital broadcasting system 30 has been described. However, the present invention is not limited to this, and the compression encoding method by MPEG2 is used. The present invention may be applied to a multiplexing device used in various other transmitting devices and transmitting / receiving devices as well as a recording device and a recording / reproducing device.

Further, in the above embodiment, the output from the multiplexer 31 is DVB-Parallel and DVB-Parallel.
The B-ASI is provided with one system each, but the present invention is not limited to this, and DVB-Parallel and DVB-A
-A plurality of ASIs may be provided.

Further, in the above embodiment, DVB-ASI and DVB-Parallel are used as an interface between the multiplexing device 31 and the transmission circuit 12, but the present invention is not limited to this, and the present invention is not limited thereto. You may apply also to an interface.

[0081]

As described above, according to the present invention, multiplexing means for multiplexing packet data and correcting time information of the packet data accompanying the multiplexing, and writing and storing the packet data, and then writing the packet data. By providing storage means for reading in synchronization with a frequency different from the time and control means for controlling the time from writing to reading of packet data at a constant value, a simple circuit configuration enables synchronization with a plurality of different frequencies. A multiplexing apparatus and a multiplexing method capable of supplying the packet data thus obtained can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a digital broadcasting system using a multiplexing device according to the present invention.

FIG. 2 is a block diagram showing an embodiment of a multiplexing device according to the present invention.

FIG. 3 is a block diagram showing details of a multiplexer according to the present invention.

FIG. 4 is a schematic diagram showing PCR timing of a parallel TS packet.

FIG. 5 is a schematic diagram showing buffer write / read timings;

FIG. 6 is a schematic diagram showing an alternative to PCR.

FIG. 7 is a block diagram showing a configuration of a digital broadcasting system.

FIG. 8 is a schematic diagram illustrating a relationship between a PCR and a count value.

FIG. 9 is a schematic diagram showing a process of multiplexing TS packet data in the multiplexing device.

FIG. 10 is a schematic diagram illustrating delay of TS packet data due to multiplexing processing.

FIG. 11 is a schematic diagram illustrating DVB-ASI transmission.

FIG. 12 is a schematic diagram illustrating DVB-Parallel transmission.

FIG. 13 is a schematic diagram illustrating a multiplexing device that supports both serial and parallel.

[Explanation of symbols]

5, 30: a digital broadcasting system; 6, a transmitting device; 9, 31, a multiplexing device; 15, a receiving device;
A, 32B, 32N ... input section, 34A ... packet identification circuit, 35A ... time stamp addition circuit, 40 ...
Multiplexer, 41... Time stamp generating circuit, 42A
... Memory, 43, readout circuit, 44, time stamp identification circuit, 45, PCR identification circuit, 46, PC
R correction circuit, 50 time stamp removal circuit, 51
... arithmetic circuit 60 parallel-serial converter 61
...... Buffer, 62 ... Buffer controller.

Claims (3)

[Claims] 1. Packet data supplied from a plurality of systems and formed by storing time information as required for each predetermined block and packetizing the packet is referred to as:
A multiplexing device for sequentially multiplexing and outputting the multiplexed packet data; multiplexing means for multiplexing the packet data to which the time information is added; writing and storing each of the multiplexed packet data;
Storage means for reading each of the packet data in synchronization with a frequency different from that at which it was written, and control means for controlling the time from writing to reading of the packet data to the storage means to be constant for each of the packets. A multiplexing device comprising: 2. The control means instructs the storage means to write the packet data with reference to the time when the supply of the packet data to the storage means is started, and the time when the packet data is completely written into the storage means. 2. The multiplexing apparatus according to claim 1, wherein an instruction to read said packet data is given to said storage means on the basis of the following. 3. Packet data supplied from a plurality of systems and formed by storing time information as required for each predetermined block and packetizing the data is referred to as packet data.
In a multiplexing method of sequentially multiplexing, the packet data to which the time information is added is multiplexed, and each of the multiplexed packet data is written and stored.
Multiplexing wherein each of the packet data is read out in synchronization with a different frequency from that at which it was written, and the time from writing to reading of the packet data is controlled to be constant for each of the packets to the storage means. Method.