JPH114129A - Power amplifier module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce third mutual modulation distortion (reverse IM3 ) without increasing power consumption and to prevent the drop of a gain by using a field-effect transistor(FET) as the main amplifier element of a power amplifier module and setting the gate width to be not less than a specified value. SOLUTION: Two output signals obtained by power-amplifying signals where two different frequencies are set to be carriers are synthesized. The amplifier element of a final output stage in an outputting power amplifier is set to be FET and the whole gate width Wg of FET is set to be not less than 4.8 mm. Reverse IM3 reduction effect can be increased by enlarging gate width Wg. It is desirable that the value of gate width Wg is in the range of 4.8-20 mm. A more satisfactory suppression ratio PIM3 than a reverse IM3 suppression ratio P' by former FET is obtained and power consumption can effectively be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power amplification module, and more particularly, to a metal semiconductor field effect transistor having a pulse-doped structure based on gallium arsenide (GaAs).
The present invention relates to a power amplifier using MESFET.

[0002]

2. Description of the Related Art In mobile communication such as mobile phones and PHSs (personal handyphone systems), whose markets are rapidly growing in recent years, in order to obtain effective use of frequencies and high transmission speeds, Digital modulation techniques are used. Devices used in these systems, in particular, power amplifiers used in the transmission section are required to have high linearity.

For example, a power amplifier used in a PHS is a π / 4 shift QPSK (Quadrature Phase Shift KPSK).
In order to amplify a signal modulated by eying (four-phase shift keying), adjacent channel leakage power is an important parameter that determines the characteristics of a power amplifier. In PHS, the adjacent channel leakage power is specified by an absolute value,
The base station power amplifier having a large output power is designed to have a large back-off from the saturation output power as compared with the terminal power amplifier. For this reason, the power added efficiency is lower than that for terminals.

[0004] By reducing the power consumption of the power amplifier for the base station, not only the heat radiation design of the base station can be simplified, but also the size and battery capacity of the base station can be reduced. In particular, in PHS, low equipment cost is required, and therefore, power consumption is also an important parameter in designing such a power amplifier.

[0005] In general, the PHS uses a carrier radio frequency of 1.9 GHz band, more specifically, 1895.75 to 1918.55 MHz, and 77 channels are allocated to this frequency band every 300 kHz, and multi-carrier TDMA (time d
ivision multiple access (time division multiple access) communication system is adopted. The PHS base station uses PDC (pe
Unlike cellular base stations such as rsonal digital cellular), individual amplification is used for each transmission and reception channel.
Although the signals are multiplexed into four signals by the TDMA method,
Recently, the number of PHS users has been rapidly increasing, and the number of terminals that can be accessed in one base station area by increasing transmission / reception channels in the base station has been reduced from the conventional three to seven.
Attempts have been made to increase the number.

[System Configuration of PHS 7 Traffic Channel Base Station] For example, in the case of a 7 traffic channel base station capable of accessing seven terminals,
Two sets of transmission / reception channels are provided, and adjacent transmission / reception channels communicate with each other at a predetermined frequency (for example, 600 kHz).
(= 300 kHz × 2)], and operates at _two carrier radio frequencies f ₁ and f ₂ . FIG. 1 shows an example of the transmission unit of the base station for the seven communication channels, and FIG. 2 shows an example of channel assignment in each of the transmission / reception channels (f ₁ , f ₂ ). As shown in FIG. 1, the first and second transmission channels TX
_{1 (f 1), TX 2} (f 2) is provided, and as shown in FIG. 2, 1, each transceiver channel (f _1, f ₂₎
Four channels can be assigned to each frame fr.

Here, one frame (fr) is 625 μs
Eight channel slots cs ₀ to c of [microseconds]
consisting of s _7. In the first transmission / reception channel (f ₁ ),
Channel slots cs ₀ and cs ₄ are control channels c
It is used as h _0, the remaining three pairs of transmission and reception channel slot _{cs 1; cs 5 ~cs 3;} cs 7 can be assigned respectively to the communication channel ch ₁ to CH ₃ of the three terminals, the second in reception channel (f _2), channel slots cs ₀ of 4 pairs; may be assigned respectively to cs ₇ speech channel ch ₄ to cH ₇ of another 4 terminal; cs ₄ to cS _3.

That is, in the PHS, transmission (Tx ₁ , Tx ₂ ) and reception (Rx) are performed on each transmission / reception channel (f ₁ , f ₂ ).
x ₁ , Rx ₂ ) and a time division duplexing (TDD) communication system using one frequency f ₁ , f ₂ is used, and one communication channel is allocated every 625 μs, and four communication channels are allocated. By switching between transmission and reception every (2.5 ms), transmission and reception are alternately performed for each fixed time in each channel slot pair (for example, cs ₁ and cs ₅ ). Accordingly, a total of seven communication channels ch ₁ are used in both transmission and reception channels (f ₁ , f ₂ ).
It is possible to use to CH _7, is not able to access seven terminals.

In the case of such a base station for seven traffic channels, as shown in FIG. 1, both transmission channels Tx ₁ ,
Tx ₂ is provided with transmission signals s ₁ and s _{2 of} a predetermined radio frequency corresponding to each control / communication channel channel ch _{0 to} ch ₃ ; ch _{4 to} ch ₇ every 625 μs. These signals s ₁ and s ₂ are, respectively, mixers M ₁ and M ₂
The high-frequency signal from the frequency-controlled voltage-controlled oscillator VCO is mixed by the first and second automatic level adjustment amplifiers A.
Via LCA ₁ , ALCA ₂ and first and second bandpass filters BPF ₁ , BPF ₂ , the first and second carrier radio frequencies f ₁ , f ₂ are raised (Si ₁ , Si ₂ ), for example The power is supplied to the first and second power amplifiers PA ₁ and PA ₂ of 30 dBm (1 W [watt]). Further, the transmission signals So ₁ and So ₂ individually amplified by the power amplifiers PA ₁ and PA ₂ pass through the first and second isolators IS ₁ and IS ₂ , respectively, and are, for example, 3 dB directional couplers. The power is synthesized at DC. Then, the power-combined signal is transmitted from the antenna AT via the transmission / reception changeover switch S and the third bandpass filter BPF to, for example, 22.0
It can transmit with an instantaneous output of dBm (160 mW [milliwatt]).

[0010] The transport radio frequency f _1, f ₂ of each transmission channel Tx _1, signal So. ₁ from Tx ₂ are simultaneously transmitted, So. ₂ a predetermined frequency from each other [for example, 600 or
900 kHz] (detuning).

Each of the power amplifiers PA ₁ and PA ₂ originally considers the power loss in the elements following these power amplifiers, ie, the isolators I ₁ and I ₂ , the directional coupler DC, the switch S, and the filter BPF. Therefore, it is required to generate a large output power.

In addition, in the case of a base station for seven traffic channels, since power combining is further performed, a part of the output signal P ₁ of _one power amplifier (for example, PA ₁ ) is changed to a directional coupler DC. Through the other power amplifier (eg, PA
₂ ) A wraparound phenomenon C of an output signal, which is input to the output terminal, occurs. For example, very simply, the first power amplifier PA ₁ outputs 30 dBm, and the directional coupler DC and the second isolator I ₂ each have an isolation of 20 dB.
Assuming that take, the second output of the power amplifier PA ₂ echo signal S ₁₂ of -10dBm (0.1 mW) is input.

Therefore, such a wraparound phenomenon C of the output signal causes a third intermodulation distortion called “reverse IM ₃ ”. Figure 3 is a first frequency spectrum of the power amplifier PA ₁ output of the transmission channel TX ₁ by wraparound phenomenon C from the second transmission channel TX ₂ is illustrated schematically. Third-order intermodulation distortion ( "reverse IM _3") component P _IM3 for frequencies f ₂ of the second transmission channel TX ₂ adjacent to the first center frequency f ₁ and its transmission channel TX _1, " 2f ₁ −f ₂ ″. Since this reverse IM ₃ occurs in another channel band, its absolute value is -36d depending on the system standard.
And the Bm less, and the relative intensity (suppression ratio) is set to be less than -58dBc to the size of the center frequency components P _1.

[0014] Such reverse IM _3, even in the second transmission channel TX ₂ adjacent, frequency "2f ₂
A third-order intermodulation distortion including a component of −f ₁ ″ similarly appears,
Exactly the same effect is exhibited.

[0015]

As described above, in mobile communication such as PHS, it is required to generate a large output power despite the need to reduce the power consumption, and moreover, it is necessary to have a 7-talk system. In the channel power amplifier, since the two frequency signals are individually amplified and combined, a distortion characteristic (reverse IM ₃ ) which has not been a problem in the conventional three-channel communication channel power amplifier has emerged as a new problem.

Accordingly, a main object of the present invention is to provide a power amplifier module which solves the above problems and solves the problem of the reverse IM ₃ without increasing the output power to optimize the power added efficiency. It is in.

[0017]

SUMMARY OF THE INVENTION According to the present invention, there is provided, in accordance with the present invention, a first and a second power amplifier for transmitting signals having first and second different frequencies separated by a predetermined frequency as carrier waves. In a power amplifying module that combines and outputs two output signals obtained by power amplification with a directional coupler, an amplifying element at a final output stage of the power amplifier is a field-effect transistor, and all of the field-effect transistors are This can be achieved by setting the gate width to 4.8 mm or more.

For example, in order to reduce the reverse IM ₃ in the transmission channels adjacent to each other as described above, the output power of the power amplifier of each transmission channel is increased, and the frequency components in FIG. Frequency component P
By increasing the difference Pe between ₁ and reverse IM ₃ distortion component P _IM3, it can satisfy the standard. Such a power increasing method can be realized by a normal field effect transistor. However, as described earlier, there is a demand for reducing the power consumption of this type of power amplifier as much as possible, and the power increasing method goes against this demand.

Therefore, in the present invention, a field effect transistor (FE) is used as a main amplifying element of the power amplifying module.
Use the T), by the gate width of the FET to or greater than a predetermined value, without increasing the power consumption, to be able to reduce the reverse IM ₃ itself, moreover, it is possible to prevent a reduction in the gain Will be possible. According to the present invention, the effect of reducing the reverse IM ₃ can be increased by increasing the gate width, and as will be described later in detail,
The value of the gate width is preferably in the range of 4.8 to 20 mm.

According to a feature of the present invention, when the output power of the second power amplifier is input to the output terminal of the first power amplifier via the directional coupler, the second frequency with respect to the first frequency intensity is output. The intensity of the third frequency component induced by the component is set to -65 dBc or less, and the output power of the first frequency is set to 30 dBm or more. Further, in the present invention, the power consumption of the amplifying element at the final output stage of the power amplifying module is set to 3.5 W or less. As a result, the desired reverse IM ₃ and power consumption reduction effect are achieved, and
A power amplification module that satisfies various standards and restrictions can be provided.

According to another feature of the present invention, the use of a pulse-doped field effect transistor in which impurities are doped in a pulsed manner in an active layer as a field effect transistor effectively reduces good reverse IM ₃ and power consumption. can do. That is, according to the present invention, a pulse-doped field effect transistor, in particular, a pulse-doped structure G
By using AAsMESFET, without increasing the power consumption, to be able to reduce the reverse IM ₃ itself, moreover, it is possible to prevent a decrease in gain.

Other features and advantages of the present invention can be more clearly understood from the following description made with reference to the accompanying drawings, but the scope of the present invention is in any way limited by these descriptions. Instead, it is limited only by the provisions of the claims.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION

[Pulse-doped field effect transistor] FIG.
1 shows a cross-sectional view of a field-effect transistor used in a power amplification module according to an embodiment of the present invention. This field-effect transistor is characterized in that the doping distribution of each device layer protrudes in a pulse shape in two channel layers. And the "pulse-doped GaAs"
It is called "MESFET". That is, the semi-insulating G
A p ^- GaAs buffer layer 2 (for example, a carrier density of 2.5 × 10 ¹⁶ [cm ⁻³ ]) is formed on a semiconductor substrate 1 made of aAs, and a high carrier density of 4 × 10 ¹⁸ [Si (silicon) is formed thereon. cm ^-3 ] and thin (eg, 200-400
A first pulse-doped GaAs channel layer 3 (angstrom) pulse-doped (also referred to as hetero-doped) is formed. On the GaAs channel layer 3, Si is coated with a similar carrier density of 4 × 10 ¹⁸ via a first GaAs layer 4 (for example, 150 to 300 Å in thickness).
Second pulse-doped GaAs thinner (eg, 50-100 Å thick) at [cm ⁻³ ].
An s channel layer 5 is formed, on which a second GaAs layer is formed.
A layer is formed (eg, on the order of 200-400 angstroms thick).

In this field effect transistor, a gate electrode 6 is formed on the laminated structure in which each layer is formed as described above. For example, Si ions are selectively and asymmetrically implanted from the surface of the second GaAs layer. Thereby, n ⁺ implantation regions 7 are formed on both sides of gate electrode 6, and n ⁻ implantation regions 8 are formed near one side of gate electrode 6.
Is formed, and an n ^- GaAs cap layer 9 is formed below the gate electrode 6. A source electrode 10 and a drain electrode 11 are formed on the two n ⁺ implantation regions 7. As for the gate electrode 6, a dimension perpendicular to the paper surface with respect to the gate length in the left-right direction of the drawing (represented by "Lg") is referred to as a gate width (represented by "Wg").

The second pulse-doped layer 4 on the front side functions to suppress the surface depletion layer from spreading to the second pulse-doped layer. FIG. 5 shows a case where the gate bias Vg is changed (gate length Lg = 0.7 μm, gate width Wg = 20 μm).
m, drain current Ids at drain voltage Vd = 2 V) and characteristic examples of transconductance gm. Here, Idsso indicates the drain current when Vg = 0 V, and the mutual conductance gm of the drain current Ids is expressed by the following equation, as is well known. gm = ∂Ids / ∂Vg

As shown in FIG. 5, in the pulse-doped field effect transistor (FET) according to the present invention,
The drain current Ids increases while maintaining a substantially linear relationship with the change in the gate bias Vg, and linearly increases to a predetermined gate voltage Vgo, for example, around Vgo = 0.4 volt [V]. That is, the transconductance gm has a flat characteristic without depending on the gate voltage Vg. Therefore,
The component of ∂ ² Ids / ∂Vg ² is almost zero, and the third-order intermodulation distortion is extremely small as described later. this is,
In addition, this FET has a feature that the amplification factor of the field effect transistor, that is, the output efficiency does not decrease even in a region where the drain current is narrowed by increasing the gate bias (in the negative direction). .

In a normal field effect transistor, a high mobility field effect transistor (HEMT), or the like, the characteristic of the transconductance gm with respect to the gate bias Vg is not flat like a pulse-doped FET, but becomes smaller as the gate bias Vg becomes shallower. The gm value is increased (as the drain current Ids is increased). Therefore, in order to increase the transconductance gm, that is, the gain (efficiency), it is necessary to use the gate bias under such a condition that the drain current increases. Such a pulse-doped GaAsMESFE
Regarding the structure and characteristics of T, see, for example, JP-A-4-225.
No. 533, and the like.

Now, in the power amplification module of the present invention,
Not only the characteristics such as the excellent linearity of such a pulse-doped GaAs MESFET can be fully utilized, but also the reverse IM ₃ can be effectively reduced as described below.

FIG. 6 shows a circuit configuration example of a power amplification module according to an embodiment of the present invention. This circuit is
As shown in FIG. 6, using the field effect transistor amplifier element FET1, FET2 two stages, in the present invention, as a main amplifying element FET ₂ of at least the final output stage, field-effect transistor of the above-mentioned pulse-doped structure ( FET), the power amplification module PA is configured. Then, the power amplification module PA thus configured is connected to each transmission channel Tx as shown in FIG.
₁ and Tx ₂ are used as power amplifiers PA ₁ and PA ₂ .

The power consumption is 3.5 W or less (voltage 5 V, current 7
00 mA or less), the power of the output signal So is 30 dBm, the reverse IM ₃ at this time is -35 dBc or less, and the suppression ratio is -65 dB.
c The following is an example of a configuration aiming at the following.

FIG. 7 shows the drain current (Id) of the output power of the pulse-doped field effect transistor FET2 at the final output stage of the power amplifier module according to one embodiment of the present invention.
s) Dependencies are indicated. This is because the gate width Wg = 5.2
This is an actual measurement example when the drain voltage Vd = 5 V with respect to the FET of 1 mm. The output power Pout is a value when the suppression ratio at an adjacent frequency separated by 600 kHz is -60 dBc. The maximum value of the power added efficiency Epa is the drain current Ids
Is obtained at about 30% of the Idsso value, which is about 42.5%. The output power Pout is proportional to the gate width Wg of the field effect transistor used. From FIG. 7, it is assumed that a field-effect transistor having the same properties is used and operated under a bias condition at which the maximum power efficiency is obtained.
In order to obtain an output power of Bm or more, the gate width Wg must be Wgo = 5.2 mm × 10 ^{30/10/10 29/10} = 6.5 mm or more.

[0032] FIG. 8 is a gate width dependency of the reverse IM ₃ suppression ratio of the power amplifier using a pulse doped structure FET according to an embodiment of the present invention is shown. This is because the measurement conditions are as follows: drain voltage Vd = 5 V, drain current Ids = 600 mA, that is, power consumption is 3 W,
Intensity 600kHz detuned from output end when output is 30dBm
It was measured by inputting an interference wave of -10 dBm. As a result, the reverse IM ₃ suppression ratio decreases as the gate width Wg increases.
It was confirmed to be -6 dBc.

Although the reverse IM ₃ suppression ratio P ′ _IM3 of the conventional field effect transistor having no pulse doping structure shows the same decreasing tendency as shown by the broken line, the reverse IM ₃ suppression ratio P _IM3 according to the present invention is obtained. The value for the same gate width Wg is much larger than
Therefore, if an attempt to below a desired value by reducing the reverse IM ₃ using conventional field effect transistor, requires several times the gate width.

That is, it is understood from the results of FIG. 8 that the reverse IM ₃ can be significantly reduced by increasing the gate width Wg. Under a bias condition in which the gate width Wg is increased in a normal FET and the gain is not reduced,
When ET is used, the current flowing through the FET becomes large, and the power consumption increases. In contrast, in a pulse-doped FET having a large gate width Wg,
Since the transconductance gm has a flat characteristic without depending on the gate bias, generation of harmonic distortion is essentially suppressed. Further, such a pulse-doped FE
Because does not cause gain reduction be set to the gate bias conditions to limit the drain current for T, reverse IM ₃
It is possible to achieve both reduction and power consumption.

FIG. 9 shows an interference terminal 1906.55 at the output terminal of the power amplification module according to one embodiment of the present invention.
The output power dependence of the reverse IM ₃ when ± 0.6 MHz and a disturbance wave input of -10 dBm are input is shown. As shown in FIG. 9, at the time of 30 dBm output, -65 dBc
Suppression ratio of can be obtained, it was further confirmed that the desired reverse IM ₃ reduction effect is obtained.

[Example of Method of Determining Gate Width Wg] As described above, the power of the output signal So is set to, for example, 30 dBm [= 1 W].
In order to output 30 dBm, the power consumption of the final-stage field effect transistor FET2 needs to be 2 to 3 W.
For example, drain voltage Vd = 5V, drain current Id =
It shall be 600 mA. In order to obtain this drain current, the gate width Wg of the field effect transistor FET2 is set to Idsso = 1200 mA when the gate voltage Vg = 0 V and the gate width 1 mm.
Assuming 250 mA (/ mm) per unit, and assuming that the A-class operation is performed, a minimum of 4.8 mm is required. Then, using the measurement results of FIG. 8 will increase the gate width Wg, as desired gate width Wg corresponding to reverse IM ₃ value P _IM3 in need, for example, it is possible to obtain a value of 10.4 mm. This value also depends on the threshold voltage value of the field effect transistor. However, in the power amplifier using the pulse-doped FET, the desired relationship is satisfied with respect to the output power and the reverse IM ₃ without the gate width Wg exceeding 20 mm. be able to.

[0037]

As described above, according to the present invention,
By using pulse-doped field effect transistors as power amplifiers in adjacent transmission channels,
While reducing the power consumption of the power amplifier, moreover, it can be obtained conflicting technical effect of significantly reducing the reverse IM ₃ effectively. Also, the desired reverse IM ₃
A reduction effect can be obtained by a simple method of increasing the gate width Wg. This field-effect transistor has a pulse-doped structure G of the type shown in FIG.
By using the aAsMESFET, a power amplifier having more excellent linearity can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a transmitting unit of a base station for seven communication channels of a PHS.

FIG. 2 is a diagram showing channel assignment of a base station for 7 communication channels of PHS.

FIG. 3 is a diagram showing a power frequency distribution for explaining intermodulation distortion due to signal wraparound;

FIG. 4 is a sectional view showing a structural example of a field-effect transistor used in a power amplification module according to one embodiment of the present invention.

FIG. 5 is a diagram showing characteristics of a drain current with respect to a gate voltage of a field effect transistor used in a power amplification module according to an embodiment of the present invention.

FIG. 6 is a diagram showing a circuit configuration of a power amplification module according to one embodiment of the present invention.

FIG. 7 is a diagram showing output power characteristics of the power amplification module according to one embodiment of the present invention.

Diagram for explaining the reverse IM ₃ characteristic according to an embodiment for a gate width of the power amplifier module of the present invention; FIG.

Shows a reverse IM ₃ characteristic according to an embodiment for the output power of the power amplifier module of the present invention; FIG.

[Explanation of symbols]

PA _1, PA ₂ power amplifier module, TX _1, TX ₂ first and second transmission channels, f _1, f ₂ the first and second operating frequency, the S _12, S ₂₁ PA ₁ to PA _2, PA PA ₁ from ₂
Signal, P _IM3 , P ' _IM3 reverse IM ₃ power, 1 GaAs substrate, 2 p ^- GaAs buffer layer 2, 3 first pulse-doped GaAs channel layer, 4 first GaAs layer, 5 second pulse-doped GaAs Channel layer, 7 n ⁺ implantation region formed below source electrode 10 and drain electrode 11 8 n ⁻ implantation region, 9 n ⁻ GaAs cap layer formed below gate electrode 6, Wg gate width, PA power amplification module, FET1, FET2 field effect transistor amplifier element, Pout power amplifier output signal So of the power, P ₁₂ loop signal power.

Claims (6)

[Claims] 1. A signal having a first and a second two different frequencies separated by a predetermined frequency as carrier waves, respectively.
And a power amplifying module that combines two output signals obtained by power amplification with the second power amplifier and then outputs the combined signals using a directional coupler, wherein the amplification element at the final output stage of the power amplifier is a field effect transistor. A power amplification module, wherein the gate width of the field effect transistor is 4.8 mm or more. 2. A gate width of said field effect transistor is 20.
The power amplification module according to claim 1, wherein the distance is equal to or less than mm. 3. When the output power of the second power amplifier is input to the output terminal of the first power amplifier via the directional coupler, the output power is induced by the second frequency component with respect to the first frequency intensity. 3. The power amplification module according to claim 1, wherein the intensity of the third frequency component is -65 dBc or less, and the output power of the first frequency is 30 dBm or more. 4. The power consumption of the amplifying element at the final output stage is
4. The power amplification module according to claim 3, wherein the power is 3.5 W or less. 5. The power amplification module according to claim 1, wherein the field effect transistor is a pulse-doped field effect transistor in which an impurity is doped in an operation layer in a pulsed manner. 6. The semiconductor device according to claim 1, wherein said field effect transistor is GaAsME.
The power amplification module according to claim 5, wherein the power amplification module is an SFET.