JPH1141153A - Transmitter and receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a transmitter/receiver capable of preventing occurrence of a reception error. SOLUTION: The transmitter/receiver 1 is provided with a modulation part 12 to generate a high frequency signal by modulating a phase of a carrier wave, high frequency amplification parts 31, 32 to amplify the high frequency signal, an electric power coupling part 14 at a transmission side to be connected with an electric power coupling part at a reception side and to output the amplified high frequency signal to the electric power coupling part at the reception side, matching parts 33, 34 capable of matching the high frequency amplification parts 31, 32 and the electric power coupling part 14 at the transmission side, an amplitude signal detection part 51 to detect an amplitude signal from the amplified high frequency signal whose amplitude is modulated by a receiver, a demodulation signal generation part 52 to generate a signal for demodulation whose phase is synchronized with the amplitude signal and a demodulation part 53 to demodulate received data from the amplitude signal and constituted to transmit and receive the data by a semi-duplex system. In this case, the received data demodulated when a fixed time passes from the time when the phase of the carrier wave is varied is established as a predetermined value and the received data to be demodulated after the value is established is converted into a value capable of maintaining relative relation with the established value by providing a data conversion part 16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmitting / receiving apparatus, and more particularly, to a phase-locked detection of a high-frequency signal, which is an own transmission signal whose amplitude has been modulated by a receiving apparatus, to receive data received from the receiving apparatus. The present invention relates to a transmission / reception device configured so as to be capable of being used.

[0002]

2. Description of the Related Art As a transmission / reception device of this type, the applicant has
The non-contact IC card reader system 100 (hereinafter, also referred to as “system 100”) shown in FIG. 6 has already been developed. The system 100 is configured so that the IC card 2 can be inserted thereinto.
The power transmission apparatus 101 includes a power transmission device 101 that transmits a high-frequency signal as power for an IC card in a contactless manner. The power transmission apparatus 101 transmits a high-frequency signal obtained by phase-modulating a carrier signal based on a control signal for reading and writing information to the IC card 2,
The power supply for the IC card is supplied to the internal electronic circuit section 72 and an internal memory (not shown) provided in the electronic circuit section 72 can be accessed.

The specific operation will be described with reference to FIGS. 5 and 6. In the power transmission apparatus 101, the CPU 21 in the interface 11 unit converts the transmission data SD shown in FIG. Modulation unit 12
, The phase modulation unit 12 generates a 4.9152 MHz carrier signal CR generated by dividing the frequency of the 9.8304 MHz clock signal CL shown in FIG.
The phase modulation is performed on the transmission data SD (see FIG. 3C) based on the transmission data SD (see FIG. 3A). In this case, the phase modulation unit 1
2 generates high-frequency signals RF1 and RF2 whose phases are orthogonal to each other by phase-modulating the carrier signal CR as shown in FIGS. Specifically, when the transmission data SD is a low-level signal (hereinafter, also referred to as an “L signal”), the phase modulating unit 12 transmits the high-frequency signal RF1 that is 0 ° phase-modulated to the carrier signal CR to the high-frequency amplifier circuit 31. At the same time, the high-frequency signal RF2 obtained by phase-modulating the carrier signal CR by -90 ° is output to the high-frequency amplifier circuit 32. On the other hand, when the transmission data SD is a high-level signal (hereinafter also referred to as “H signal”),
The phase modulating unit 12 outputs the high-frequency signal RF1 phase-modulated to the carrier signal CR by + 90 ° to the high-frequency amplifier circuit 31, and outputs the high-frequency signal RF2 obtained by phase-modulating the carrier signal CR by −180 ° to the high-frequency amplifier circuit 32. Output to

[0004] Next, both high-frequency amplifier circuits 31, 32 are:
The high-frequency signals RF11 and RF12 obtained by amplifying the high-frequency signal RF1 and the high-frequency signal RF2 are connected to an antenna matching circuit 33,
34 respectively. In this case, the constant current supply circuit 3
5 supplies a constant current so that both high-frequency amplifier circuits 3
1, 32 are operating. Antenna matching circuits 33, 3
Reference numeral 4 denotes a center frequency tuned to 4.9152 MHz, which is the same frequency as the fundamental frequency of the carrier signal CR.
1 and 32 are matched with the primary windings 41 and 42 of the high-frequency transformer provided in the antenna unit 14, respectively. On the other hand, the inside of the IC card 2 includes an antenna unit 71,
The high-frequency signals RF11 and RF12 are input to the electronic circuit unit 72 in the IC card 2 via the secondary windings 81 and 82 of the high-frequency transformer provided in the antenna unit 71, respectively.

In the electronic circuit section 72, both high-frequency signals RF1
1, RF12 is rectified to generate power to be used by itself, and high-frequency signals RF11, RF12 are demodulated into transmission data SD by phase-locked detection. Next, the electronic circuit unit 72 accesses the power transmission apparatus 101 according to the transmission data SD. In this case, the electronic circuit unit 72 includes the high-frequency signals RF11 and RF12.
9.8, which is twice the frequency component of the carrier signal CR.
It extracts a 304 MHz clock signal CL and divides the clock signal CL by 2 to generate an internal clock signal for controlling itself. Next, the electronic circuit unit 72
By dividing the internal clock signal by 16, the 307.2 KHz reference subcarrier RS shown in FIG.
A CR is generated, and the generated reference subcarrier RSCR is phase-modulated based on answerback transmission data. In this case, the electronic circuit unit 72 generates the subcarrier SCR by performing phase modulation of the reference subcarrier RSCR by 180 ° at the data change point of the answer back transmission data, as shown at point A in FIG. I do. After this,
The electronic circuit section 72 varies the load impedance of the secondary windings 81 and 82 based on the phase-modulated subcarrier SCR. Thereby, the high frequency signals RF11, RF12
Is amplitude-modulated in synchronization with the subcarrier SCR as shown in FIG.

On the other hand, in the power transmission apparatus 101, the supply terminal voltage of the constant current supply circuit 35 fluctuates due to the amplitude modulation of the high frequency signals RF11 and RF12. Therefore, the reception detection circuit 51 in the reception unit 15
By performing amplitude demodulation, the subcarrier SCR shown in FIG. Here, the carrier synchronization circuit 52
Is a digital PLL (Digital-Phase-Locked-Loop,
(Hereinafter, also referred to as “DPLL”), and driven by the input 9.8304 MHz clock signal CL, as shown in FIG.
A clock signal DCL for demodulation synchronized with R is generated and output to the phase detection circuit 53. The phase detection circuit 53 detects the received data RD shown in FIG. 9K from the subcarrier SCR by performing phase detection by exclusive OR of the clock signal DCL and the subcarrier SCR, and detects the detected received data RD. Output to CPU21. Thereby, the CPU 21 can read and write information in the IC card 2 by receiving the reception data RD.

[0007]

However, the power transmission device 101 developed by the present applicant has the following improvements. That is, the antenna matching circuits 33 and 34 are tuned to the carrier frequencies of the high-frequency signals RF11 and RF12. On the other hand, the carrier signal C
When the phase of R is changed, the harmonic components and other noise components of the carrier signal CR are changed to the high frequency signals RF11 and RF1.
2 included. For this reason, the reception detection circuit 51 adds and detects the amplitude variation of the high frequency signals RF11 and RF12 and the amplitude component of the subcarrier SCR. Therefore,
Since the carrier synchronization circuit 52 automatically follows the detected amplitude change, the carrier synchronization circuit 52 operates to lock to a portion which is not a phase change point which should be phase locked. May output a clock signal DCL having a different (that is, inverted in phase). When such a situation occurs, when the phase detection circuit 53 performs phase detection on the subcarrier SCR, the H signal may be detected as an L signal or the L signal may be detected as an H signal. An error occurs. Therefore, the power transmission device 101 developed by the applicant includes:
Clock signal DC generated by carrier synchronization circuit
There is an improvement that the occurrence of a reception error due to the phase shift of L should be prevented.

The DPLL in the carrier synchronization circuit 52
It is possible to prevent a reception error by setting the lock-up time to a relatively long time to eliminate the phase shift. However, with this setting,
In case of asynchronous transmission / reception, or in case of subcarrier SCR
If the ratio of the time of the data slot to the time of one data slot of the transmission data SD is small, it takes too much time for the DPLL to lock, resulting in the phase detection circuit 53.
This makes it difficult to perform phase-locked detection.

[0009] The present invention has been made to solve such an improvement, and an object of the present invention is to provide a transmitting / receiving apparatus capable of preventing occurrence of a reception error.

[0010]

According to a first aspect of the present invention, there is provided a transmitting / receiving apparatus which modulates a carrier wave based on transmission data to generate a high-frequency signal, and amplifies the high-frequency signal. A high-frequency amplifier, and a transmission-side power coupling unit configured to be coupled to a reception-side power coupling unit disposed on the reception device side and outputting an amplified high-frequency signal amplified by the high-frequency amplification unit to the reception-side power coupling unit; A matching unit capable of matching the high-frequency amplification unit and the transmission-side power coupling unit; an amplitude signal detection unit that detects an amplitude signal from an amplified high-frequency signal amplitude-modulated by the receiving device based on the received data; and A demodulation signal generation unit that generates a demodulation signal that is phase-synchronized with the fundamental frequency signal; and demodulates received data by performing phase detection on an amplitude signal based on the generated demodulation signal. And a transmission / reception device that transmits and receives transmission data and reception data in a half-duplex mode, wherein the reception data demodulated by the demodulation unit when a predetermined time has elapsed after the phase change of the carrier by the modulation unit is predetermined. A data conversion unit is provided which determines a predetermined value and converts received data demodulated after the determination into a value capable of maintaining a relative relationship with the determined value.

In general, when transmitting and receiving by the half-duplex method, a pause time longer than a time corresponding to one data slot is provided from the end of transmission to the start of reception. In this transmission / reception device, the data conversion unit determines the reception data demodulated by the demodulation unit to a predetermined value when a predetermined time has elapsed from when the phase of the carrier is changed by the modulation unit. In this case, it is preferable that the predetermined time is a time required for the phase of the demodulation signal generated by the demodulation signal generation unit to be completely stabilized. Next, the data conversion unit converts the received data after the determination into a value that can maintain a relative relationship with the determined value. That is, for example, when the received data is binary data, the data conversion unit determines the value 0 of the received data as the value 1 and sets the value 0 in the subsequent received data to the value 0.
And value 1 are converted to value 1 and value 0, respectively. In this case, for example, by setting the value to be determined to a value used during the idle period between transmission and reception, even if the phase of the demodulation signal is inverted from the original phase,
It becomes possible to receive received data accurately.

According to a second aspect of the present invention, in the transmission / reception apparatus according to the first aspect, the data converter determines the reception data to a predetermined value every time a predetermined time elapses from the last phase change in each transmission. It is characterized by doing.

After a lapse of a predetermined time from the time when the phase change occurs at the end of the transmission data, the phase of the demodulated signal generated by the demodulated signal generating section is stabilized. Therefore, by determining the received data every time a predetermined time has elapsed since the last phase change at the time of each transmission, the relative phase relationship of the subsequently demodulated received data is accurately maintained. As a result, control can be performed more easily than in the case where the phase is determined every time the phase changes within one transmission time.

According to a third aspect of the present invention, there is provided the transmission / reception apparatus according to the first or second aspect, wherein the transmission data and the reception data are each constituted by a data structure adaptable to a start-stop synchronization system, and the data conversion unit comprises a data structure. Is characterized in that the received data is determined to a value corresponding to the no signal in.

The transmission / reception apparatus according to the first aspect is applicable to all communications using the half-duplex system. On the other hand, in the case of transmission / reception by the start-stop synchronization method, the value of the data in the pause period from the end of transmission to the reception is defined as 1 in advance. Therefore, as long as it is used for transmission / reception by the start-stop synchronization method, it is possible to preset the final value of the received data to the value 1 at the time of shipment from the factory. As a result, the final value is individually set for each transmitting / receiving apparatus. It is possible to omit the troublesome work of performing.

According to a fourth aspect of the present invention, in the transmission and reception apparatus according to any one of the first to third aspects, the transmission-side power coupling unit and the reception-side power coupling unit are respectively a primary winding and a secondary winding of a high-frequency transformer. A winding is formed, and a carrier component of the high-frequency signal is supplied as electric power on the receiving device side.

[0017]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention applied to a non-contact type IC card reader. The same components as those in the conventional system 100 and the various signals used are denoted by the same reference numerals, and redundant description will be omitted.

First, the system configuration of a non-contact type IC card reader will be described with reference to FIGS.

As shown in FIG. 1, the non-contact type IC card reader system has a
A power transmission device (corresponding to a transmission / reception device in the present invention) 1 is configured to supply power of W to 300 mW and to be able to access the IC card 2.

As shown in FIG. 1, the power transmission apparatus 1 includes an interface section 11, a phase modulation section 12 corresponding to a modulation section in the present invention, a power transmission section 13, and an antenna corresponding to a transmission-side power coupling section in the present invention. Unit 14, receiving unit 15
And a control unit 16.

The interface unit 11 includes a CPU 21. The CPU 21 transmits and receives various control data and card data to and from a management device (not shown) via a communication port. Specifically, the CPU 21
Accesses the IC card 2 (see FIG. 2) by outputting predetermined transmission data SD to the control unit 16 in accordance with the control data transmitted by the management device, and reads customer information and balance information in the IC card 2. Control and write control of new balance information and the like are executed. The phase modulation unit 12 divides the frequency of the input 9.8304 MHz clock signal CL by two, and controls the divided carrier signal CR by the control unit 16.
Phase modulation based on the transmission data SD input through the RF signal, the high-frequency signals RF1, RF orthogonal to each other
Generate 2.

The power transmission unit 13 corresponds to a high-frequency amplifier in the present invention and amplifies high-frequency signals RF1 and RF2, respectively, and the high-frequency amplifiers 31 and 32 correspond to a matching unit in the present invention. Antenna matching circuits 33 and 34 for matching between the antenna units 14 and a constant current supply circuit 35 for supplying a constant current to the high frequency amplifier circuits 31 and 32 are provided. The antenna unit 14 includes primary windings 41 and 42 that can be magnetically coupled to a secondary winding of a high-frequency transformer provided on the IC card 2 side. In this case, the primary windings 41, 41 are formed by a spirally formed print pattern on a printed circuit board, and a magnetic core (not shown) is provided at the center of the spiral pattern.

The receiving section 15 includes a reception detecting circuit 51 corresponding to an amplitude signal detecting section in the present invention, a carrier synchronizing circuit 52 corresponding to a demodulated signal generating section in the present invention, and a phase detecting circuit corresponding to a demodulating section in the present invention. And a circuit 53.

The control section 16 corresponds to a data conversion section in the present invention, and oscillates a transmission data sampling circuit 61, a timing control circuit 62, and a clock signal CL serving as a reference of a sampling signal at the time of sampling described later to perform timing control. An oscillator 63 for outputting to the circuit 62 and a reception data conversion circuit 64 are provided. Here, the transmission data sampling circuit 61 receives the transmission data SD output from the CPU 21 and formed by the data structure of the start-stop synchronization system, detects a phase change point of the transmission data SD, and performs timing control as the phase change data PD. Output to the circuit 62. After a lapse of a predetermined time from the input of the phase change data PD, the timing control circuit 62 outputs a phase determination control signal PLS reception data conversion circuit 64 described later.
Output to The reception data conversion circuit 64 determines the reception data RD output from the phase detection circuit 53 to a value of 1 when the phase determination control signal PLS is input. Further, the reception data conversion circuit 64 converts the reception data RD into a value corresponding to the determined predetermined value every predetermined time.

Next, regarding the internal configuration of the IC card 2,
This will be described with reference to FIG.

As shown in FIG. 1, the IC card 2 includes an antenna unit 71 and an electronic circuit unit 72. The antenna unit 71 includes a secondary winding 8 that can be magnetically coupled with the primary windings 41 and 42 of the antenna unit 14 in the power transmission device 1.
1 and 82, and the primary windings 41 and 42 and the secondary windings 81 and 82 form a high-frequency transformer.

The electronic circuit section 72 includes power receiving circuits 91 and 92,
A constant voltage circuit 93, an initialization circuit 94, a phase detection circuit 95,
A clock generation circuit 96, a data demodulation circuit 97, a signal processing circuit 98, and an amplitude modulation circuit 99 are provided. Here, the power receiving circuits 91 and 92 are each constituted by a rectifier circuit using a diode bridge, and output a direct current generated by rectifying the high-frequency signals RF11 and 12 input via the antenna unit 71 to the constant voltage circuit 93 and , And outputs the high-frequency signals RF11 and RF12 to the phase detection circuit 95. The constant voltage circuit 93 generates a DC power supply stabilized at a predetermined voltage and outputs it as a power supply for each circuit in the IC card 2. The initialization circuit 94 resets the signal processing circuit 98 by outputting a reset signal RS when a predetermined voltage is input.

The phase detection circuit 95 demodulates the input high-frequency signals RF11 and RF12 by phase detection to receive data RD11 and outputs the received data RD11 to the data demodulation circuit 97, and also converts the high-frequency signals RF1 and RF2 to the clock generation circuit 9
6 is output. The clock generation circuit 96 outputs the high-frequency signal R
By calculating the exclusive OR of F1 and RF2 and dividing the frequency by two, an internal clock signal CLI of 4.9152 MHz for controlling itself is generated, and the generated internal clock signal CLI is transmitted to the data demodulation circuit 97 and the signal demodulation circuit 97. Processing circuit 9
8 is output. The data demodulation circuit 97 reads the reception data RD11 in synchronization with the internal clock signal CLI, demodulates the transmission data SD, and demodulates the transmission data SD.
D is output to the signal processing circuit 98. Signal processing circuit 98
Is configured to include a CPU, and executes a predetermined process according to the transmission data SD. Also, the signal processing circuit 98
Generates a reference subcarrier RSCR of 307.2 KHz by dividing the internal clock signal CLI by 16, performs phase modulation on the generated reference subcarrier RSCR based on answerback transmission data, and performs phase modulation on the subcarrier RSCR. The carrier SCR is output to the amplitude modulation circuit 99. In this case, the signal processing circuit 98 phase-modulates the reference subcarrier RSCR by 180 ° at the data change point of the answerback transmission data. Amplitude modulation circuit 99
Changes the load impedance of the secondary windings 81 and 82 via the power receiving circuits 91 and 92 by changing the internal impedance in synchronization with the H signal and the L signal of the subcarrier SCR. Thereby, the high frequency signal RF1
1 and RF12 are amplitude-modulated in synchronization with the subcarrier SCR as shown in FIG.

Next, the overall operation of the non-contact type IC card reader will be described. The power transmission device 1
Since the transmission from the IC card 2 and the reception and transmission operations in the IC card 2 are the same as the operations in the non-contact IC card reader system 100 described above, only the reception operation in the power transmission device 1 is described with reference to FIGS. I will explain.

In this non-contact type IC card reader, transmission and reception are performed by a half-duplex start-stop synchronization method with a communication speed of 9800 BPS. In this case, in the start-stop synchronization method, as shown in FIG.
Since E is added, from the end of transmission of the transmission data SD to the reception of the start bit RDS of the reception data RD, there is a pause time tr equal to or longer than one data slot. , The value is maintained at one. On the premise of these, the power transmission device 1 executes the following processing.

When the transmission data SD is output from the CPU 21, the transmission data sampling circuit 61 detects a phase change point of the transmission data SD, and outputs the phase change data PD to the timing control circuit 62 each time. Therefore, the transmission data sampling circuit 61 outputs the transmission data S
When the bit data SDE1 immediately before the stop bit SDE in D is 0, the phase data PD is output at times t ₁ and t _{2 as shown} in FIG. On the other hand, when the phase of the transmission data SD changes, the clock signal D generated by the carrier synchronization circuit 52 is changed.
As shown in FIG. 3D, the phase of CL is shifted in phase as compared with the case where the phase is normally locked. In this case, the phase detection circuit 53 performs phase detection by exclusive OR of the subcarrier SCR (see FIG. 3C) output from the reception detection circuit 51 and the clock signal DCL. For this reason, when the phase of the clock signal DCL is shifted by 180 ° from the original phase, the data that should be detected as the value 1 is the value 0 as shown in the part B of FIG. Is detected as In this case, a particular problem is that an incorrect value is continuously detected unless the phase is once shifted by 180 ° and then the phase is correctly locked again. Therefore, if the reception data RD that has been erroneously detected is input to the CPU 21, a reception error occurs.

[0032] The In the power transmission device 1, the timing control circuit 62, the phase change data PD from time to time enter t ₁ has passed the predetermined time t ₁₂ to the phase determined control signal PL
S is output to the reception data conversion circuit 64. Next, the reception data conversion circuit 64 samples the reception data RD output from the phase detection circuit 53 when the phase determination control signal PLS is input, and determines the sampling value as an initial value to a value of 1. In this case, the predetermined time is set to a time that exceeds at least the lock-up time of the DPLL in the carrier synchronization circuit 52. Then, reception data converting circuit 64, in the same manner as a general data sampling, sampling the received data RD from the edge change at t ₀₁ the received data RD for each elapse of a predetermined time to remove the noise N, These values are converted so that the relative relationship with the determined sampling value is maintained. In this case, the predetermined time is set after the phase is determined and shorter than the time corresponding to one data slot. Since in this case, the phase change data PD at time t ₂ after the time t ₁₂ is input,
The sampling of the reception data RD is temporarily stopped.

Next, when the phase change data PD is input at time t ₂ , the timing control circuit 62 outputs a phase determination control signal PLS to the reception data conversion circuit 64. Next, the reception data conversion circuit 64 operates at the time t.
After determining again the received data RD to the value 1 at _21, the time has elapsed a predetermined time from an edge change at t ₀₂ t ₂₂ ,,
t ₂₃ samples the received data RD at the time of ..., to the value of the received data RD sampled, converted to a relative relationship between the value 1 finalized is maintained. That is, the reception data conversion circuit 64 outputs the reception data RD having the value 0.
Is determined to be the value 1, the subsequent reception data RD
Are converted to values 1 and 0, respectively. Thus, received data RD at time t ₂₂ and time t ₂₃ is converted into respective values 1 and the value 0. As a result, the reception data RD is converted into the reception data RD1 having a normal value as shown in FIG.
Output to PU21.

Since the CPU 21 itself is transmitting the received data RD sampled at the time t ₁₂ , the CPU 21 receives the received data RD transmitted from the IC card 2.
If not, discard it. Then, the reception data RD sampled at time t _22, t ₂₃ · · after being determined at time t ₂₁ are the input to the after end of transmission data, handled as received data RD from the IC card 2, It is stored in an internal RAM (not shown).

As a result of the above processing, the CPU 21
Can receive the reception data RD1 without causing a reception error. Here, the reception error can be prevented for the following reasons. That is, in the start-stop synchronization method, the reception data RD1 input after the transmission data SD is changed in phase is always defined as the value 1. Therefore, the clock signal DCL phase stable even value if the value 0 of the received data RD output from the phase detection circuit 53 in The times t ₂₁ value 1
If the relative value between the determined value and the value of the received data RD input thereafter is maintained, the value of the received data RD can be accurately received.

Note that the present invention is not limited to the above-described configuration and processing, and can be appropriately changed. For example, in the power transmission apparatus 1, the above-described data determination processing is performed every time the phase of the transmission data SD changes, but can be performed only when the phase of the transmission data SD last changes. That is, since the control unit 16 cannot grasp when the last phase change data PD is input, the data determination processing is performed for each phase change of the transmission data SD. As shown by the broken line 1, the phase change data PD may be directly output to the timing control circuit 62. In this case,
The transmission data sampling circuit 61 can be omitted, and the control of the phase determination processing for the reception data conversion circuit 64 becomes easy.

Further, in the embodiment of the present invention, an example in which the present invention is applied to a non-contact type IC card reader has been described. However, the present invention is not limited to this. A telephone charging system that transmits high-frequency power and converts the transmitted high-frequency power to charging power,
The present invention can be applied to a heating device for a toilet seat, and can be applied to all devices that transmit and receive a high-frequency signal by coupling means on the transmission side and the reception side in non-contact or contact with each other.

[0038]

As described above, according to the transmission / reception apparatus of the first aspect, the data conversion unit determines the reception data demodulated by the demodulation unit when a predetermined time has elapsed after the phase change of the carrier by the modulation unit. And the received data demodulated after the determination is converted to a value that can maintain the relative relationship with the determined value, whereby the phase of the demodulation signal is inverted from the original phase. However, even if it is, the received data can be accurately received.

According to the transmission / reception device of the second aspect, the data conversion unit determines the reception data to a predetermined value every time a predetermined time elapses from the last phase change at the time of each transmission. Can be easily controlled, as compared with the case where it is determined every time the value changes.

According to the third aspect of the present invention, the transmission data and the reception data have a data structure compatible with the start-stop synchronization method, and the data conversion unit includes:
By determining the received data to a value corresponding to no signal in the data structure, the determined value can be set uniformly and easily.

Further, according to the transmission / reception device of the fourth aspect, the transmission-side power coupling unit and the reception-side power coupling unit constitute the primary winding and the secondary winding of the high-frequency transformer, respectively, so that the carrier wave of the high-frequency signal can be obtained. As a result, the components can be supplied as power on the receiving device side, so that the component can be suitably used as a transmitting device of a power transmission system.

[Brief description of the drawings]

FIG. 1 is a block diagram of a power transmission device in a contactless IC card reader according to an embodiment of the present invention.

FIG. 2 is a block diagram of an IC card in the non-contact type IC card reader according to the embodiment of the present invention.

FIG. 3 is a signal waveform diagram showing a temporal relationship between transmission data SD and reception data RD in the start-stop synchronization method.

FIG. 4A shows a stop bit SD of transmission data SD.
E, a signal waveform diagram near the start bit RDS of the received data RD, (c) a signal waveform diagram of the subcarrier SCR, (d) a signal waveform diagram of the clock signal DCL, and (e). ) Is a signal waveform diagram of the reception data RD,
(F) is a signal waveform diagram of the converted reception data RD1.

FIG. 5 is a signal waveform diagram of each unit in the non-contact IC card reader according to the embodiment of the present invention and a non-contact IC card reader system already developed by the applicant;
(A) is a signal waveform diagram of the transmission data SD, (b) is a signal waveform diagram of the clock signal CL, (c) is a signal waveform diagram of the carrier signal CR, (d) is a signal waveform diagram of the high-frequency signal RF1,
(E) is a signal waveform diagram of the high-frequency signal RF2, (f) is a signal waveform diagram of the reference subcarrier RSCR, (g) is a signal waveform diagram of the subcarrier SCR, and (h) is a high-frequency signal RF1
1, RF12 signal waveform diagram, (i) shows subcarrier SC
FIG. 7J is a signal waveform diagram of the clock signal DCL, and FIG. 7K is a signal waveform diagram of the received data RD.

FIG. 6 is a block diagram of a contactless IC card reader system already developed by the applicant.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 power transmission device 2 IC card 12 phase modulation unit 14 antenna unit 16 control unit 31 high-frequency amplification circuit 32 high-frequency amplification circuit 33 antenna matching circuit 34 antenna matching circuit 51 reception detection circuit 52 carrier synchronization circuit 53 phase detection circuit 61 transmission data sampling circuit 62 Timing control circuit 64 Receive data conversion circuit

Claims (4)

[Claims] 1. A modulation section for generating a high-frequency signal by phase-modulating a carrier based on transmission data, a high-frequency amplification section for amplifying the high-frequency signal, and a reception-side power coupling section provided on a reception device side. A transmission-side power coupling unit configured to be coupled to the radio-frequency amplification unit and outputting an amplified high-frequency signal amplified by the high-frequency amplification unit to the reception-side power coupling unit; and capable of matching the high-frequency amplification unit and the transmission-side power coupling unit. A matching unit, an amplitude signal detecting unit that detects an amplitude signal from the amplified high-frequency signal that is amplitude-modulated by the receiving device based on received data, and a demodulation signal that is phase-synchronized with a fundamental frequency signal of the detected amplitude signal. A demodulation signal generation unit for generating, and a demodulation unit for demodulating the received data by performing phase detection of the amplitude signal based on the generated demodulation signal, A transmission / reception apparatus for transmitting and receiving transmission data and the reception data in a half-duplex mode, wherein a predetermined time is used to determine the reception data demodulated by the demodulation section when a predetermined time has elapsed from a phase change of the carrier by the modulation section. A transmission / reception apparatus comprising: a data conversion unit that determines a value and converts the received data demodulated after the determination into a value that can maintain a relative relationship with the determined value. 2. The transmission / reception according to claim 1, wherein the data conversion unit determines the reception data to the predetermined value every time the predetermined time elapses from the last phase change in each transmission. apparatus. 3. The transmission data and the reception data are each constituted by a data structure adaptable to a start-stop synchronization method, and the data conversion unit determines the reception data to a value corresponding to a no signal in the data structure. The transmission / reception device according to claim 1 or 2, wherein: 4. The transmission-side power coupling section and the reception-side power coupling section constitute a primary winding and a secondary winding of a high-frequency transformer, respectively, and a carrier component of the high-frequency signal is used as power on the receiving device side. The transmission / reception device according to claim 1, wherein the transmission / reception device is supplied.