JPH1141129A - Balance mixer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a balance mixer circuit which efficiently reduces distortion that is caused by mixing of an input signal and a local oscillator signal. SOLUTION: A test signal generation circuit 10 supplies a test signal to an amplifier 9 at the time of starting or non-communication of information, and 1st and 2nd mixers 2 and 4 mix signals which are and are not performed phase inversion by an inverter 3 with a local oscillator signal and are respectively given to addition circuits 5 (5a and 5b). The circuits 5 add two mixed signals and output an addition signal 5a1. This addition output is detected by a distortion detection circuit 12, and a detection result is given to a sensitivity control circuit 13. The circuit 13 generates sensitivity control signals 13b and 13a to the mixers 2 and 4 and gives them.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a balance mixer circuit, and more particularly, to a quadrature balance mixer circuit, a double balance mixer circuit, a receiving device, and a recording medium on which a balance mixer control program is recorded.
For example, the present invention can be applied to a wireless communication device employing a direct conversion method.

[0002]

2. Description of the Related Art Conventionally, in a receiving section of a communication device, distortion generated in a mixer section is designed by optimizing a signal level applied to the mixer and a level of a local oscillator, and a distortion characteristic due to a change over time or a change in temperature of a circuit. It has not been easy to actively compensate for the deterioration of.

[0003] In particular, in the receiver of the direct conversion system in which the receiving frequency is directly converted to the base frequency, the secondary distortion of the mixer has been a problem.

[0004]

A mixer that performs frequency conversion to a base frequency for a receiver that handles a modulation method involving amplitude fluctuations has a local oscillation frequency and a mixer input frequency of the same frequency. The generation of secondary distortion has been a problem.

[0005] For example, FIG. 2 is a configuration diagram of a conventional balance mixer circuit 7 used in a receiver. This will be described with reference to FIG. The received signal 1a is applied to the signal input terminal 1 and the signal is branched into two, one of which is the first signal.
, And the other is inverted in phase by a phase inversion circuit 3 and applied to a second mixer 4. First mixer 2 and second mixer
Is supplied with a local oscillation signal from a local oscillator 6.

The signal applied to the first mixer 2 is designated as e1, and the signal applied to the second mixer 4 is designated as -e2. Assuming that the secondary conversion coefficient of the first mixer 2 is k1 and the secondary conversion coefficient of the second mixer 4 is k2, it can be expressed as follows.

[0007]

[Equation 1] e1 = A1 (t) cos {ωt + Φ (t)} (1)

[0008]

[Equation 2] e2 = A2 (t) cos {ωt + Φ (t)} (2) The local oscillation signal is set to eLo, and each mixer is set to eLo1 and eLo.
Suppose 2 is added.

[0009]

ELo1 = B1cos (ωt), eLo2 = B2cos (ωt) (3) From these equations, the mixer output eo can be expressed by the following equation.

[0010]

Equation 4] eo = k1 (e1 + eLo1) 2 -k2 (-e2 + eLo2) 2 = k1 (2 × e1 × eLo1 + e1 2 + eLo1 2) - k2 (-2 × e2 × eLo2 + e2 2 + eLo2 ² ) ・ ・ ・ ・ (4) When extracting only the base frequency signal,

[0011]

Eo = k1A1 (t) B1cos {Φ (t)} + k2A2 (t) B2cos {Φ (t)} + 1 / 2k1A1 ² (t) -1 / 2k2A2 ² (t) + 1 / 2k1B1 ² -1 / 2k2B2 ² ... (5) The first and second terms of the equation (5) are the mixer output converted to the basic frequency required by the mixer. The third and fourth terms are signals output by squaring the input signals of the first mixer 2 and the second mixer 4 themselves. The fifth and sixth terms are DC components output by squaring the local oscillation signal. The signals of the third and fourth terms are interference components due to second-order distortion, and the signals of the fifth and sixth terms are
The term is a DC offset due to the local oscillation signal.

Ideally, A1 = A2, k1 = k2 and B1 = B2
Needs to be However, the conversion coefficient k of the mixer
The magnitude of the signal of the third term differs from the magnitude of the signal of the fourth term due to the variation of 1, k2 and the loss of the phase inversion circuit 3.
Is output without being canceled. The same applies to B1 and B2.

FIG. 3 shows the basic signal output and A2 when A1 = A2, B1 = B2, the respective conversion coefficients are K1 = 10 dB, k2 = 9.5 dB, and the secondary intercept point of each mixer is 10 dBm.
It is a figure showing an example of the next distortion output. In FIG. 3, when the mixer input level is -20 dBm, the first mixer 2, the second mixer 4 and the addition output
The fundamental wave of 5a1 is -10 dBm, -10.5 dBm, and about -7 dBm, respectively.
-20dBm in the second mixer, -2 in the second mixer
It can be seen that 0.5 dBm and -55 dBm at the added output 5a1.

At the added output 5a1, the fundamental wave and the distortion component have a difference of 43 dB. This second-order distortion signal has a signal of 2
Since the signal is output after being multiplied, even the adjacent channel signal of the own station frequency in the radio frequency band falls to the base frequency band. In order to avoid this, there is a heterodyne reception system in which an intermediate frequency is provided. In the direct conversion receiving method, since a channel filter is often provided only in the base frequency band, a problem arises when there is an adjacent interference signal larger than the frequency signal of the own station in the adjacent frequency channel, and the second-order distortion component is no longer filtered. Removal becomes impossible by means or the like. The variation in these conversion factors is
This is due to variations in temperature and circuit components.

[0015] In view of the above, realization of a balance mixer circuit, a quadrature balance mixer circuit, a double balance mixer circuit, a receiving device, and the like for efficiently reducing distortion due to mixing of an input signal and a local oscillation signal is demanded. .

[0016]

SUMMARY OF THE INVENTION Therefore, the present invention provides a first mixer for mixing an input signal and a local oscillation signal, and a first mixer for mixing the input signal and the local oscillation signal in a 180-degree phase shift relationship with the first mixer. In a balanced mixer circuit including a second mixer that performs mixing, and an adding unit that adds an output signal of the first mixer and an output signal of the second mixer, the above-described problem is solved by the following characteristic configuration. I do.

That is, according to the present invention, the balanced mixer circuit comprises: (1) test signal generating means for generating a test signal for performing distortion compensation for the first mixer and the second mixer; (3) a distortion amount detecting means for detecting an amount of distortion from an output signal of the first mixer and the second mixer or an output signal of the adding means when the signal is supplied to the first mixer and the second mixer; A sensitivity control amount signal for the first mixer and the second mixer or the adding means is determined from a distortion amount when the test signal is supplied to the first mixer and the second mixer, and the sensitivity determined when a non-test signal is input. And sensitivity control means for controlling the sensitivity of the first mixer and the second mixer or the addition means with the control amount signal.

By adopting such a configuration, the amount of distortion output from the first mixer and the second mixer can be detected by the output signal of the adding means, and the optimum sensitivity is determined according to the amount of distortion. A control signal can be generated to control the first mixer and the second mixer to suppress distortion.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a preferred embodiment of the present invention will be described with reference to the drawings. In the present embodiment, in a receiving apparatus having a balance mixer having at least two mixers for mixing a received signal and a local oscillation signal, a test signal is added to the input of the receiving apparatus, and distortion of the balanced mixer is detected based on the test signal. A sensitivity control circuit for controlling the amount of distortion of the two mixers based on the result of the distortion detection circuit. The two mixers control the magnitude of the distortion by a sensitivity control signal, and phase-shift the distortion components of the mixers with each other. It is configured to include a balance mixer for adding in an inverted state. This suppresses distortion.

In order to prevent the occurrence of secondary distortion due to aging or temperature change, a test signal is generated at startup and / or at the time of non-information communication (at the time of non-information communication), so that the distortion component becomes less than a predetermined value. It controls so that it becomes. As a result, a receiving device having no intermediate frequency can be configured.

More specifically, the sensitivity control signal is updated at the time of starting the receiving apparatus and / or at the time of non-information communication.

Further, the balance mixer circuit is provided with gain variable means which can be independently controlled at the signal input terminals of the respective mixers, so that the gain is controlled by a sensitivity control signal generated based on the distortion amount.

Alternatively, the balance mixer circuit is provided with gain varying means independently at the signal input terminal of each mixer, so that the gain is controlled by a sensitivity control signal generated based on the distortion amount.

Further, the balance mixer circuit is provided with gain variable means for each mixer output so that the gain is controlled and added by a sensitivity control signal generated based on the distortion amount.

Further, the balance mixer circuit is provided with an adder comprising a variable gain differential operational amplifier at the output of each mixer, and the gain of the variable gain differential operational amplifier is controlled by a sensitivity control signal generated based on the amount of distortion. The configuration is as follows.

Further, the balance mixer circuit is constituted by an emitter-coupled transistor pair circuit, and is configured such that the base bias of each transistor is independently controlled by a sensitivity control signal generated based on the distortion amount as a distortion amount control method.

Further, the balance mixer circuit has a source coupling
A FET pair circuit is used, and as a distortion control method, the gate bias of each FET is independently controlled by a sensitivity control signal generated based on the amount of distortion.

Further, the balance mixer circuit has a Gilbert cell configuration including two differential pair amplifiers. As a distortion control method, the current of each differential pair amplifier is independently controlled by a sensitivity control signal generated based on the amount of distortion. It is constituted so that.

Further, the balance mixer circuit is an emitter-coupled transistor pair circuit, and the distortion control method is configured to independently control the collector voltage of each transistor by a sensitivity control signal generated based on the amount of distortion.

The balance mixer circuit has a source coupling
An FET pair circuit is used, and as a distortion control method, the drain voltage of each FET is independently controlled by a sensitivity control signal generated based on the distortion amount.

Further, in the balance mixer circuit, an A / D converter is provided at the output of each mixer, the A / D conversion output is taken into a digital signal processor, and each is taken in by a sensitivity control signal generated based on the amount of distortion. A standardization operation is performed so that distortion components of signals are equal, and an addition is performed so that distortion is canceled.

Furthermore, as a distortion detection method, a modulated signal having a line spectrum of two or more signal inputs or two or more
A CW wave (continuous wave) is added as a test signal, and a local oscillation signal is further applied to a local oscillation signal input terminal of the balance mixer.
Distortion component detection filtering means is provided at the output of the balance mixer circuit, and the distortion detection method is configured so that the output of the distortion component detection filtering means is used as a detection signal.

As a distortion detection method, a modulation signal having a line spectrum of two or more signal inputs or two or more CW waves (continuous waves) is added as a test signal, and a local oscillation signal is further input to a local oscillation signal input terminal of the balance mixer circuit. In addition, distortion component detection filtering means is provided at each mixer output of the balanced mixer circuit, and the output of the distortion component detection filtering means is used as a detection signal.

As a distortion detection method, a modulation signal having a line spectrum of two or more signal inputs or two or more CW waves (continuous waves) is added to a receiving device as a test signal, and a local oscillation signal input terminal of a balance mixer circuit is further added. A local oscillator signal is added to the A / D converter at each mixer output of the balanced mixer circuit, and the A / D converter outputs the data to a digital signal processor. And a distortion detection circuit for detecting the amount of distortion of each mixer.

Further, as a distortion detection method, a modulated signal or a modulated signal having a line spectrum of two or more signal inputs to a receiving apparatus is used.
The above CW wave (continuous wave) is applied as a test signal, a local oscillation signal is applied to the local oscillation signal input terminal of the balance mixer circuit, and an A / D converter is provided at the output of the balance mixer circuit. The output is taken into a digital signal processor, a Fourier transform operation such as FFT is performed by a program incorporated in the digital signal processor, and a distortion detection circuit is configured to detect a distortion amount of the balance mixer circuit. Next, a more specific description will be given with reference to the drawings.

FIG. 1 is a configuration diagram of the balance mixer circuit 16 of the first embodiment. The balance mixer circuit 16 has a first
A local oscillator 6 for providing a local oscillation signal 6a to the first mixer 2 and the second mixer 4 including a balance mixer 7 comprising a mixer 2, a phase inversion circuit 3, a second mixer 4 and an addition circuit 5. A start-up / non-information communication detection circuit 15 for detecting start-up detection / non-information communication time, and a test signal generation circuit 10
And a switch 8 for selecting a test signal or an input signal 1a and supplying the selected signal to an amplifier 9, and a compensation control circuit for controlling the switch 8.
14, a distortion detection circuit 12 for detecting the amount of distortion of the output signal of the balance mixer 7, a sensitivity control circuit 13 for controlling the sensitivity of the balance mixer 7, and the like.

In FIG. 1, an input signal is input to a signal input terminal 1.
1a is applied to one input terminal 8c, 8a of the switch 8, and is applied to the signal input terminal 7a of the balance mixer 7 through the amplifier 9. On the other hand, a test signal from a test signal generation circuit 10 is applied to the other input terminal 8b of the switch 8. The balance mixer 7 divides the input signal into two, and applies one to the first mixer 2 and the other to the second mixer 4 through the phase inversion circuit 3. The output signal of the second mixer 4 is applied to the inverting input terminal 5a of the adding circuit 5, and the output signal of the first mixer 2 is applied to the other non-inverting input terminal 5b of the adding circuit 5. The output signal of the addition circuit 5 is output to the output terminal 11 as the output signal of the balance mixer 7.

Further, the balance mixer output signal from the output terminal 11 is applied to the distortion detection circuit 12, and the detection result 12a is supplied to the sensitivity control circuit 13. The sensitivity control circuit 13 is a compensation control circuit
A sensitivity control signal 13a for controlling the sensitivities of the first mixer 2 and the second mixer 4 based on the control signal 14a from
, 13b.

On the other hand, the compensation control circuit 14 starts the compensation control circuit 14 based on the detection result 15a of the start-up / non-information communication time detection circuit 15, and sends the start control signal 14b to the test signal generation circuit 10.
And a control signal 14c is also supplied to the switch 8 to switch to the test signal generation circuit 10 side, so that the distortion compensation operation is performed.

In the first mixer 2 and the second mixer 4, the conversion coefficients k 1 and k 2 of the above equation (5) are controlled by sensitivity control signals 13 a and 13 b from the sensitivity control circuit 13. When a normal random modulation signal is input to the distortion detection circuit 12 connected to the output terminal 11, as is apparent from the above equation (5), the basic signal of the first and second terms and the third Term and fourth
Since the distortion signal of the term cannot be distinguished, the following test signal is used. That is, two CWs (continuous waves) having different frequencies are used as test signals.

The output signal 6a of the local oscillator 6 is 1000 MHz, and the test signal frequency is two waves of 1001 MHz and 1001.1 MHz. As a result, the mixer output outputs a signal having a fundamental frequency component of 1 MHz and a signal having a frequency of 1.1 MHz.

The second-order distortion signal is a signal component having a frequency of 0.1 MHz, and can be separated by a filtering circuit or the like. The test signal may be a modulated signal obtained by applying carrier suppression amplitude modulation to a carrier frequency of 1001 MHz at a modulation frequency of 0.1 MHz. Therefore, the magnitude of the distortion component is detected by the distortion detection circuit 12 having the separation circuit for separating the distortion component. The balance mixer 7 is controlled by the sensitivity control circuit 13 so as to reduce the detected distortion component.

FIG. 4 is a configuration diagram of the balance mixer circuit 16C of the second embodiment. In FIG. 4, a balance mixer circuit 16C is a quadrature mixer circuit, and includes a balance mixer circuit 16A and a balance mixer circuit 16B, and is configured to convert a complex signal into a base frequency. The balance mixer circuit 16A has almost the same configuration as the balance mixer circuit 16 in FIG. 1 except that the distortion detection circuit 12A detects the output signals of both the balance mixer circuit 16A and the balance mixer circuit 16B and detects the signal. The result is given to the sensitivity control circuit 13A, and the sensitivity control circuit 13A is configured to control both the mixers of the balance mixer circuit 16A and the balance mixer circuit 16B, respectively.

The configuration of the balance mixer circuit 16C shown in FIG.
This is a configuration of a direct conversion mixer circuit that handles complex signals. The balance mixer circuits 16A and 16B are arranged so that the two balance mixer circuits 16A and 16B operate orthogonally, and the distortion components at the output terminals 11A and 11B of the respective balance mixer circuits 16A and 16B are reduced. Is controlled.

In order to operate the balance mixer circuit 16A and the balance mixer circuit 16B at right angles to each other, FIG. 4 shows an example in which the 90-degree phase shift circuit 17 is inserted into one of the branches of the output signal 6a of the local oscillator 6. However, as another example, the 90-degree phase shift circuit 17 may be inserted into any one of the paths for branching the output signal 9a of the amplifier 9 and supplying a signal to the balance mixer 7A and the balance mixer 7B. .

The phase inverting circuits 3A and 3B of the balance mixer 7A and the balance mixer 7B insert the input signal 9a into one of the branched paths, but use this as another example to output the output of the local oscillator 6. It is clear from the above-mentioned equation (4) that the same effect can be obtained even if the signal is inserted into either one of the branches.

FIG. 5 is a configuration diagram of the balance mixer circuit 16D of the third embodiment. In FIG. 5, FIG.
What is different from the configuration of the first embodiment is that the distortion detection circuit 12 is
Is replaced by Note that the start-up / non-information communication detection circuit 15, the compensation control circuit 14, and the test signal generation circuit 10
, The switch 8 and the amplifier 9 are not shown.

The balance mixer circuit 16D separates a distortion component when a test signal is added from the output signal of the balance mixer 7 by a filtering circuit 18 and detects the magnitude thereof. The detection result 18a is given to the sensitivity control circuit 13 to control the sensitivity.

FIG. 6 is a configuration diagram of a balance mixer circuit 16E according to the fourth embodiment. In FIG. 6, FIG.
This is different from the first embodiment in that first and second mixers 2 and 2 of the balance mixer 7 are provided on the input side of the adder circuit 5 by adding test signals and providing filtering circuits 18A and 18B as filtering circuits for distortion signals.
, The sensitivity signals of the first and second mixers 2 and 4 are controlled by the sensitivity control circuit 13 so that the magnitudes of the detected distortions are equal. With this configuration, the distortion component is canceled at the output of the adding circuit 5. When starting /
The non-information communication time detection circuit 15, the compensation control circuit 14, the test signal generation circuit 10, the switch 8, and the amplifier 9 are not shown.

FIG. 7 is a block diagram of the balance mixer circuit 16F of the fifth embodiment. 7 is different from the configuration of the above-described embodiment in that an analog / digital (A / D) conversion circuit 19 is provided in the output path of the addition circuit 5 of the balance mixer 7, and an output signal of the analog / digital conversion circuit 19 is provided. Into the digital signal processor circuit 20 and perform a Fourier operation by a program such as a built-in fast Fourier transform (FFT) operation to separate a fundamental component from a distortion component so that the separated distortion signal is minimized. This is to operate the sensitivity control circuit 13. The startup / non-information communication detection circuit 15, the compensation control circuit 14, the test signal generation circuit 10, the switch 8, and the amplifier 9 are not shown.

FIG. 8 is a control flowchart of the distortion compensation operation in the balance mixer circuit 16F of the fifth embodiment of FIG. First, the mixer output signal quantized by the analog / digital conversion circuit 19 is taken in a predetermined number of data (steps S10 and S20). Then, a fast Fourier calculation is performed to detect the magnitude of the distortion component (step S30).
Next, let C1 (n) be the distortion signal of the current balance mixer,
Using C1 (n-1) as the distortion signal of the previous balance mixer, the magnitude of the distortion component C1 (n
If the current magnitude C1 (n) of the distortion component is smaller than that in (-1), the control method controlled by the sensitivity control circuit 13 is the same (step S50). Magnitude of distortion component of fast Fourier transform operation result of
If the current magnitude C1 (n) of the distortion component is larger than C1 (n-1), control is performed with a predetermined magnitude in the direction opposite to the previously controlled method (step S60).

Next, it is confirmed whether or not the magnitude of the distortion component has become equal to or less than a predetermined value (step S70). If the magnitude has become equal to or less than the predetermined value, the control signal of the sensitivity control circuit 13 is fixed, and the test is terminated (step S70). Step S80). If not, the above steps S10 to S70 are repeated.

The control program for performing the processing shown in FIG. 8 is stored in a program ROM or the like, and can be executed by a microcomputer.

FIG. 9 is a block diagram of a balance mixer circuit 16G of the sixth embodiment. In FIG. 9, the difference from the above-described embodiment is that the output of the first
A digital conversion circuit 19A is provided, an analog / digital conversion circuit 19B is provided at the output of the second mixer 4, and the outputs of the analog / digital conversion circuits 19A and 19B are taken into a digital signal processor circuit 20A to output a mixer output signal. This is to output a sensitivity control signal. It should be noted that the start-up / non-information communication detection circuit 15, the compensation control circuit 14,
The test signal generation circuit 10, the switch 8, and the amplifier 9
Illustration is omitted.

FIG. 10 is a control flowchart of the distortion compensating operation of the balance mixer circuit 16G of the sixth embodiment of FIG. In FIG. 10, when a predetermined number of data is taken in the digital signal processor circuit 20A (steps S90 and S100), a fast Fourier operation is performed (step S1).
10) The distortion component D2 of the first mixer 2 and the distortion component D1 of the second mixer 4 are compared, and the magnitudes of the distortion components D1 and D2 are compared (step S120). A control signal 20Aa for decreasing the sensitivity of the second mixer 4 and / or increasing the sensitivity of the first mixer 2 is supplied to the sensitivity control circuit 13 (step S130). On the other hand, when the distortion component D2 is large,
A control signal 20Aa for lowering the sensitivity of the first mixer 2 and / or increasing the sensitivity of the second mixer 4 is supplied to a sensitivity control circuit 13
(Step S130).

Then, it is confirmed whether or not the magnitudes of the distortion components D1 and D2 have become equal to or smaller than a predetermined value (step S140). If the magnitude has become equal to or smaller than the predetermined value, the test is terminated (step S15).
0). If not, the above steps S90 to S140 are repeated.

The control program for performing the processing shown in FIG. 10 is stored in a program ROM or the like, and can be executed by a microcomputer.

FIG. 11 is a block diagram of a second embodiment of the balance mixer 7 described above. In FIG. 11, the balance mixer 7A is characterized in that the first mixer 2A is composed of a variable gain circuit 21 and a mixer 22, and the second mixer 4A is composed of a variable gain circuit 41 and a mixer 42. It is configured.

The input signal 7a is supplied to the variable gain circuit 21 and the phase inversion circuit 3. The phase inversion circuit 3 receives the input signal 7a
Is given to the variable gain circuit 41 after phase inversion. Variable gain circuit
The gain control signal 13 a is supplied from the sensitivity control circuit 13 to the gain control circuit 21, the gain control is performed on the input signal 7 a, and the gain control signal 13 a is output to the mixer 22. Then, the mixer 22 mixes the gain-controlled input signal with the local oscillation signal 6 a and supplies the mixed signal to the addition circuit 5.

The other gain variable circuit 41 is also used for the sensitivity control circuit 13
Supplies a gain control signal 13a from the phase inverting circuit 3 and outputs the same to the mixer 42 after performing gain control on the signal. Then, the mixer 42 mixes the gain-controlled phase inversion signal with the local oscillation signal 6a and supplies the signal to the addition circuit 5.

The magnitude of the second-order distortion of the mixers 22, 42 increases in proportion to the square of the input level, as is apparent from the above equation (5). Therefore, by inserting, for example, a variable attenuator as gain variable means at the inputs of the mixers 22 and 42, the magnitude of the distortion can be adjusted by changing the input levels of the respective mixers 22 and 42.

Further, gain control signals 13a and 13b which can be controlled independently are added to the first mixer 2A and the second mixer 4A,
What is necessary is just to control so that the distortion component in the output of the addition circuit 5 is minimized. The same effect can be obtained even if one of the gain control signals 13a and 13b is fixed and the other is variable.

FIG. 12 is a block diagram of a third embodiment of the balance mixer 7 described above. In FIG. 12, the balance mixer 7B is characteristically different from the above-described FIG. 11 in that the first mixer 2B replaces the connection order of the gain variable circuit 21 and the mixer 22 and performs processing by the mixer 22 after processing by the mixer 22. The variable mixer 21 is configured to perform gain control, and the second mixer 4B switches the connection order of the gain variable circuit 41 and the mixer 42 to
And the gain is controlled by the gain variable circuit 41. Then, the first mixer 2B and the second mixer 2B are controlled so that the magnitude of the distortion is minimized at the output of the adding circuit 5.
It is configured to control the output of the mixer 4B.

FIG. 13 is a block diagram of a fourth embodiment of the balance mixer 7 described above. In FIG. 13, in the balance mixer 7C, a gain variable circuit 21 for the first mixer 22 is provided on the local oscillation signal input side, and a gain variable circuit 41 for the first mixer 42 is also provided on the local oscillation signal input side. That is, the local oscillation signal 6a is provided to the gain variable circuits 21 and 41, and the gain variable circuit 21
6a is gain-controlled and given to the first mixer 22. On the other hand, the gain variable circuit 41 also controls the local oscillation signal by the gain control signal 13b.
6a is gain-controlled and given to the second mixer 42. The output of the first mixer 22 and the output signal of the second mixer 42 are added by the adding circuit 5 and output.

Changing the level of the local oscillation signal 6a applied to the mixers 22 and 42 is appropriate from the above equation (5). Therefore, the amount of distortion of the outputs of the mixers 22 and 42 can be controlled, and the distortion of the output of the adder circuit 5 can be reduced.

FIG. 14 is a block diagram of a fifth embodiment of the balance mixer 7 described above. In FIG. 14, the balance mixer 7D and particularly the adder circuit 5A are described in detail. The output signals of the mixers 2 and 4 are added and output by the operational amplifier 51 under the control of the gain control circuit 5B. The output signals of the mixers 2 and 4 are supplied to terminals 52 and 53 of the adder circuit 5A, and are connected to resistors R20, R21, R22 and R23 connected to the operational amplifier 51.
The gain control of addition is performed according to the value of. In gain control, a gain control signal is output by a control signal applied to a control input terminal 5B1 of the gain control circuit 5B, and the addition circuit 5A
, And the resistance of the resistor R20 is controlled. By doing so, it is clear that the magnitude of the distortion component of the mixer output signal can be controlled.

FIG. 15 shows the resistor of the adder circuit 5A of FIG.
It is a specific block diagram of R20. In FIG. 15, a resistor R20 connects one of the resistors R20-a to R20-n to a control terminal.
The switch 55 may be switched by the gain control signal applied to 54 and connected to a desired resistor to determine the resistance value of the resistor R20.

Although the operation of switching the resistor by the switch 55 has been described, the same effect can be obtained even if the resistance value is equivalently changed by changing the bias current of the PIN diode or the like.

FIG. 16 is a circuit diagram of a sixth embodiment of the balance mixer. In FIG. 16, the balance mixer
7E is a differential connection by bipolar transistors Q1 and Q2, a constant current circuit by bipolar transistor Q3,
It comprises an adder circuit 51 for outputting a mixer and a bias control circuit 52. To the input terminals 7a1 and 7a2, input signals whose phases are inverted from each other are applied, and the local oscillation signal input terminals
The local oscillation signal is applied to 61 and applied to the base of bipolar transistor Q3 through resistor R6. The emitter of the bipolar transistor Q3 is grounded through a resistor R5.

A bias voltage for controlling the collector current of the bipolar transistor Q3 is applied to the bias terminal B3, and is applied to the base of the bipolar transistor Q3 through the resistor R7. Bias terminal B1 and bias terminal B2
Is supplied with a bias voltage from the bias control circuit 52. The bias voltage applied to the bias terminal B1 is applied to the base of the bipolar transistor Q1 through the resistor R1. The bias voltage applied to the bias terminal B2 is
Added to the base of bipolar transistor Q2 through resistor R2.

A predetermined collector bias voltage is applied to the collector bias terminals Vcc1 and Vcc2. The collector voltage applied to the collector bias terminal Vcc1 is connected to the collector of the bipolar transistor Q1 and the addition circuit through the resistor R3.
Added to 51. The collector voltage applied to the collector bias terminal Vcc2 is applied to the collector of the bipolar transistor Q2 and the adding circuit 51 through the resistor R4.

The collector currents of the bipolar transistors Q1 and Q2, which are mixer elements, are controlled by the bias voltage from the bias control circuit 52. Since the magnitudes of the conversion coefficients k1 and k2 of the balance mixer change by changing the collector currents and collector voltages of the bipolar transistors Q1 and Q2, the bipolar transistors Q1 and k2 are changed.
By independently controlling the bias voltage of Q2 and the bias voltage of Q2 by the bias control circuit 52, it is possible to suppress the distortion component in the output of the addition circuit 51.

FIG. 17 is a block diagram of a seventh embodiment of the balance mixer. In FIG. 17, the balance mixer 7F
Is a circuit configuration in which a bipolar transistor is used in the above-described circuit configuration of FIG. 16 and is replaced with an FET (field-effect transistor).

The balance mixer 7F is composed of a differential connection using FET1 and FET2, a constant current circuit using FET3, an adder circuit 51 that outputs a mixer, and a bias control circuit 52. To the input terminals 7a1 and 7a2, input signals whose phases are inverted with respect to each other are applied. To the local oscillation signal input terminal 61, a local oscillation signal is applied and applied to the gate of the FET 3 through the resistor R6. The source of FET3 is grounded through resistor R5.

A bias voltage for controlling the drain current of the FET 3 is applied to the bias terminal B3, and the bias voltage is applied through the resistor R7.
Added to the gate of FET3. A bias voltage from the bias control circuit 52 is supplied to the bias terminals B1 and B2. The bias voltage applied to the bias terminal B1 is applied to the gate of the FET1 through the resistor R1. The bias voltage applied to the bias terminal B2 is applied to the gate of FET2 through the resistor R2.

A predetermined drain bias voltage is applied to the drain bias terminals Vdd1 and Vdd2. The drain voltage applied to the drain bias terminal Vdd1 is applied to the drain of the FET1 and the addition circuit 51 through the resistor R3. The drain voltage applied to the drain bias terminal Vdd2 is
It is applied to the drain of FET2 and the adder circuit 51 through a resistor R4.

The drain currents of the mixer elements FET1 and FET2 are controlled by the bias voltage from the bias control circuit 52. The conversion coefficient k1 of this balance mixer and
The magnitude of k2 changes by changing the drain current and drain voltage of FET1 and FET2.
By controlling the bias voltage of the FET 2 independently by the bias control circuit 52, the distortion component in the output of the adder circuit 51 can be suppressed.

FIG. 18 is a block diagram of an eighth embodiment of the balance mixer. In FIG. 16 described above, the bias control circuit
Although the base voltage applied to the bases of the bipolar transistors Q1 and Q2 is controlled by 52, in FIG. 18, the balance mixer 7G connects the bias control circuit 52 to the collector bias terminals Vcc1 and Vcc2, A configuration for controlling the collector voltages of the transistors Q1 and Q2 is employed. As a result, the amount of distortion of the output of the adding circuit 51 that adds the collector voltages of the bipolar transistors Q1 and Q2 can be reduced.

FIG. 19 is a block diagram of a ninth embodiment of the balance mixer. 17, the gate voltage applied to the gates of FET1 and FET2 is controlled by the bias control circuit 52.In FIG. 19, the balance mixer 7H includes the bias control circuit 52 connected to the drain bias terminal. It is connected to Vdd1 and Vd2 to control the drain voltage of FET1 and FET2. This allows the addition circuit to add the drain voltage of FET1 and FET2
The amount of distortion of the output of 51 can be suppressed small.

FIG. 20 is a block diagram of a tenth embodiment of the balance mixer. In FIG. 20, the balance mixer 7I
Supplies a fixed bias to the bias terminals B1 and B2, and inserts a controllable variable attenuator (ATT) 54 between the input terminal 7a1 and the base of the bipolar transistor Q1,
Further, a controllable variable attenuator 55 is inserted between the input terminal 7a2 and the base of the bipolar transistor Q2.

The attenuation amounts of the variable attenuator 54 and the variable attenuator 55 are independently controlled by the control of the gain control circuit 53. Other circuit configurations are the same as those in FIG. 16 described above. Since the magnitude of the distortion of the output of the adder circuit 51 changes according to the input level of each of the bipolar transistors Q1 and Q2, the magnitude of the distortion can be controlled by switching between the variable attenuators 54 and 55.

FIG. 21 is a block diagram of an eleventh embodiment of the balance mixer. In FIG. 21, the balance mixer 7J
Differs from the configuration of FIG. 20 in that the connection positions of the variable attenuator 54 and the variable attenuator 55 are changed. That is, a fixed bias is supplied to the bias terminal B1 and the bias terminal B2, a controllable variable attenuator 54 is inserted between the collector output of the bipolar transistor Q1 and the addition circuit 51, and furthermore, the collector output of the bipolar transistor Q2 and A controllable variable attenuator 55 is inserted between the adder 51 and the adder 51.
The variable attenuator 54 and the variable attenuator 55 are controlled by the gain control circuit 53. In this circuit configuration, an operation similar to that of FIG. 12 described above is performed in principle.

FIG. 22 is a circuit configuration diagram in the case where the above-described balance mixer of FIG. 16 is a double balance mixer. This circuit configuration applies a basic circuit called a Gilbert cell.

The configuration of the first balance mixer 56 and the second balance mixer 57 is almost the same as the configuration of FIG. 16 described above. The first balance mixer 56 is different from the differential connection by the bipolar transistors Q1 and Q2. , And a constant current circuit using a bipolar transistor Q3. The second balance mixer 57 includes bipolar transistors Q4 and Q5.
And a constant current circuit using a bipolar transistor Q6.

The collector of the bipolar transistor Q1 and the collector of the bipolar transistor Q4 are connected, and the collector voltage is applied to the addition circuit 51 from the connection. The collector of the bipolar transistor Q2 and the collector of the bipolar transistor Q5 are connected, and the collector voltage is applied to the addition circuit 51 from the connection.

The bias terminal B1 of the first balance mixer 56
Is supplied with a bias voltage from the bias control circuit 52. The bias voltage is also supplied from the bias control circuit 52 to the resistor R2 of the second balance mixer 57. First
A local oscillation signal is supplied to a local oscillation signal input terminal 61 of the balance mixer 56, and the local oscillation signal is inverted in phase by a phase inversion circuit 58 and supplied to a resistor R9 of a second balance mixer 57. . The base of the bipolar transistor Q2 of the first balance mixer 56 and the base of the bipolar transistor Q4 of the second balance mixer 57 are supplied with an input signal applied to the input terminal 7a2 in common.

Test signals inverted from each other are applied to the input terminals 7a1 and 7a2 as in FIG. By controlling the conversion coefficients of the first balance mixer 56 and the second balance mixer 57 by the bias control circuit 52, the amount of distortion in the output of the addition circuit 51 is suppressed.

FIG. 23 shows that the bipolar transistors Q1, Q2, and Q3 used in the first balance mixer and the second balance mixer are replaced with FET1, FET2, and FET3 in the circuit configuration of the double balance mixer shown in FIG. This is a circuit composed of a first balance mixer 56A and a second balance mixer 57A.

Even with such a configuration, by controlling the conversion coefficients of the first balance mixer 56A and the second balance mixer 57A by the bias control circuit 52,
The amount of distortion can be suppressed at the output of the adding circuit 51.

[0090]

As described above, according to the present invention, a test signal for performing distortion compensation for the first mixer and the second mixer is generated, and the test signal is supplied to the first mixer and the second mixer. A distortion amount is detected from the output signal when supplied, and a sensitivity control amount signal for the first mixer and the second mixer is determined from the distortion amount. When the non-test signal is input, the first sensitivity control amount signal is used to determine the first sensitivity control amount signal. Since the sensitivity control for the mixer and the second mixer is performed, distortion due to mixing between the input signal and the local oscillation signal can be efficiently reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a balanced mixer circuit according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional balanced mixer circuit.

FIG. 3 is a diagram illustrating a relationship between a mixer input and a mixer output in a conventional balanced mixer circuit, and illustrates a fundamental wave output and a second-order distortion output of a first mixer and a second mixer, and an output of an adder circuit; It is a figure showing a fundamental wave output and a 2nd-order distortion output.

FIG. 4 is a configuration diagram of a balanced mixer circuit according to a second embodiment of the present invention, which is a configuration of a direct conversion mixer circuit that handles complex signals.

FIG. 5 is a configuration diagram of a balanced mixer circuit according to a third embodiment.

FIG. 6 is a configuration diagram of a balance mixer circuit according to a fourth embodiment.

FIG. 7 is a configuration diagram of a balanced mixer circuit according to a fifth embodiment.

FIG. 8 is a control flowchart of a distortion compensation operation in the balance mixer circuit of FIG. 7;

FIG. 9 is a configuration diagram of a balance mixer circuit according to a sixth embodiment.

FIG. 10 is a control flowchart of a distortion compensation operation in the balance mixer circuit of FIG. 9;

FIG. 11 is a configuration diagram of a second embodiment of a balance mixer.

FIG. 12 is a configuration diagram of a third embodiment of the balance mixer.

FIG. 13 is a configuration diagram of a fourth embodiment of a balance mixer.

FIG. 14 is a configuration diagram of a fifth embodiment of a balance mixer.

15 is a detailed configuration diagram of an addition circuit of the balance mixer of FIG. 14;

FIG. 16 is a circuit diagram of a balance mixer according to a sixth embodiment;

FIG. 17 is a configuration diagram of a seventh embodiment of a balance mixer.

FIG. 18 is a configuration diagram of an eighth embodiment of the balance mixer.

FIG. 19 is a configuration diagram of a ninth embodiment of a balance mixer.

FIG. 20 is a configuration diagram of a tenth embodiment of a balance mixer.

FIG. 21 is a configuration diagram of an eleventh embodiment of a balance mixer.

FIG. 22 is a configuration diagram of a double balance mixer circuit of the first embodiment.

FIG. 23 is a configuration diagram of a double balance mixer circuit according to a second embodiment.

[Explanation of symbols]

 2, 4 mixer 5 addition circuit 6 local oscillator 7 balance mixer 10 test signal generation circuit 12 distortion detection circuit 13 sensitivity control circuit 14 compensation control circuit 15 start-up / non-information communication detection circuit

Claims (13)

[Claims] 1. A first mixer for mixing an input signal and a local oscillation signal, and a second mixer for mixing the input signal and the local oscillation signal in a 180-degree phase shift relationship with the first mixer. And a summing means for summing an output signal of the first mixer and an output signal of the second mixer, wherein the circuit comprises: a distortion compensation circuit for the first mixer and the second mixer. Test signal generating means for generating a test signal for performing the following: an output signal of the first mixer and the second mixer when the test signal is supplied to the first mixer and the second mixer; or A distortion amount detecting unit for detecting a distortion amount from an output signal of the adding unit; and a first mixer and a first mixer based on the distortion amount when the test signal is supplied to the first mixer and the second mixer. 2 and a sensitivity control signal for the adding means is determined, and when a non-test signal is input, sensitivity control for the first mixer and the second mixer or the adding means is performed using the determined sensitivity control signal. A balance mixer circuit comprising: a sensitivity control unit. 2. The circuit according to claim 1, wherein said distortion amount detecting means separates a distortion component by filtering an output signal of said first mixer and said second mixer or an output signal of said adding means. A balanced mixer circuit for detecting the magnitude of a distortion component. 3. The circuit according to claim 1, wherein the distortion amount detecting means performs a Fourier transform on an output signal of the first mixer and the second mixer, or an output signal of the adding means, to reduce a distortion component. A balanced mixer circuit characterized by detecting. 4. The circuit according to claim 1, wherein said sensitivity control means controls a level of an input signal or an output signal at an input side or an output side of said first mixer and said second mixer. A balance mixer circuit characterized by controlling the size. 5. A circuit according to claim 1, wherein said sensitivity control means controls a level of a level of a local oscillation signal for said first mixer and said second mixer. And the balance mixer circuit. 6. The circuit according to claim 1, wherein said adding means includes a variable gain differential operational amplifier, wherein the gain of said variable gain differential operational amplifier is controlled by said sensitivity control amount signal. A balance mixer circuit characterized in that: 7. The circuit according to claim 1, wherein said first mixer and said second mixer include an emitter-coupled transistor pair circuit, wherein said emitter-coupled transistor pair circuit has a base bias or collector voltage. Is independently controlled by the sensitivity control amount signal. 8. The circuit according to claim 1, wherein the first mixer and the second mixer include a source-coupled field effect transistor pair circuit, and a gate bias or a drain voltage of the circuit is the sensitivity. A balanced mixer circuit which is independently controlled by a control amount signal. 9. A first mixer for mixing an input signal and a local oscillation signal, and a second mixer for mixing the input signal and the local oscillation signal in a 180-degree phase shift relationship with the first mixer. A first balance mixer including first addition means for adding the output signal of the first mixer and the output signal of the second mixer; and shifting the input signal and the local oscillation signal by 90 degrees. A third mixer for mixing the phase-shifted local oscillation signal with the third local mixer, a fourth mixer for mixing the input signal and the 90-phase-shift local oscillation signal with a 180-degree phase shift relationship with the third mixer, In a quadrature balance mixer circuit including a second balance mixer including a second addition means for adding an output signal of a third mixer and an output signal of the fourth mixer, the circuit includes: Balance mixer and second bus Test signal generating means for generating a test signal for performing distortion compensation on the mixer, and the first balance mixer and the second balance mixer when the test signal is supplied to the first balance mixer and the second balance mixer. A distortion amount detecting means for detecting an amount of distortion from an output signal of the balance mixer, and the first balance mixer based on the amount of distortion when the test signal is supplied to the first balance mixer and the second balance mixer. A sensitivity control means for determining a sensitivity control amount signal for the second balance mixer and performing sensitivity control on the first balance mixer and the second balance mixer with the determined sensitivity control amount signal when a non-test signal is input. A quadrature balance mixer circuit characterized in that: 10. A first balance mixer comprising a differential pair amplifier for mixing an input signal and a local oscillation signal,
A second balance mixer including a differential pair amplifier for mixing the input signal and the local oscillation signal with the first balance mixer in a 180-degree phase shift relationship, in a Gilbert cell configuration; In a double balance mixer circuit including an adder for adding an output signal of a balance mixer and an output signal of the second balance mixer, the circuit performs distortion compensation on the first balance mixer and the second balance mixer. Signal generating means for generating a test signal for outputting the output signal of the first balance mixer and the second balance mixer when the test signal is supplied to the first balance mixer and the second balance mixer And a distortion amount detecting unit for detecting a distortion amount from the first and second balance mixers. A sensitivity control amount signal for the first balance mixer and the second balance mixer is determined from the distortion amount when the first balance mixer and the second balance mixer are input when a non-test signal is input. And a sensitivity control means for independently controlling the current of the differential pair amplifier of the balance mixer. 11. A receiving device comprising any one of the balanced mixer circuit, the quadrature balanced mixer circuit and the double balanced mixer circuit according to any one of claims 1 to 10, wherein the receiving device is provided immediately after startup or When information is not received, the sensitivity control means signal is determined by supplying the test signal to the mixer circuit, or the sensitivity control amount signal is updated.When the information is received, the determined or updated A receiving apparatus for performing sensitivity control on the mixer circuit using a sensitivity control amount signal. 12. A recording device in which a computer detects a distortion amount included in an output signal of a balance mixer for mixing an input signal and a local oscillation signal, and records a balance mixer control program for controlling the sensitivity of the balance mixer. A medium, wherein the balance mixer control program includes a detecting step of taking in an output signal of the balance mixer, calculating and detecting a distortion amount included in the output signal, and detecting the balance mixer from the detected distortion amount. And a sensitivity control signal generating step of generating a sensitivity control signal for performing sensitivity control on the balance mixer control program. 13. The recording medium according to claim 12, wherein
A recording medium storing a balance mixer control program, wherein the detecting step detects the distortion amount by a filtering process or a Fourier transform process.