JPH1140866A - Oxide superconducting logic circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture an oxide superconducting logic circuit which meets the operating conditions of a quantum magnetic flux parametron element and where restrictions on a layer structure and a circuit structure as to the layout of a Josephson junction are taken into consideration by a method, wherein the oxide superconducting logic circuit has a layer structure where an oxide superconductor layer, an insulator layer, and a metal layer are provided on a substrate. SOLUTION: An oxide superconductor layer 10 is processed into an element pattern 91, a connection pattern 93, and a grounding pattern 92 through an electron lithography or the like, and an insulator layer 30 of SiO is formed through a resistance heating evaporation method. When the SiO insulator layer 30 is evaporated, the temperature of a substrate hardly exceeds 500 deg.C, so that oxygen does not desorbs from the oxide superconductor layer 10, and the oxide superconductor layer 10 is restrained from deteriorating in characteristics. Similarly, a metal layer 20 of Au is formed through a resistance heating evaporation method and processed through an electron beam lithography or the like. Through these processes, a quantum magnetic flux parametron element is formed. As a result of this an oxide superconducting logic circuit of layout structure which satisfies the operating conditions of a quantum magnetic flux parametron element is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oxide superconducting logic circuit comprising a quantum flux parametron device manufactured using an oxide superconductor, and more particularly, to an operating condition of the quantum flux parametron device and a constraint on the circuit fabrication. And an oxide superconducting logic circuit device having a configuration satisfying the above conditions.

[0002]

2. Description of the Related Art Conventionally, with regard to the design and operation of a quantum flux parametron device, see IEE Transactions on Update Superconductivity, Vol. 3, 1993, pp. 3022 to 3028 (IEEE Transactions on Applied Sup
erconductivity vol. 3 (1993) pp. 3022-3028). Hereinafter, this will be referred to as a first conventional example. Regarding the design and operation of a logic circuit composed of an oxide superconductor, see IEE Transactions on Update Superconductivity, Vol. 5, 1995, pp. 3401-3.
404 pages (IEEE Transactions on Applied Superconduc
tivity vol. 5 (1995) pp.3401-3404). Hereinafter, this will be referred to as a second conventional example.

In order to manufacture a quantum flux parametron device made of an oxide superconductor, the operating conditions of the quantum flux parametron device must be satisfied in consideration of the inherent constraints that arise when fabricating an oxide superconducting logic circuit. There is a need. First, for the operation of the quantum flux parametron device,
As described in the first conventional example, the product of the loop inductance of the superconducting closed loop, that is, the product of the sum of the first inductance and the second inductance and the superconducting critical current of the first and second Josephson junctions is substantially a magnetic flux. Must be set to about quantum.

Further, the signal current needs to be large enough to cancel the thermal noise. Therefore, at an operating temperature of several tens K,
The superconducting critical current generally requires several tens of μA or more. Therefore, the loop inductance must be suppressed to a small value of about several tens of pH or less. Further, the output current is inversely proportional to the load inductance. Therefore, in order to obtain a sufficiently large output current, it is necessary to reduce the distance between the quantum flux parametron elements as much as possible to reduce the load inductance.

On the other hand, it is generally difficult to realize a stacked structure of oxide superconductors in an oxide superconductor logic circuit. For example, in order to maintain the superconductivity of the upper and lower two oxide superconductor layers, specific insulator layers such as SrTiO3 and film formation conditions are required, and the process conditions for circuit fabrication are limited. Further, at the time of forming the oxide superconductor, foreign matter of fine particles is easily formed. These fine particles destroy the insulator layer, which is an interlayer insulating film, cause a short circuit between layers, and cause a failure in circuit operation. Therefore, it is desirable for the oxide superconducting logic circuit to have a layer configuration that does not include the laminated structure of the oxide superconductor as much as possible.

As a Josephson junction in an oxide superconducting logic circuit, a step edge type having a step formed on a substrate and a bicrystal type using a bicrystal as a substrate are used. As shown in FIG. 1 of the second conventional example, the Josephson junctions can be arranged only on a straight line where the edge or the substrate junction exists, and cannot be arranged at an arbitrary position. Therefore, when manufacturing an oxide superconducting logic circuit, it is necessary to configure the circuit in consideration of the restrictions on the arrangement of the Josephson junctions.

In particular, a second conventional example is an RSFQ element (R
This is an example in which an oxide superconducting logic circuit is manufactured by using SFQ (Rapid Single Flux Quantum). In this RSFQ element, circuit element elements are connected only by a direct coupling type and do not include a magnetic coupling type. Therefore, the configuration of the element is relatively simple. On the other hand, in the quantum flux parametron element, the circuit element elements are connected by both the direct coupling type and the magnetic coupling type, and the configuration of the element is complicated. Therefore, there is no example in which an oxide superconducting logic circuit is manufactured using a plurality of quantum flux parametron elements, and no optimum layout configuration is shown.

[0008]

The problem to be solved is that, in the prior art, the oxidation that satisfies the operating conditions of the quantum flux parametron device and takes into account the restrictions on the layer structure and the arrangement of the Josephson junction is considered. The point is that a superconducting logic circuit device cannot be manufactured. The purpose of the present invention is
An object of the present invention is to solve the problems of the prior art and to provide an oxide superconducting logic circuit device using a quantum flux parametron element which can be put into practical use.

[0009]

In order to achieve the above object, an oxide superconducting logic circuit device of the present invention comprises:
With a layered structure including an oxide superconductor layer, an insulator layer, and a metal layer, a quantum flux parametron device using one oxide superconductor layer can be manufactured. As a result, a layout configuration that sufficiently considers the layer configuration and the arrangement of the Josephson junctions and satisfies the operating conditions of the quantum flux parametron device becomes possible. That is,
With the oxide superconductor layer, the element pattern of the quantum flux parametron element and the ground pattern are formed separately at the Josephson junction, and the connection pattern connecting the element patterns is formed in a continuous shape, thereby forming a plurality of patterns. Of the quantum flux parametron device can be made of one layer of oxide superconductor. In particular, since the connection pattern is continuous, that is, all the quantum flux parametron elements are formed in a continuous area other than the ground pattern area surface, the quantum flux parametron elements are not interposed between the quantum flux parametron elements without passing through the ground pattern area. Connection can be made, the connection length can be shortened, and the load inductance can be reduced. The ground pattern is separated from the element pattern at the Josephson junction, and the ground plane and the quantum flux parametron element are formed close to each other.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of a configuration according to the present invention of an oxide superconducting logic circuit device of the present invention, and FIG. 2 is a quantum flux parametron in the oxide superconducting logic circuit device in FIG. FIG. 3 is a circuit diagram showing an equivalent circuit of the device, and FIG. 3 is an explanatory diagram showing a layout of a quantum flux parametron device in the oxide superconducting logic circuit device in FIG.

The oxide superconducting logic circuit device of this embodiment shown in FIG.
4 quantum flux parametron devices and 1 dc-SQU
ID (: Direct Current Superconducting Quantum Int
erference device (quantum interferometer)), thereby producing an 8: 1 multiplexer. In FIG. 1, 90 is a substrate made of SrTiO 3, 91 is an element pattern of a quantum flux parametron element, 92 is a ground pattern, 93 is a connection pattern, 101 is a ground pattern 9
2 is a region of the ground plane, and 102 is the other region.

The respective structures of the element pattern 91, the ground pattern 92, and the connection pattern 93 are shown in the equivalent circuit of FIG. 2. First, a process for manufacturing such a quantum flux parametron element will be described with reference to FIG. I do. In FIG. 3, 10 is an oxide superconductor layer, 20 is a metal layer, 30 is an insulating layer, 40 is a Josephson junction position, and 90 is a substrate.

A mask pattern made of Si is formed on the substrate 90 by using electron beam lithography. This mask pattern is formed so as to cover the half plane of the substrate 90 with the Josephson junction position 40 as a boundary. Then, the substrate 90 is etched by Ar + O2 ion etching to form a step having a height h = 240 nm at the Josephson junction position 40. Next, an oxide superconductor layer 10 made of YBa2 Cu3 O7 having a thickness of t = 120 nm is formed on the substrate 90 by a laser ablation method. As a result, a Josephson junction is formed at the intersection of the oxide superconductor layer 10 and the Josephson junction position 40.

Then, the oxide superconductor layer 10 is processed by electron beam lithography or Ar ion etching to form an element pattern 91, a connection pattern 93 and a ground pattern 92 in a shape as shown in the figure, and then use a shadow mask. An insulating layer 30 made of SiO having a thickness of t = 600 nm is formed by a resistance heating evaporation method. During this SiO vapor deposition, the temperature of the substrate does not rise to 500 ° C. or higher. Therefore, oxygen does not escape from the oxide superconductor layer 10 and the characteristics do not deteriorate. Further, in the same manner, the film thickness is determined by resistance heating evaporation.
A metal layer 20 made of Au having a thickness of t = 280 nm is formed and processed by electron beam lithography or Ar ion etching. Thus, the quantum flux parametron device shown in FIG. 3 is manufactured.

When the oxide superconductor is formed, foreign matter of fine particles is easily formed. These fine particles destroy the insulator layer, which is an interlayer insulating film, cause a short circuit between layers, and cause a failure in circuit operation. However, in this embodiment, the diameter of the fine particles is at most about 100 nm, which is sufficiently smaller than the film thickness (t = 600 nm) of the SiO insulator layer 30, and the fine particles can be sufficiently covered by the SiO insulator layer 30. . In addition, since the evaporation method with a low substrate temperature is used, the SiO insulator layer 30 having a sufficiently large thickness can be formed without deteriorating the oxide superconductor layer 10.

On the other hand, an oxide superconductor is used as the metal layer 20 in order to realize a laminated structure of the oxide superconductor.
At this time, a specific material such as SrTiO3 is used for the insulator layer 30 in order to maintain the superconductivity of the upper and lower oxide superconductor layers. In general, it is necessary to use 500 to form SrTiO3.
A high substrate temperature of not less than ° C. is required. At this time, the characteristics of the oxide superconductor layer 10 are liable to be deteriorated due to release of oxygen and the like. Accordingly, circuit manufacturing process conditions, for example, oxygen partial pressure and incident energy during film formation of YBa2Cu3O7 and SrTiO3 become narrower, and it becomes difficult to obtain desired values of manufacturing process parameters such as the film thickness of SrTiO3. As a result, the superconducting property of YBa2Cu3O7 and the insulating property of SrTiO3 tend to deteriorate.

Next, the structure of the quantum flux parametron device thus manufactured will be described with reference to FIG. As shown in the equivalent circuit of FIG. 2, the quantum flux parametron device of the present embodiment has a signal input line 12, a load inductor 13, and first and second Josephs formed respectively from the oxide superconductor layer 10 of FIG. 3, the first and second inductors 113 and 114, the ground plane 115,
Input lines 2 formed from metal layers 20 of
The first and third inductors 22 and 23 are provided.

The first Josephson junction 111, the first inductor 113, the second inductor 114, and the second Josephson junction 112 are connected in this order to form a superconducting closed loop 11, and the first Josephson junction 111 And the second
The connection point of the Josephson junction 112 is connected to the ground plane 115. First and second Josephson junctions 111,
The element pattern in FIGS. 1 and 2 is formed by 112 and the first and second inductors 113 and 114,
The connection pattern 93 in FIG. 2 is formed by the signal input line 12 and the load inductor 13, and the ground pattern 92 in FIG. 2 is formed by the third and fourth inductors 22 and 23.

One of the terminals of the signal input line 12 and one of the terminals of the load inductor 13 are connected to a first inductor 113 and a second inductor 114 which are part of the superconducting closed loop 11.
Connected to the connection point. And the clock input line 2
The first, third and fourth inductors 22 and 23 are connected in series in this order, and are connected to the first and second inductors 113 and 22 and the second inductor 114 via the insulator layer 30 in FIG. The fourth inductors 23 are each magnetically coupled.

As described above, in the present embodiment, the third inductor 22 and the fourth inductor 23 are formed of a layer different from the oxide superconductor layer 10 of FIG. 3, that is, the metal layer 20 of FIG. . Therefore, the superconducting closed loop 11 is connected while connecting the circuit element elements in both the direct coupling type and the magnetic coupling type.
Can be reduced. In an actual specific example, the width of the first and second Josephson junctions 111 and 112 is set to 2 μm.
By setting m, the width of the first and second inductances 113 and 114 to 3 μm, and the center hole to 2 μm × 6 μm, a small loop inductance L = 8pH suitable for device operation could be realized.

By combining and connecting a plurality of quantum flux parametron devices configured as described above, FIG.
4 and the 8: 1 multiplexer shown in FIG. FIG. 4 is a circuit diagram showing an equivalent circuit of the oxide superconducting logic circuit device in FIG. The manufacturing process of the 8: 1 multiplexer including a plurality of quantum flux parametron elements shown in this equivalent circuit is the same as the manufacturing process shown in FIGS. 2 and 3 except for the pattern of the mask made of Si. In other words, the mask pattern made of Si is not formed so as to cover a half plane of the substrate, but is formed only in the vicinity where the Josephson junction is formed.

The 8: 1 multiplexer of the present example is connected to the substrate (9
0) It consists of 14 quantum flux parametron elements composed of an oxide superconductor layer (10), an insulator layer (30) and a metal layer (20) formed thereon and one dc-SQUID, The quantum flux parametron element includes a first Josephson junction (111), a second Josephson junction (112), a first inductor (113), and a second inductor (114) formed from an oxide superconductor layer. , Signal input line (12), load inductor (13) and ground plane (115)
And a clock input line (21) formed of a metal layer, a third inductor (22), and a fourth inductor (23).

The first Josephson junction, the first inductor, the second inductor, and the second Josephson junction are connected in order to form a superconducting closed loop. Further, the clock input line, the third inductor, and the fourth inductor are connected in series in order, and one of the terminals of the signal input line and one of the terminals of the load inductor are connected to a part of the superconducting closed loop. Further, a connection point between the first Josephson junction and the second Josephson junction is connected to a ground plane.

Further, the first inductor and the third inductor are magnetically coupled, and the second inductor and the fourth inductor are magnetically coupled. The other of the terminals of the load inductor forming each quantum flux parametron element is connected to the other of the signal input line terminals of the other adjacent quantum flux parametron element, or the other of the load inductor terminals or the ground plane. Connected. With such a configuration, the substrate can be formed by being divided into the ground plane region and the other two regions, and all the quantum flux parametron elements can be included in the other regions. Further, a ground plane can be formed close to each quantum flux parametron element.

Ib, S0, S1, S2, Ig2 in FIG.
Are signal currents applied to the clock input lines, respectively, and these wirings are formed from the metal layer 20 in FIG.
I0-I7 is a signal current applied to the signal input line;
g1 and Vout are the power supply current and output voltage applied to the dc-SQUID, and these wirings are both formed from the oxide superconductor layer 10 of FIG. Further, I0-I7 is an 8-bit input signal, and S0, S1, and S2 are 3-bit selection signals. The input signal is selected by these selection signals, and is output through dc-SQUID.

In the quantum flux parametron device, the layout of the oxide superconductor layer 10 in FIG. 3 is important. In general, a plurality of elements must be connected to produce a logic circuit. When a logic circuit is manufactured using a quantum flux parametron element, one of the terminals of the load inductor 13 shown in FIG. 2 of one element is connected to one of the terminals of the signal input line 12 shown in FIG. Figure 2 of the device
2 or one of the terminals of the load inductor 13 or the ground plane 115 shown in FIG. Then, in order to obtain a sufficiently large output current, the load inductance must be reduced.However, in the conventional example up to now, a suitable layout for connecting a plurality of quantum flux parametron elements while keeping the load inductance small is adopted. No examples were shown.

In this embodiment, the oxide superconductor layer 10 shown in FIG.
The layout shown in FIG. 1 allows a plurality of quantum flux parametron elements to be connected while keeping such a low load inductance. That is, as shown in FIG. 3, the oxide superconductor layer 10 of the quantum flux parametron element can be divided into a ground plane region and other regions with the Josephson junction position 40 as a boundary. The oxide superconductor layer 10 of FIG. 3 on the substrate 90 is connected to the ground plane region 101 and the other region 10.
It can be divided into two. All the quantum flux parametron devices are laid out so as to be included in the other region 102.

Further, with respect to the substrate 90, the other region 102 is a so-called single connection which is not divided by the ground surface region 101. Therefore, each quantum flux parametron element can connect all the load inductors and the signal input lines without passing through the region of the ground plane. The wiring of the quantum flux parametron element is laid out so as to be close to the area 101 on the ground plane, and all the elements are embedded in the area 101 on the ground plane. This reduces the load inductance of the quantum flux parametron device. At the same time, the line width of the ground plane also increases, so that the inductance decreases. In this way,
Since the values of the circuit element elements satisfying the operation conditions of the element can be obtained, an oxide superconducting logic circuit including a quantum flux parametron element can be realized.

In order to estimate the inductance of such a wiring, a direct coupling type dc-SQU is actually mounted on another substrate.
The ID was manufactured, the injection current / the SQUID voltage was measured, and the inductance of the wiring was obtained from the periodic characteristic. As a result, in the single-layer YBa2Cu3O7 having the layer configuration of the present embodiment, the inductance per square for a line width w = 0.5 mm-3.0 mm is L at a sufficiently low temperature of 60 K or less.
= 1.25 pH / square. Therefore, in the layout of FIG. 1, the load inductance of the quantum flux parametron device is at most 30 pH. This is a value small enough to realize element operation, and an 8: 1 multiplexer can be realized by the layout of FIG.

Next, an example of the configuration of an 8: 1 multiplexer in another layout will be described. FIG. 5 is a block diagram showing a second embodiment of the configuration according to the present invention of the oxide superconducting logic circuit device of the present invention. In the second example, 14 quantum flux parametron elements and one dc-SQUID are formed using a bicrystal-type Josephson junction, thereby forming the same dc-SQUID as shown in FIG. 4 of the first embodiment. This is an example in which an 8: 1 multiplexer represented by an equivalent circuit is manufactured. The layer configuration is Au / SiO / YBa2Cu3O7, which is the same as that of the first embodiment, and each manufacturing process such as film formation, lithography, and etching is the same as that of the first embodiment.

The substrate 90a of this embodiment is a bicrystal substrate, and the Josephson junction position 40a is the junction surface of the bicrystal. The Josephson junction is formed at the intersection of the oxide superconductor layer and the Josephson junction position 40a. The oxide superconductor layer has a ground plane region 101a and a region 102a other than the region 101a with the Josephson junction position 40a as a boundary.
Is divided into two. All the quantum flux parametron elements are laid out so as to be included in the other region 102a.

As described above, since the other region 102a on the substrate 90 is not divided by the ground plane region 101a, all the load inductors and signal input lines of the quantum flux parametron element are connected to the ground plane region 101a. You can connect without going through. Thus, an oxide superconducting logic circuit including a quantum flux parametron element with reduced load inductance can be realized.

Further, in the step-edge type Josephson junction of the first embodiment, since a step is formed in the substrate, the film thickness t is sufficient for the Au wiring to get over this step.
In the second embodiment, a bicrystal type was used as the Josephson junction, so such a step was eliminated, and the restriction on the circuit fabrication process was relaxed. A circuit can be manufactured using Au of t = 200 nm, and the yield is improved. Further, disconnection due to a step of the Au wiring as a metal layer is reduced, and the yield of circuit fabrication is further improved.

FIG. 6 is a block diagram showing a third embodiment of the configuration according to the present invention of the oxide superconducting logic circuit device of the present invention, and FIG. 7 is a circuit diagram showing an equivalent circuit thereof. In the third embodiment shown in FIG. 6, eight quantum flux parametron elements and one dc-SQUID are formed using a bicrystal Josephson junction, and are represented by an equivalent circuit of FIG. 8: 1 multiplexer. The layer structure is the same as that of the first and second embodiments, Au / SiO.
/ YBa2Cu3O7, and the respective manufacturing processes such as film formation, lithography, and etching are the same as those in the first and second embodiments.

In the first and second embodiments, the number of bits of the selection signal is as small as 3 bits S0, S1, and S2, but 14 quantum flux parametron elements are required. In the third embodiment, the selection signal is as large as 8 bits, but the number of quantum flux parametron elements can be as small as eight. Ib0-Ib7 in FIGS. 6 and 7 are signal currents applied to a clock input line formed of a metal layer, and these become the selection signals.

In FIG. 6, a substrate 90b is a bicrystal substrate, and a Josephson junction position 40b is a junction surface of the bicrystal. The Josephson junction is formed at the intersection of the oxide superconductor layer and the Josephson junction position 40b. The oxide superconductor layer is located at the Josephson junction position 40b.
And the other area 1
02b. All the quantum flux parametron elements are laid out so as to be included in the other region 102b.

As described above, since the other region 102b on the substrate 90b is not divided by the ground plane region 101b, the load inductor of the quantum flux parametron element is similar to the first and second embodiments. And the signal input lines can be connected without passing through the ground plane region 101b. Thus, an oxide superconducting logic circuit including a quantum flux parametron element with reduced load inductance can be realized. Furthermore, as in the second embodiment, since the Josephson junction is of the bicrystal type, such a step is eliminated, the restriction on the circuit fabrication process is loosened, and the disconnection due to the step is reduced. The yield of circuit fabrication is improved.

FIG. 8 is a block diagram showing a fourth embodiment of the configuration according to the present invention of the oxide superconducting logic circuit device of the present invention. This example has a configuration in which a ground plane area 101c is divided by another area 102c on a substrate 90c. Even in such a layout,
As in the first to third embodiments, the load inductors and signal input lines of the quantum flux parametron element are all connected to the ground plane region 1.
01c, and an oxide superconducting logic circuit comprising a quantum flux parametron element with reduced load inductance can be realized. In the oxide superconducting logic circuit device of this example, the connection between the regions 101c of the respective ground planes is made outside the circuit.

As described above with reference to FIGS. 1 to 8, the oxide superconducting logic circuit device of this embodiment has a structure in which an oxide superconductor layer, an insulator layer, and a metal layer are provided on a substrate. The oxide superconductor layer,
It is divided into a ground plane region and other regions, and all the quantum flux parametron elements are formed so as to be included in the other regions. Therefore, since the load inductors and signal input lines of the quantum flux parametron element can all be connected without passing through the ground plane area, an optimal layout that satisfies the operating conditions of the quantum flux parametron element can be configured. Oxide superconducting logic circuit can be realized.

That is, the oxide superconducting logic circuit device of this embodiment has a layer structure of an oxide superconductor layer, an insulator layer, and a metal layer, and is manufactured using at least one oxide superconductor layer. . As described above, when the ground plane and the quantum flux parametron element are formed by the oxide superconductor layer having a single-layer structure, the area of the ground plane is divided into two or more areas including the quantum flux parametron element, and three substrates are used. When divided into the above-mentioned regions, the load inductor and the signal input line between the quantum flux parametron elements included in the different regions cannot be connected without passing through the region of the ground plane. The region is divided into a ground plane region and two other regions so that all the quantum flux parametron elements are included in the other region.

As a result, since the other regions are simply connected, the load inductor of the quantum flux parametron element and the signal input lines can all be connected without passing through the region of the ground plane. Therefore, a layout suitable for satisfying the operating conditions can be configured under the restrictions on the layer configuration and the arrangement of the Josephson junctions, thereby realizing an oxide superconducting logic circuit including a quantum flux parametron device. Specifically, by appropriately selecting the materials of the metal layer and the insulator layer, the film formation conditions of the oxide superconductor layer, the metal layer, and the insulator layer are optimized, and interlayer short-circuits are suppressed to prevent circuit operation failure. To realize no oxide superconducting logic circuit.

The present invention is not limited to the embodiment described with reference to FIGS. 1 to 8, and can be variously modified without departing from the gist thereof. For example, in the layer configuration of the present example, the metal layer is a superconductor, but it is not necessarily required to be a superconductor, and the material can be freely selected similarly to the insulator layer. In this case, the circuit element elements formed by each layer must be appropriately selected.

[0043]

According to the present invention, there is provided an oxide superconducting logic circuit which satisfies the operating conditions of the quantum flux parametron element and takes into account the restrictions of the circuit configuration regarding the layer configuration and the arrangement of Josephson junctions. Thus, an oxide superconducting logic circuit device using a quantum flux parametron element can be put to practical use.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a configuration according to the present invention of an oxide superconducting logic circuit device of the present invention.

FIG. 2 is a circuit diagram showing an equivalent circuit of a quantum flux parametron element in the oxide superconducting logic circuit device in FIG.

FIG. 3 is an explanatory diagram showing a layout of a quantum flux parametron element in the oxide superconducting logic circuit device in FIG. 1;

FIG. 4 is a circuit diagram showing an equivalent circuit of the oxide superconducting logic circuit device in FIG.

FIG. 5 is a block diagram showing a second embodiment of the configuration according to the present invention of the oxide superconducting logic circuit device of the present invention.

FIG. 6 is a block diagram showing a third embodiment of the configuration according to the present invention of the oxide superconducting logic circuit device of the present invention.

FIG. 7 is a circuit diagram showing an equivalent circuit of the oxide superconducting logic circuit device in FIG. 6;

FIG. 8 is a block diagram showing a fourth embodiment of the configuration according to the present invention of the oxide superconducting logic circuit device of the present invention.

[Explanation of symbols]

10: oxide superconductor layer, 11: superconducting closed loop, 1
2: signal input line, 13: load inductor, 20: metal layer, 21: clock input line, 22: third inductor,
23: fourth inductor, 30: insulator layer, 40, 40
a, 40b: Josephson junction position, 90, 90a-9
0c: substrate, 91: element pattern, 92: ground pattern, 93: connection pattern, 101, 101a to 101
c: ground plane area, 102, 102a to 102c: other area, 111: first Josephson junction, 11
2: second Josephson junction, 113: first inductor, 114: second inductor, 115: ground plane.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor ▲ Taka ▼ Kazumasa Ki 2520 Akanuma, Hatoyama-cho, Hiki-gun, Saitama Pref.

Claims (7)

[Claims] An oxide superconducting logic circuit device comprising a plurality of quantum flux parametron elements connected to each other, wherein an element pattern of the quantum flux parametron element and a ground pattern are formed separately at a Josephson junction, An oxide superconductor layer for forming a connection pattern for connecting the respective element patterns in a continuous shape; and the oxide superconductor layer formed on the oxide superconductor layer. The Josephson junction is formed on the formed oxide superconductor layer. Having a portion to form on a continuous line,
A substrate on which a plurality of the ground patterns are formed by one common ground pattern; an insulating layer covering the element superconductor layer, the connection pattern and the oxide superconductor layer on which the ground pattern is formed; Deposited on the layer,
An oxide superconducting logic circuit device, comprising: a metal layer that supplies a signal by magnetic coupling to an inductor portion forming a superconducting closed loop in the element pattern of the oxide superconducting layer. 2. The oxide superconducting logic circuit device according to claim 1, wherein said element pattern comprises first and second inductors and first and second inductors forming said superconducting closed loop.
Wherein the connection pattern comprises an input line connected to an intermediate point between the first and second inductors and a load inductor, and connects the load inductor to an adjacent quantum flux parametron element. The ground pattern is connected to the input line or the load inductor, and the first and second inductors are connected to the first and second inductors.
The superconducting closed loop is formed opposite to the second Josephson junction, and the metal layer includes third and fourth inductors magnetically coupled to the first and second inductors. Oxide superconducting logic circuit device. 3. The oxide superconducting logic circuit device according to claim 1, wherein said metal layer is made of an oxide superconductor. . 4. The oxide superconducting logic circuit device according to claim 1, wherein the substrate has a portion for forming all the Josephson junctions.
An oxide superconducting logic circuit device having on one continuous line, wherein all the ground patterns are formed by one common ground pattern. 5. The oxide superconducting logic circuit device according to claim 1, wherein the substrate has a continuous step as a portion forming the Josephson junction. Oxide superconducting logic circuit device. 6. The oxide superconducting logic circuit device according to claim 1, wherein the substrate has a portion on which the Josephson junction is formed on a continuous straight line. Oxide superconducting logic circuit device. 7. The oxide superconducting logic circuit device according to claim 5, wherein said substrate comprises a bicrystal substrate, and said Josephson junction is formed at a junction surface of said bicrystal. Logic circuit device.