JPH1140807A - Igbt and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an IGBT which is high in productivity and low in ion resistance. SOLUTION: A groove T1 where a gate electrode 9 is housed is extended in a direction at right angles (lateral direction in the figure) with the longer directions of a collector layer 5 and a buffer layer 4, or in the direction in which a current flows. Therefore, electrons traveling towards the collector layer 5 via an emitter layer 10, an inverted channel region CH, and a drift layer 3 are not stopped from flowing by the groove T1 . Therefore, even if the groove T1 and a groove T2 electrically isolated from the groove T1 are formed at the same depth through the same etching, the flow of electrons is not adversely affected. Although the holes and electrons move on the surface and base of the drift layer 3 respectively, holes are stopped from flowing by a groove T3 . Through this setup, holes and electrons flow through paths, overlapping with each other, and holes are accumulated on the sidewall of the groove T3 on a collector layer 5 side. As a result, conductivity modulation is promoted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a lateral IG in which an emitter electrode and a collector electrode are formed on the same surface.
The present invention relates to a BT and a method for manufacturing the BT.

[0002]

2. Description of the Related Art FIGS. 25 and 26 are a sectional view and a plan view, respectively, showing the structure of a horizontal IGBT according to the prior art. The silicon layer SLP penetrates through the base layer 8 from the surface of the emitter layer 110 and reaches the drift layer 3.
Direction perpendicular to the cross section of FIG. 25 (vertical direction in FIG. 26)
Is formed. Inside the trench T100, a trench gate electrode 109 extending in a direction perpendicular to the cross section is formed via an insulating film 112.

When a positive bias is applied to the gate electrode 109 at the time of turn-on, the polarity of the channel region CH, which is a portion of the base layer 8 near both ends of the gate electrode 109, is inverted. The electrons injected from the emitter electrode 111 flow into the drift layer 3 via the emitter layer 110 and the inverted channel region CH. The state of the movement of the electrons is schematically shown by a two-dot chain line in FIG. The depth of the trench T100 is set so that the insulating film 112 does not prevent electrons flowing through one of the channel regions CH on the left side of the drawing from moving in the drift layer 3 toward the collector electrode 6 side. 8 is adjusted so that it does not reach the silicon oxide film 2 while penetrating through it. On the other hand, holes injected from the collector electrode 6
It flows into drift layer 3 via collector layer 5 and buffer layer 4. The movement of the hall is schematically shown by a dotted line.

[0004] As a result of the electrons and holes injected from the emitter electrode 111 and the collector electrode 6 flowing into the drift layer 3, conductivity modulation occurs and the drift layer 3 has a low resistance. As a result, a main current flows between the emitter electrode 111 and the collector electrode 6.

In order to electrically isolate the IGBT element from other elements formed on the silicon layer SLP, a trench T2 is formed around the IGBT element. To ensure electrical isolation, the trench T2 extends from the surface of the silicon layer SLP to the silicon oxide film 2.

[0006]

As is apparent from the above description, the trench T100 which must not reach the silicon oxide film 2 in order not to hinder the movement of carriers, and the silicon oxide film T for electrical isolation. The depth of the groove T2, which preferably reaches 2, differs from that of the groove T2. Therefore, the groove T10
0 and T2 cannot be formed by the same one-time etching, and there has been a problem that a plurality of etching operations are required to form the trenches T100 and T2.
Since it takes time to form the groove, the manufacturing efficiency of the IGBT element is reduced. Further, the cost is increased due to the necessity of performing the etching a plurality of times.

The holes move on the surface of the silicon layer SLP, which is the surface of the IGBT element, and the electrons move to the silicon layer SL.
P moves near the silicon oxide film 2. As described above, since the paths through which the carriers move are separated from each other, there is a problem that the efficiency of the conductivity modulation is not high and the on-resistance is high.

SUMMARY OF THE INVENTION In view of the above problems, the present invention provides an IGBT having a low on-resistance, in which a groove for electrical isolation and a groove for accommodating a gate can be formed by the same etching, and a method of manufacturing the same. The purpose is to do.

[0009]

An IGB as claimed in claim 1 wherein:
T is a first conductive type drift layer formed on the insulating film and having a first groove for electrical isolation formed therein;
A second conductive type base layer and a collector layer respectively formed on a surface portion of the drift layer and isolated from each other; and the first conductive type formed inside the base layer. An emitter layer, an emitter electrode connected to the emitter layer and the base layer, a collector electrode connected to the collector layer and the drift layer, and a second electrode extending along a carrier flow direction connecting the emitter electrode and the collector electrode to each other. And a gate electrode formed inside the second groove.

An IGBT according to a second aspect is the IGBT according to the first aspect, wherein the third IGBT extends between the emitter electrode and the collector electrode along a direction intersecting the carrier flow direction. Grooves are drilled.

[0011] An IGBT according to a third aspect is the IGBT according to the second aspect, wherein the third groove is formed in the base layer.

According to a fourth aspect of the present invention, there is provided a method for manufacturing an IGBT.
The drift layer on the insulating film, the base layer having a different conductivity type from the drift layer, the drift layer is separated from the drift layer by the base layer, and the emitter layer connected to the emitter electrode and the drift layer A method for manufacturing an IGBT including a semiconductor layer having a different conductivity type and having a collector layer connected to a collector electrode, wherein a portion of the semiconductor layer serving as a first trench for performing electrical isolation is provided. First
Is formed on a portion of the semiconductor layer, which is located between the emitter electrode and the collector electrode and serves as a second groove for promoting conductivity modulation, and has a second narrower than the first opening.
A first step of forming a mask having respective openings on a surface of the semiconductor layer having both the emitter layer and the collector layer, and a step of etching the semiconductor layer using the mask. 2 steps.

According to a fifth aspect of the present invention, there is provided a method of manufacturing an IGBT,
5. The method for manufacturing an IGBT according to claim 4, wherein at least the first and second steps are performed between the first and second steps.
An etching delay film having a thickness covering the second opening while covering the opening of the first opening while leaving the space in the first opening.
The method further includes a step of forming on the semiconductor layer and the mask.

According to a sixth aspect of the present invention, there is provided a method of manufacturing an IGBT.
The drift layer on the insulating film, the base layer having a different conductivity type from the drift layer, the drift layer is separated from the drift layer by the base layer, and the emitter layer connected to the emitter electrode and the drift layer A method for manufacturing an IGBT including a semiconductor layer having a different conductivity type and having a collector layer connected to a collector electrode, wherein a portion of the semiconductor layer serving as a first trench for performing electrical isolation is provided. First
A mask having a second opening on a portion of the semiconductor layer that becomes a second groove for promoting conductivity modulation located between the emitter electrode and the collector electrode, A first step of forming on a surface having both the emitter layer and the collector layer;
A second step of selectively forming an etching delay film in a portion inside the second opening on the surface of the semiconductor layer and the mask; and forming the etching delay film on the semiconductor layer while using the mask and the etching delay film. And performing a third etching step.

According to a seventh aspect of the present invention, there is provided a method of manufacturing an IGBT.
7. The method of manufacturing an IGBT according to claim 4, wherein the concentration of impurities is higher in the emitter layer than in the base layer, and the mask is formed on the surface of the semiconductor layer. A third opening for forming a third groove in which a gate electrode is formed, which is narrower than a portion where the emitter layer is exposed, and the third opening is formed by performing the etching. After the groove is formed, the method further includes a step of oxidizing the surface of the third groove.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. In the present embodiment, the same configuration and structure as those of the related art will be described with the same reference numerals. 1 and 2 are a cross-sectional view and a plan view, respectively, illustrating the structure of a horizontal IGBT according to the present embodiment.
FIGS. 1 and 2 each illustrate the structure of the IGBT in a cross section taken along the cutting line shown on the other side.

On a silicon substrate 1, silicon oxide (S
The silicon layer SL is formed via the iO ₂ ) film 2. The silicon layer SL has a low-concentration N-type impurity diffused therein, and a drift layer 3 in contact with the silicon oxide film 2 and a P layer selectively formed on the surface of the silicon layer SL and isolated from each other. Base layer 8 and collector layer 5, N-type emitter layer 10 separated from drift layer 3 by base layer 8, and N-type buffer layer 4 surrounding collector layer 5 inside silicon layer SL. It is configured.

On the silicon layer SL, an emitter electrode 11 which contacts the emitter layer 10 and the base layer 8 while being in contact therewith.
However, a collector electrode 6 is formed so as to be in contact with the buffer layer 4 and the collector layer 5.

The silicon layer SL extends from the surface of the emitter layer 10 through the base layer 8 and the drift layer 3 to the silicon oxide film 2 in a direction parallel to the cross section of FIG. 1 (FIG. 2).
(A left-right direction in FIG. 1). The direction parallel to the cross section of FIG. 1 is a direction connecting the emitter electrode 11 and the collector electrode 6 to each other, that is, these electrodes 11, 11
6 is the direction in which the current (carrier) flows. Groove T1
A trench gate electrode 9 extending in a direction parallel to the cross section of FIG.

In the silicon layer SL, in addition to the trench T1, IGB
A groove T2 for electrically isolating the T element from other elements formed in the silicon layer SL is formed. Groove T2 is I
It is pierced around the GBT element and reaches the silicon oxide film 2 from the surface of the silicon layer SL in order to ensure electrical isolation.

When a positive bias is applied to the gate electrode 9 at the time of turn-on, the polarity of the channel region CH which is a portion of the base layer 8 near both ends of the gate electrode 9 is inverted. Electrons injected from the emitter electrode 11 flow into the drift layer 3 via the emitter layer 10 and the inverted channel region CH. Since the trench T1 of the present embodiment extends in the direction in which current flows, electrons traveling toward the drift layer 3 on the collector electrode side via the channel region CH are:
The flow is not hindered by the groove T1. Therefore, the groove T1
Has a depth that reaches the silicon oxide film 3, which has no adverse effect on the flow of electrons.

The fact that the trenches T1 and T2 have the same depth reaching the silicon oxide film 2 means that the trenches T1 and T2 can be formed simultaneously by one etching. As compared with the conventional structure shown in FIG. 25, in which the depth of the groove T100 for accommodating the gate electrode 109 and the depth of the groove T2 for electrical isolation are different from each other, etching must be performed a plurality of times. The time required is reduced. Thereby, the time required for manufacturing the IGBT element is reduced, and the productivity is improved. As a result, manufacturing costs are reduced.

At the same time that electrons flow into the drift layer 3 at the time of turn-on, holes are generated from the collector electrode 6 via the collector layer 5 and the buffer layer 4.
Flows into The electrons flow in a portion of the silicon layer SL near the silicon oxide film 2, but the holes are
L flows in a portion near the surface on which the collector layer 5 and the emitter layer 10 are formed.

The silicon layer SL has a silicon oxide film 2 on the surface where the collector layer 5 and the emitter layer 11 are formed.
The groove T3 that does not reach the hole is drilled. The trench T3 extends in a direction crossing the direction in which current flows between the emitter electrode 11 and the collector electrode 6.

The holes flowing on the surface of the IGBT element are:
The movement is inhibited by the groove T3. The holes must flow in the vicinity of the silicon oxide film 2, and the electron flow path and the hole flow path overlap. Thereby, the conductivity modulation is promoted, and the on-resistance of the drift layer 3 is lower than in the conventional case.

Further, the movement is hindered by the groove T3, so that holes are accumulated in a portion of the silicon layer SL located on the right side of the groove T3 in the cross section of FIG. The accumulated holes promote conductivity modulation and IGBT
The on-resistance of the device is further reduced.

As described above, the conductivity modulation occurs and the drift layer 3 has a low resistance. As a result, a main current flows between the emitter electrode 11 and the collector electrode 6. At the time of turn-off, a negative bias with respect to the emitter electrode 11 is applied to the gate electrode 9. At this time, the inversion of the polarity of the channel region CH disappears, and the flow of electrons from the emitter electrode 11 to the drift layer 3 stops. As a result, no conductivity modulation occurs, and no main current flows between the emitter electrode 11 and the collector electrode 6.

Embodiment 2 In the present embodiment,
A method for manufacturing the groove T3 according to the first embodiment illustrated in FIGS. 1 and 2 will be described. Hereinafter, the same configurations and structures as those already described have the same reference characters allotted, and description thereof will not be repeated.

FIGS. 3 and 4 are cross-sectional views illustrating a method of manufacturing a groove according to the present embodiment in the order of steps. The components such as the emitter electrode 11, the emitter layer 10, and the base layer 8 shown in FIGS.
Are not shown for simplicity.

First, as illustrated in FIG. 3, a mask M1 made of silicon oxide or the like is formed on the surface of the silicon layer SL. The mask M1 has an opening H2 and an opening H3 whose width in the cross section in FIG. 3 is smaller than the opening H2 by photolithography.

Next, as illustrated in FIG.
1, trenches T2 and T3 are selectively formed in the silicon layer SL under the openings H2 and H3, respectively. The groove T3 formed below the narrower opening H3 is formed shallower by the microloading effect than the groove T2 formed below the wider opening H2. still,
Although not shown, the groove T illustrated in FIGS.
1 is formed simultaneously with the grooves T2 and T3.

As described above, the opening H of the mask M1
The grooves T2 and T3 having different depths are formed at the same time by a simple configuration for realizing that the widths of H2 and H3 are different from each other. The productivity of the IGBT element is improved for the same reason that the trench T1 for housing the gate electrode 9 and the trench T2 for electrical isolation are formed at the same time in the first embodiment. Further, since the width of the groove T3 is small, the IGBT
The element becomes smaller as a whole, which is effective for shrinking.

In the above structure, a plurality of grooves having different depths are formed by one etching by the microloading effect. However, it is not limited to only such a configuration. 5 to 8 are cross-sectional views illustrating a second example of the groove manufacturing method of the present embodiment in the order of steps.

First, as illustrated in FIG. 5, a mask M2 is formed on the silicon layer SL. In the mask M2, the above-described opening H2 and an opening H3a wider than the above-described opening H3 in FIG. 3 are formed by photolithography.
Next, as illustrated in FIG. 6, a thin silicon oxide film is deposited on the surface of the semiconductor layer SL and the mask M2, and the openings H2 and H2 of the upper surface of the mask M2 and the surface of the silicon layer SL are formed.
A mask M3 is formed in a portion exposed by H3a.

Next, as illustrated in FIG.
While selectively leaving only those existing in the opening H3a among the three, the remaining part is removed by photolithography using a reticle and etching. And the mask M
Etching is performed using the remaining portion of 3 and the mask M2 to form a groove in the silicon layer SL. As illustrated in FIG. 8, the groove T3a formed below the opening H3a is smaller than the groove T2 formed by etching below the opening H2.
Becomes shallower by the amount that the mask M3 must be etched. As described above, as illustrated in FIGS. 9 and 10, the trench T2 for electrical isolation and the trench T3a for accelerating conductivity modulation are simultaneously formed in the silicon layer SL.

In the second example of the manufacturing method as described above, the trench T3a can be surely formed shallow by the mask 3 remaining in the opening 3a. For this reason, as compared with the first example of the manufacturing method which requires the accuracy of the width of the opening H3 in order to surely obtain the microloading effect as illustrated in FIGS. There is an advantage that the accuracy of the width of H3a may be low. Since the accuracy is not required, the yield of the IGBT element is improved.

Next, a third example will be described. FIG.
14 to 14 are cross-sectional views illustrating a third example of the manufacturing method in the order of steps. First, as illustrated in FIG.
A mask M3 having H2b is formed on the silicon layer SL. The opening H3b has a width approximately equal to or wider than the opening H3 illustrated in FIG. 3, and the opening 3a illustrated in FIG.
Narrower than Therefore, the width of the opening H3b is smaller than the width of the opening H2 illustrated adjacent thereto.

Next, as illustrated in FIG. 12, a polysilicon layer M5 is formed on the surface of the silicon layer SL and the mask M3.
Is deposited. At this time, the thickness of the polysilicon layer M5 is
Since the polysilicon layer M5 follows the shape of the opening H2, the opening 5a remains inside the opening H2, and the surface of the polysilicon layer M5 adheres inside the opening H3b, so that the entire inside of the opening H3b becomes the polysilicon layer M5. To the extent that it is filled by

Next, the polysilicon layer M5 is selectively etched. At this time, unlike the selective etching of the mask M3 in the second example illustrated in FIG. 7, the entire surface of the polysilicon layer M5 is etched. However, the entire etching is performed, but the portion of the polysilicon layer M5 that is present inside the opening H2 is present in the opening H3b that is completely filled due to the presence of the opening H5a. Removed earlier than part. Therefore, the polysilicon layer M5 is selectively removed and remains only inside the opening H3b as illustrated in FIG.

In this state, the silicon layer SL is etched using the mask M4 and the polysilicon layer M5.
The portion of the silicon layer SL below the opening H2 is etched faster and faster than the portion below the opening H3b where the polysilicon layer M5 remains and the microloading effect works. Therefore, when the trench T2 reaches the silicon oxide layer 2, the silicon layer SL remains in a portion below the trench T3b formed below the opening T3b.

In the third example of the manufacturing method, the trench T3b is surely shallowed by the remaining polysilicon layer M5, which is the same as that of the mask M3 of the second example illustrated in FIGS. The effect is obtained. However, FIG. 12 and FIG.
3 is performed on the entire surface of the polysilicon layer M5, and the etching for selectively removing the mask M3 by a photolithography technique using a reticle illustrated in FIG. 6 and FIG. The configuration is different from that of the second example. Therefore, the number of reticles in the third example is one less than in the second example. Further, the step of performing photolithography is not required.

Embodiment 3 In the configuration of the first embodiment illustrated in FIG. 2, the trench T3 is formed between the base layer 8 and the buffer layer 4. Therefore, there is a problem that the extension of the depletion layer generated between the P-type base layer 8 and the N-type drift layer 3 is hindered by the trench T3.
FIG. 15 is a schematic cross-sectional view illustrating the extension of the depletion layer.

Generally, the impurity concentration of the P-type base layer 8 is much higher than that of the N-type drift layer 3 (impurity concentration in the base layer 8 >> impurity concentration in the drift layer 3). Therefore, the PN between the base layer 8 and the drift layer 3
When a reverse bias voltage is applied to the junction, the depletion layer extends well from the high concentration base layer 8 to the low concentration drift layer 3 in the direction indicated by the arrow in the figure. However, even if the depletion layer tries to extend toward the collector layer 5, it can only extend to the trench T3. Therefore, the withstand voltage capability of the IGBT element when a reverse bias is applied, which is determined by the width of the depletion layer, is not sufficient.

Therefore, in the present embodiment, a configuration is shown in which the position of the groove for promoting the conductivity modulation is changed, and the extension of the depletion layer is not hindered. 16 and 17 are a cross-sectional view and a plan view, respectively, illustrating the structure of the IGBT element according to the present embodiment. IGB shown in these figures
The T element is an embodiment in which a groove T3 is formed in the drift layer 3 as illustrated in FIGS. 1 and 2 in that a groove T3c for promoting conductivity modulation is formed in the base layer 8. This is different from the IGBT element of the first embodiment. However, the configuration of the part other than this is the same.

FIG. 18 is a cross-sectional view schematically illustrating the extension of the depletion layer in the structure of the present embodiment. In this case, the depletion layer generated at the boundary between the drift layer 3 and the portion 8b of the base layer 8 located on the right side of the trench T3c can sufficiently extend to the collector layer 5 side. Therefore, it is possible to obtain the maximum value of the withstand value corresponding to the thickness of the depletion layer in the width between the base layer 8 and the collector layer 5.

Embodiment 4 FIG. In the conventional IGBT element illustrated in FIGS. 25 and 26, the emitter layer 110 and the base layer 8 extend perpendicularly to the current direction connecting the collector electrode 6 and the emitter electrode 111. And
The gate electrode 109 is formed in the emitter layer 110 and the base layer 8 with the direction in which they extend as the longitudinal direction.

On the other hand, in the structure of the first embodiment, in order to set the trench T1 to a depth reaching the silicon oxide film 2 as illustrated in FIG. A structure is employed in which the longitudinal direction of the groove T1 extends along the current direction connecting the collector electrode 11 and the collector electrode 6. Therefore,
In the cross section illustrated in FIG. 2, the trench T1 protrudes from the emitter layer 10 toward the right side.

The formation rate of an oxide film is affected by impurities contained in silicon (semiconductor device-basic theory and process technology-published by S.M.G.
368-369 etc.). Therefore, the insulating film 12 as silicon oxide formed around the gate electrode 9 is formed thick in the emitter layer 10 in which N-type impurities are diffused at a high concentration. As illustrated in FIG. 1 and FIG.
Is formed, a thin portion is locally formed in the insulating film 12 due to its shape at the upper corner of the trench T1 at a portion protruding from the emitter layer 10, and electric field concentration occurs. The gate breakdown voltage cannot be obtained. Therefore, in the present embodiment, the emitter layer is formed to have a larger width, and the trench for accommodating the gate electrode and the insulating film are formed therein.

FIGS. 19 and 20 show the IG of this embodiment.
It is sectional drawing which illustrates the structure of a BT element. As is apparent from comparison with the IGBT element of the third embodiment illustrated in FIGS. 16 and 17, in the present embodiment, the emitter layer 10a is formed wider than the gate electrode 9 and the insulating film 12. ing. As apparent from FIG. 20 in particular, in the cross section illustrated in FIG. 20, the gate electrode 9 and the insulating film 12 are completely contained in the emitter layer 10a.

Accordingly, the insulating film 12 of the present embodiment formed by oxidizing the surface of the trench T1 formed in the emitter layer 10a, the base layer 8, and the drift layer 3 is illustrated in FIGS. Compared to the configuration of the third embodiment, the number of portions existing in the emitter layer 10a increases, and therefore, the portion which is made thicker by the accelerated oxidation by high-concentration impurities increases. Thereby, the gate withstand voltage is improved as compared with the configuration of the third embodiment. Further, the configuration in which the width of the emitter layer 10a is widened does not prevent the trench T3c from being formed in the base layer 8. Therefore, similarly to the third embodiment, the effect that the expansion of the depletion layer is not hindered can be obtained.

Embodiment 5 FIG. In the present embodiment,
Grooves T3 to T described in the first to fourth embodiments
Variations in the position and length where 3c is formed will be described. In the following description, the variation is described using the groove T3, but the same applies to the grooves T3a to T3c.

FIG. 21 is a sectional view showing a first example of the position and length of the groove T3. One trench T <b> 3 is formed at a length and position including an extension in the direction A (shown by a dashed line) of the emitter layer 10 surrounding one gate electrode 9. Here, a direction perpendicular to the longitudinal direction of the collector layer 5 is defined as a direction A. One trench T3 is formed for each gate electrode 9.

The presence of the trench T3 on the extension of the emitter layer 10 affects the holes that are not shown when the emitter electrode 11 and the collector electrode 6 are turned on at the time of turn-on, and promotes the conductivity modulation described in the first embodiment. The effect is obtained. When a reverse bias voltage is applied to the emitter electrode 11 and the collector electrode 6 (not shown), a depletion layer is formed in a portion of the drift layer 3 remaining between the plurality of trenches T3 (a portion at a boundary between the trenches T3). Spreads. Therefore, the IGBT element is higher in the case of the groove T3 illustrated in FIG. 21 than in the case where one groove T3d is formed in the IGBT element for the plurality of gate electrodes 9 illustrated in FIG. Withstand pressure.

To promote the conductivity modulation, it is necessary to inhibit the movement of the holes flowing into the base layer 8 on the surface. On the other hand, in order to guarantee the expansion of the depletion layer, it is necessary to secure a region other than the portion that hinders the movement of holes. Another example satisfying these two requirements is a configuration illustrated in FIGS. 23 and 24, respectively.

FIGS. 23 and 24 are sectional views showing other two examples. In the second example illustrated in FIG. 23, the trench T3 has a boundary extending from the center line of the gate electrode 9 in the direction A in the direction A. FIG.
In the third example illustrated in FIG. 4, the part that is the boundary of the groove T3 in FIG. 21 and the part that is the boundary of the groove T3 in FIG. 23 are all the boundary of the groove T3. . In these examples, the above two requirements are satisfied.

[0056]

According to the first aspect of the present invention, since the gate electrode is formed inside the second groove extending along the carrier flow direction, the gate electrode is formed between the emitter electrode and the collector electrode. Does not obstruct carrier flow. Therefore, even if the second groove has a depth reaching the insulating film, the flow of carriers is ensured, and the first and second grooves, which conventionally had to have different depths, can be formed simultaneously. As a result, the number of steps for forming the groove is omitted, and the IGBT is formed.
Is simple and quick.

According to the second aspect of the present invention, the holes are accumulated on the side surface of the third groove on the collector layer side, and the flow paths of the holes and the electrons overlap, so that the conductivity is increased. Modulation is promoted. With this, the IGBT
Is reduced.

According to the third aspect of the present invention, the base layer has the third groove formed therein so that the third layer is formed.
A part of itself remains between the trench and the collector layer. This remaining portion prevents the depletion layer from being restricted from spreading between the base layer and the drift layer having different conductivity types. With this, IGB
The withstand voltage capability of T is improved.

According to the structure of the fourth aspect, the micro-loading effect acts on the narrower second groove, and the second groove is formed even if the first and second grooves are formed simultaneously by etching.
Is shallower than the first groove. The first groove, which preferably has a depth reaching the insulating film for electrical isolation, and the first trench, for which the drift layer must remain between the insulating film and itself for the flow of carriers. Since two grooves having different depths from each other can be formed at the same time,
The efficiency of GBT production is improved.

According to the fifth aspect of the present invention, in the etching delay film, the portion existing in the first opening where the space remains is removed promptly by etching, and the narrower second film is formed.
The portion existing in the opening of the above remains. By adding a process of forming an etching delay film,
Simultaneously forming the first and second grooves having different depths from each other can be performed in a state where the accuracy required for the width of the second groove is low. Thereby, the yield of the IGBT is improved. Further, the structure according to claim 5, which has to be formed on the entire surface, rather than the structure according to claim 6, in which the etching delay film must be selectively formed on the surface of the semiconductor layer and the mask, There are few restrictions on the above.

According to the structure of the sixth aspect, even if the first and second grooves are simultaneously formed by etching, the second groove is necessarily shallower than the first groove by the etching delay film. .

According to the structure of the seventh aspect, the emitter layer containing more impurities is oxidized to obtain an oxide film for insulating the gate electrode. Since the oxide film becomes thicker when more impurities are present, the withstand voltage capability of the oxide film for insulating the gate electrode is improved.

[Brief description of the drawings]

FIG. 1 is a cross sectional view showing an example of a structure of an IGBT element according to a first embodiment.

FIG. 2 is a cross sectional view showing an example of the structure of the IGBT element according to the first embodiment.

FIG. 3 is a sectional view illustrating a first example of a method for manufacturing an IGBT element according to a second embodiment in the order of steps.

FIG. 4 is a cross-sectional view showing a first example of a method for manufacturing an IGBT element according to the second embodiment in the order of steps.

FIG. 5 is a sectional view illustrating a second example of the method of manufacturing the IGBT element according to the second embodiment in the order of steps.

FIG. 6 is a sectional view illustrating a second example of the method of manufacturing the IGBT element according to the second embodiment in the order of steps.

FIG. 7 is a sectional view illustrating a second example of the method of manufacturing the IGBT element according to the second embodiment in the order of steps.

FIG. 8 is a sectional view illustrating a second example of the method of manufacturing the IGBT element according to the second embodiment in the order of steps.

FIG. 9 is a sectional view showing an example of the structure of the IGBT element according to the second embodiment.

FIG. 10 is a sectional view showing an example of the structure of an IGBT element according to a second embodiment.

FIG. 11 is a sectional view illustrating a third example of the method of manufacturing the IGBT element according to the second embodiment in the order of steps.

FIG. 12 is a sectional view illustrating a third example of the method of manufacturing the IGBT element according to the second embodiment in the order of steps.

FIG. 13 is a sectional view illustrating a third example of the method of manufacturing the IGBT element according to the second embodiment in the order of steps.

FIG. 14 is a sectional view illustrating a third example of the method of manufacturing the IGBT element according to the second embodiment in the order of steps.

FIG. 15 is a cross-sectional view illustrating the expansion of a depletion layer.

FIG. 16 is a sectional view showing an example of a structure of an IGBT element according to a third embodiment.

FIG. 17 is a cross sectional view showing an example of the structure of the IGBT element according to the third embodiment.

FIG. 18 is a cross-sectional view illustrating the expansion of a depletion layer.

FIG. 19 is a sectional view showing an example of the structure of the IGBT element according to the fourth embodiment.

FIG. 20 is a sectional view showing an example of the structure of the IGBT element according to the fourth embodiment.

FIG. 21 is a cross sectional view showing a first example of the structure of the IGBT element according to the fifth embodiment.

FIG. 22 is a sectional view showing an example of the structure of the IGBT element.

FIG. 23 is a cross sectional view showing a second example of the structure of the IGBT element according to the fifth embodiment.

FIG. 24 is a sectional view showing a third example of the structure of the IGBT element according to the fifth embodiment.

FIG. 25 is a cross-sectional view showing a conventional IGBT element.

FIG. 26 is a sectional view showing a conventional IGBT element.

[Explanation of symbols]

Reference Signs List 1 silicon substrate, 2 silicon oxide film, 3 drift layer, 4 buffer layer, 5 collector layer, 6 collector electrode, 8 base layer, 9 gate electrode, 10, 10a emitter layer, 11 emitter electrode, 12 insulating film, A direction, CH channel region, H2, H3, H3a, H3b
Opening, M1-M4 mask, M5 polysilicon layer,
SL, SLP silicon layer, T1 to T3, T3a to T3
d groove.

Claims (7)

[Claims] A first conductive type drift layer formed on an insulating film and having a first groove for electrical isolation formed therein; and a first conductive type drift layer formed on a surface portion of the drift layer. A second conductive base layer and a collector layer separated from each other, the first conductive type emitter layer formed inside the base layer, and the emitter layer and the collector layer. An emitter electrode connected to the base layer, a collector electrode connected to the collector layer and the drift layer, and a second groove extending along a carrier flow direction connecting the emitter electrode and the collector electrode to each other. An IGBT comprising a gate electrode. 2. The IGBT according to claim 1, wherein a third groove extending along a direction intersecting with the carrier flow direction is formed between the emitter electrode and the collector electrode. IGBT. 3. The IGBT according to claim 2, wherein the third groove is formed in the base layer.
T. 4. A drift layer on an insulating film, a base layer having a different conductivity type from the drift layer, an emitter layer separated from the drift layer by the base layer, and connected to an emitter electrode; An IGBT including a semiconductor layer having a conductivity type different from the drift layer and having a collector layer connected to a collector electrode;
Wherein a first opening is formed on a portion of the semiconductor layer that is to be a first groove for performing electrical isolation, and wherein the first opening is formed on the emitter electrode and the collector electrode of the semiconductor layer. A mask having a second opening narrower than the first opening on a portion serving as a second groove for promoting conductivity modulation positioned between the emitter layer and the collector of the semiconductor layer; A method for manufacturing an IGBT, comprising: a first step of forming on a surface having both layers; and a second step of etching the semiconductor layer using the mask. 5. The method of manufacturing an IGBT according to claim 4, wherein at least the first and second openings are covered between the first and second steps. A method for manufacturing an IGBT, further comprising: forming an etching delay film having a thickness that closes the second opening on the semiconductor layer and the mask while leaving a space. 6. A drift layer on an insulating film, a base layer having a conductivity different from that of the drift layer, an emitter layer separated from the drift layer by the base layer and connected to an emitter electrode, An IGBT including a semiconductor layer having a conductivity type different from the drift layer and having a collector layer connected to a collector electrode;
Wherein a first opening is formed on a portion of the semiconductor layer that is to be a first groove for performing electrical isolation, and wherein the first opening is formed on the emitter electrode and the collector electrode of the semiconductor layer. A mask having a second opening on a portion serving as a second groove for promoting conductivity modulation located therebetween is formed on a surface of the semiconductor layer having both the emitter layer and the collector layer. A first step, a second step of selectively forming an etching delay film in a portion within the second opening on the surface of the semiconductor layer and the mask, and using the mask and the etching delay film. And performing a third step of etching the semiconductor layer. 7. The method for manufacturing an IGBT according to claim 4, wherein said emitter layer has a higher impurity concentration than said base layer, and said mask has A third opening for forming a third groove in which a gate electrode is formed, the third opening being narrower than a portion where the emitter layer is exposed on the surface of the semiconductor layer, wherein the etching is performed; Further comprising, after the third groove is formed, oxidizing a surface of the third groove.
GBT manufacturing method.