JPH1140773A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a new semiconductor storage device for which the area increase caused by capacitor machining can be suppressed, when a material including lead or bismuth is used for the dielectric film of a capacitor. SOLUTION: Lower electrodes 103 are separated for each cell and are formed, and then the area between the electrodes is buried by an insulator film 102, a dielectric film 104 consisting of a material including at least lead or bismuth is continuously formed over a plurality of cells, and an area above the dielectric film 104 is covered with an upper electrode 105. The oxide of a metal element with at least quadrivalent valence in an element for constituting the dielectric film 104 is used as the material of the insulator film 102, thus reducing a region for separating memory cells and hence improving integration.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a capacitor, and more particularly to a semiconductor memory device suitable for application to a large-scale integrated circuit.

[0002]

2. Description of the Related Art Lead zirconate titanate (hereinafter "PZT")
Has a high dielectric constant and ferroelectric properties. Recently, D.P.
RAM (dynamic random access memory) and non-volatile memory have been actively developed. These memories are attracting attention because of the possibility that high integration, low power supply voltage, high-speed writing, and the like, which cannot be achieved by conventional techniques, can be obtained.

[0003] PZT has a composition represented by Pb (Zr, Ti) O ₃ and contains divalent lead, tetravalent zirconium and titanium as metal elements. Lead has a property of causing a reaction with other materials of a semiconductor device, and requires careful handling. For example, in a nonvolatile memory, a metal film to be a lower electrode is uniformly formed on an element layer including a transistor, and a PZT film is formed thereon at a high temperature of about 700 ° C., and then the metal film and the PZT film are formed. Is cut for each memory cell (hereinafter simply referred to as a “cell”) by dry etching, and further, a capacitor is formed by forming an upper electrode on each of the cut PZT films. I have.

[0004] In this case, the reaction is particularly likely to occur during the formation of the PZT at a high temperature, so that the PZT must be formed first, and the insulator is filled after the formation of the capacitor.
The T film is necessarily separated for each cell. Such a structure is described in, for example, the 1995 VLSI Technology Symposium Digest (1995 Symposium on VLSI Techno
Logic Digest of Technical Papers) on pages 123 and 124.

In the case where the PZT film has a structure in which the PZT film is separated for each cell, an extra area is required between the cells, and a processing mask for simultaneously processing the metal film serving as the lower electrode and the PZT film and a processing of the upper electrode. It is inevitable to use two masks.

In general, when a memory is highly integrated, it is necessary to minimize an increase in the area of the entire chip in order to suppress an increase in manufacturing cost. For this reason, there is a need for a technique for reducing the occupied area per cell and storing many cells in the same area. On the other hand, as is widely known in the prior art, a margin is required in consideration of an error in accordance with a mask pattern in order to guarantee connection or insulation between layers. Since the margin causes an increase in the occupied area of the cell, it is necessary to reduce the number of alignment steps as much as possible.

When two masks are used as described above, of the occupied area of the capacitor, the area secured as a margin for alignment of the two masks does not function as a capacitor, leading to an increase in the occupied area. Further, in general, it is unavoidable that the side wall of the capacitor is seriously damaged by dry etching for cutting the metal film and the PZT film, thereby reducing the capacitor area. . It has been clarified that these increase in area becomes a serious obstacle to high integration.

As in the case of PZT, another material containing bismuth, for example, strontium bismuth tantalate, is known as a ferroelectric material whose use in a memory is being studied. However, bismuth has a property of causing a stronger reaction than lead, and therefore, a memory using a material containing bismuth has the same problem as the case where PZT is used.

[0009]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art, and to increase the area caused by processing a capacitor when a material containing lead or bismuth is used for a dielectric film of the capacitor. It is an object of the present invention to provide a novel semiconductor memory device capable of suppressing the problem.

[0010]

In order to reduce the number of alignment steps by using a single mask for processing a capacitor, a lower electrode is preliminarily processed for each cell and then a dielectric film is formed on the entire surface of the memory. A well-known structure in which an upper electrode is formed thereon and the dielectric film and the upper electrode are not processed for each cell. In this case, the insulator film that fills the space between the lower electrodes of each cell needs to be formed before forming the dielectric film. The dielectric film is formed in contact with the upper surfaces of the lower electrode and the insulator film after the formation thereof.

The inventor of the present invention has found that, among the constituent elements of the dielectric containing lead or bismuth, an oxide of a metal element having a valence of four or more has little reaction and does not hinder and fills the gap between the lower electrodes. It has been found that it can be used as an insulator film. As an oxide of such a metal element, for PZT,
For example, titanium oxide is used for strontium bismuth tantalate, and for example, tantalum oxide is used.

The reaction of PZT with the insulator occurs when lead enters the insulator at a high temperature and the insulator is in a molten state, and the insulator is the most common silicon oxide in a semiconductor device. In this case, PZT and P
It was found that the insulator in contact with ZT was lead glass, and the relative dielectric constant was significantly reduced. When the insulator is titanium oxide, such a reaction is hardly observed, and PZT
No decrease in the relative dielectric constant was observed.

The present invention has been made based on the above findings. That is, the object of the present invention is to form a lower electrode separately for each cell, fill the space between the electrodes with an insulator film, and then form a film made of a material containing at least one of lead and bismuth on a plurality of cells. And the upper surface of the dielectric film is covered with an upper electrode, and has a valence of four or more of the elements constituting the dielectric film as a material of the insulator film. The problem can be solved effectively by using an oxide of a metal element.

Note that the order of forming the lower electrode and the insulator film can be opposite to the above, with the insulator film first, and the same effect can be obtained.

In addition, it is desirable that the surface of the lower electrode and the surface of the insulator film are smoothly connected to each other at the peripheral portion of each lower electrode, and that a step is suppressed. By flattening the surface of this portion, the thickness of the dielectric film becomes uniform, and a capacitor with stable characteristics and high reliability can be obtained.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the semiconductor memory device according to the present invention will be described below in detail with reference to embodiments shown in some drawings.

[0017]

In FIG. 1, 101 is an element layer including a transistor formed by a known method, 103 is a lower electrode formed for each cell on the element layer 101, and 102 is a lower electrode 103 embedded therein. Titanium oxide insulator film formed by
Denotes a PZT dielectric film uniformly formed on both the lower electrode 103 and the insulator film 102, and 105 denotes an upper electrode formed on the upper surface of the dielectric film 104. Dielectric film 104 and upper electrode 105
Is continuous over a plurality of cells.

The lower electrode 103 and the insulator film 102 are made of a dielectric film 104
2 is shown in FIG. The dielectric film 104 is formed uniformly over the entire surface of the drawing. The lower electrodes 103 are arranged alternately, but the arrangement is not limited to this, and other arrangements such as a lattice shape are possible.

The manufacturing process of the semiconductor memory device having the above structure will be described below with reference to FIGS. After forming an element layer 101 including a field effect transistor and the like by using a known method, as shown in FIG. 3, a platinum thin film 401 was formed on the same layer by DC sputtering to a thickness of 200 nm. Next, using an etching mask, the thin film 40 is formed by photolithography.
1 was etched to form a lower electrode 103 for each cell (see FIG. 4).

Subsequently, a titanium oxide film 601 was formed on this pattern to a thickness of 500 nm as shown in FIG. For this formation, titanium isopropoxide [Ti (i-OC ₃ H ₇ )
_4] the MOCVD method as a raw material (metal organic chemical vapor deposition)
Was used. Since titanium isopropoxide is liquid at room temperature, the raw material was heated in a thermostat at 45 ° C. to increase the vapor pressure, and argon was introduced as a carrier gas into the reaction chamber. The flow rate of the carrier gas is set to 200 cc / min,
At the same time, oxygen was supplied at 500 cc / min to the reaction chamber. By setting the substrate temperature to 350 ° C., the titanium oxide (T
An iO ₂ ) thin film was obtained.

The raw material for the titanium oxide thin film is not limited to the above, and other alkoxide raw materials, complex raw materials, and halide raw materials can be used, and the thin film can be formed by the CVD method. However, in any case, since the thin film immediately after formation does not have sufficient insulating properties, a heat treatment at 750 ° C. is further performed in an atmosphere containing oxygen to obtain a desired titanium oxide.

Next, a photoresist is applied on the titanium oxide film 601 and the film 601 is etched by a known etch-back method to flatten its surface. The surface of the film 601 was smoothly connected. Thereby, the peripheral portion of the lower electrode 103
The step is suppressed, and the surface is flattened. As described above, the lower electrode 103 is embedded in the insulator film 102 of titanium oxide in FIG.
The structure shown in FIG. In addition, as a flattening method, a known method using a chemical mechanical polishing method can be applied.

Subsequently, the surfaces of the completed buried lower electrode 103 and the insulator film 102 are formed by a known RF (high frequency) sputtering method with a composition of Pb / Zr / Ti = 1 / 0.5 / 0.5. 150 nm of mixed amorphous mixed oxide at room temperature
Formed. This thin film was crystallized by a rapid oxidation method using a lamp heating device at 700 ° C. for 30 seconds to obtain a dielectric film 104 of a polycrystalline PZT thin film having a perovskite structure. Furthermore,
A platinum thin film was formed on the film to form an upper electrode 105 (see FIG. 1).

The dielectric film 104 was a PZT thin film made of a single perovskite phase at a portion in contact with the lower electrode 103, and a PZT thin film mixed with a pyrochlore layer at a portion in contact with the insulator film 102. As is widely known, a PZT thin film in which a pyrochlore phase is mixed has a dielectric constant less than half that of a PZT thin film having a single phase of perovskite. Typically, the relative permittivity of perovskite single-phase PZT is about 1500, while the permittivity of PZT mixed with a pyrochlore layer is about 300. As a result, it has been found that the capacitance between the adjacent lower electrodes 103 is suppressed, the amount of signal leakage between the adjacent electrodes is reduced, and the operation of the capacitor is stabilized.

In the above steps, the mask used for processing the capacitor for cell isolation is only for the lower electrode 103, and is not used for the dielectric film 104 and the upper electrode 105. The mask used for the same film and the same electrode can be used as a mask for the minimum processing required for the operation of the memory device (for example, processing for separating the memory cell region from the other region). The requirements for processing accuracy are greatly relaxed as compared with the case where the electrodes are separated for each cell.

Further, by not performing the cell separation process on the dielectric film 104, it is possible to avoid the damage of the capacitor side wall due to the dry etching which has been conventionally seen.

Further, since the lower electrode 103 is embedded in the insulator film 102 and the step in the peripheral portion is suppressed, the thickness of the dielectric film 104 becomes uniform, and the lower electrode 103 has a step in the peripheral portion. The deterioration of the capacitor characteristics that occurs during the operation is suppressed.

For comparison, a similar structure was prepared by a conventional technique. That is, the insulator film 102 was formed using a material mainly containing silicon oxide. The resulting structure is shown in FIG. The portion of the PZT dielectric film that is in contact with the insulator film 102 becomes a deteriorated film 202, and the original PZT dielectric film is
The dielectric film 106 was left on the lower electrode 103 with a size smaller than that of the lower electrode 103.

In order to investigate the cause, a reaction between a mixed oxide having a PZT composition and a silicon oxide was examined.
The following was found.

This reaction becomes remarkable from 500 ° C., and the distance that lead penetrates into silicon oxide increases as the temperature increases. This distance is 50 nm at 500 ° C. and 100 nm at 600 ° C. when the silicon oxide is a thermal oxide film and the dielectric is an amorphous mixed oxide having a PZT composition.
Met. At 700 ° C. or higher, the reactants are in a molten state, and in a PZT thin film having a thickness of less than 300 nm, P
The interface between ZT and silicon oxide disappeared. From the composition analysis, it was found that lead was diffused in a large amount in the compound generated by the reaction, and the reaction product of the altered film 202 was
It was determined to be lead glass. The relative dielectric constant of this reaction product is several tens, which is orders of magnitude smaller than that of PZT.

Since the reaction with lead is remarkable even at 500 ° C. as described above, it is impossible to cope with the reduction of the PZT forming temperature. In the above comparative experiment, PZT was crystallized at 600 ° C., but at 600 ° C., the crystallization of PZT was insufficient compared with 700 ° C. according to the present embodiment, and the dielectric constant, spontaneous polarization, etc. The physical properties of the films required for the operation of the semiconductor memory device are not sufficient. Nevertheless, the reaction was intense in the thin film containing silicon oxide as a main component, and the appearance of the reaction progressing from the periphery of the lower electrode 103 was evident by cross-sectional electron microscope observation.

Since this reaction is intense, lead diffuses in the lateral direction also on the upper surface of the lower electrode 103,
The PZT thin film near the periphery was changed to the deteriorated film 202. As a result, in the PZT thin film on the upper surface of the lower electrode 103, the portion where high dielectric constant and spontaneous polarization can be detected is limited to the region indicated by 106 in FIG. 7, and the effective area is greatly reduced. Therefore, the effect of increasing the effective area due to the removal of the alignment error and avoiding the damage of the capacitor side wall due to the dry etching cannot be obtained. Further, when the crystallization temperature was set to the above-mentioned 700 ° C., the reaction was more intense and the reactants were in a molten state, so that even the structure of FIG. 7 could not be obtained.

As described above, when a lead-containing dielectric thin film that needs to be subjected to a heat treatment of at least 500 ° C. at the time of formation is employed, the present invention makes it possible to form a structure corresponding to FIG. 1 for the first time.

Here, another manufacturing method suitable for realizing the structure of the present invention will be described with reference to FIGS. As in the case of the above-described manufacturing process, a layer 101 including an active element, for example, a field-effect transistor is formed using a known method. Next, an insulator film is deposited, and a pattern 801 from which a portion of the insulator film corresponding to the lower electrode has been removed is formed by a known lithography and etching method (see FIG. 8). Subsequently, a conductive plug layer (a layer for electrically connecting the lower electrode 103 to the transistor, not shown) and a barrier layer (not shown) are formed below the lower electrode 103 in the element layer 101, Thereafter, as shown in FIG. 9, a metal thin film 901 serving as a lower electrode is deposited on the entire surface including the pattern 801 by a sputtering method. Next, after a silicon oxide film is formed by a known CVD method or coating method, the entire upper surface is flattened to obtain a film 1001 (see FIG. 10). Thereafter, the film 901 and the film 801 are scraped by an etch-back method or a chemical mechanical polishing method until the metal thin film 901 and the insulator film 801 form a flat plane, and the lower electrode 1102 shown in FIG. Create an embedded structure. Subsequent steps are the same as those described above.

The advantages of this manufacturing method are that the insulator film is easily deposited and the thickness of the lower electrode 1102 is less limited. That is, at the time of forming the insulator film, since the underlayer is almost flat, a process for forming the step structure uniformly (CVD)
Is unnecessary. Preferably, a metal titanium thin film is formed by a known DC sputtering method, and the thin film is formed in an oxygen atmosphere for 8 minutes.
By oxidizing at 00 ° C. for 30 minutes, a titanium oxide thin film having an insulating property required for an insulator film can be easily obtained.

Further, since the lower electrode 1102 and the heat treatment for improving the insulating property of the titanium oxide can be performed before the formation of the conductive plug layer and the barrier layer in the element layer 101 existing below the lower electrode 1102, Oxidation of the lower electrode 1102 and oxidation of the conductive plug layer and barrier layer do not occur. When the lower electrode and the conductive plug layer and the barrier layer are formed first, for example, when the lower electrode is made of platinum, since platinum has a property of passing oxygen, it is necessary to suppress the deterioration of the lower layer of the lower electrode due to oxidation. In this case, it is necessary to increase the thickness of platinum according to the heat treatment temperature and the treatment time, which makes the processing difficult. This step has the advantage of not having this limitation.

Next, another embodiment of the present invention is shown in FIG. In this embodiment, an insulating film 301 containing silicon oxide as a main component is formed before forming the insulating film 102, and the lower electrode 103 is formed of a stacked film of the insulating film 301 and the insulating film 102. Embedded inside. Dielectric film 104 and silicon oxide film 301
The insulator film 102 for suppressing the reaction with the lower electrode 103 is formed without any step with the lower electrode 103, and the effect of the present invention can be obtained also by this structure.

As a dielectric material, a material containing lead is used in the above two embodiments. However, the present invention is not limited to this material but can be applied to other materials which react with silicon oxide at the forming temperature. Yes, a similar effect can be obtained. In particular, bismuth-containing materials are particularly useful because bismuth, like lead, reacts violently with silicon oxide. That is, the preferred dielectric material of the present invention is an oxide dielectric material containing lead or bismuth.

Other applicable materials other than PZT include lead titanate (PbTiO ₃ ), barium lead zirconate titanate [(Ba, Pb) (Zr, Ti) O ₃ ], barium lead niobate [(Ba, Pb) Nb ₂ O ₆ ], strontium bismuth tantalate (Sr ₂ Bi ₂ Ta ₅ O ₉ and SrBi ₂ Ta ₂ O ₉ ), and bismuth titanate (Bi ₄ Ti ₃ O ₁₂ ). The present invention can be applied to all dielectrics having these as a basic structure and mixed materials thereof. That is, (A1A2
. . _{) (B1B2 ..) O x (} A1 = Pb, Bi; A2 = C
a, Sr, Cd, Ba, La, Tl, Na, K; B1, B2 = T
a, Ti, Zr, Hf, Fe, Nb, Sn, U, Al, Mn,
W, Yb, Sc, In, Sb, Co, Zn, Li, Mo, Ni,
Oxides described in the form of Co) and mixtures thereof may be used. The present invention also includes a case where the above-described material is used as a main component and other elements are mixed therewith.

In this embodiment, a titanium oxide film is used as the insulator film.
1, the elements listed as B2, that is, Ta, Ti,
Zr, Hf, Fe, Nb, Sn, U, Al, Mn, W, Yb, S
A film mainly composed of an oxide of an element selected from c, In, Sb, Co, Zn, Li, Mo, Ni, and Co is effective. These elements have a valence of four or more in the above oxide.

In this embodiment, platinum is used as the electrode material. However, metals and alloys mainly composed of elements selected from Pd, Ni, and Pt, or V, Cr, Fe, Ru, In, Sn, and
A material containing an oxide of an element selected from Re, Ir, Pb, Cu, and Pd as a main component is also applicable.

In this embodiment, as the method of forming the insulator film 102, the CVD method and the thermal oxidation of the metal thin film have been described. However, the present invention is not limited thereto, and reactive sputtering in an oxygen-containing atmosphere and sol-gel coating method can also be applied. It is. In this embodiment, a sputtering method is used as a method for forming the dielectric film 104. However, the present invention is not limited to this, and an MOCVD method, an evaporation method, and a sol-gel method can be applied. In addition, for deposition on a flat surface, a vapor deposition method and a sol-gel method are particularly effective.

FIG. 13 shows an example in which the semiconductor memory device formed by the above method is configured as a DRAM. PZT was used as the dielectric film of the capacitor. An element layer including a transistor is formed on the Si substrate 1201 by a known process. That is, the element region isolation film 1202, the conductive impurity diffusion layer 12
03, a polysilicon transistor gate electrode 1204, polysilicon wirings 1205 and 1206, and an interlayer insulating film 1207 are formed. Next, a conductive plug 1208 for electrically connecting the capacitor to the transistor is formed. The plug is a laminated film of titanium nitride / titanium silicide formed by a CVD method. Alternatively, the laminated film may be a titanium nitride / polysilicon laminated film. The structure shown in FIG. 13 was obtained by laminating the capacitor of the present invention described in the embodiment of FIG. 1 on the element layer thus formed.

[0044]

According to the present invention, a dielectric film has a capacitor which is continuous over a plurality of memory cells, and
A semiconductor memory device in which a material containing lead or bismuth can be used as the material of the dielectric film can be realized. Further, since the alignment margin at the time of processing the capacitor can be made almost unnecessary, the area for separating the memory cells from each other can be reduced, and the degree of integration can be increased.

[Brief description of the drawings]

FIG. 1 is a sectional view for explaining an embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a plan view showing an arrangement of a lower electrode embedded in an insulator film.

FIG. 3 is a cross-sectional view for explaining a first stage of a process of forming a capacitor.

FIG. 4 is a cross-sectional view for explaining a second step of the process of forming the capacitor.

FIG. 5 is a cross-sectional view for explaining a third step of the process of forming the capacitor.

FIG. 6 is a cross-sectional view for explaining a fourth step in the process of forming the capacitor.

FIG. 7 is a cross-sectional view illustrating a comparative example according to the related art.

FIG. 8 is a cross-sectional view for explaining a first stage of another process for producing a capacitor.

FIG. 9 is a cross-sectional view for explaining a second step of another process for producing a capacitor.

FIG. 10 is a sectional view illustrating a third step of another process of manufacturing the capacitor.

FIG. 11 is a sectional view illustrating a fourth step of another process for producing a capacitor.

FIG. 12 is a sectional view for explaining another embodiment of the present invention.

FIG. 13 is a sectional view for explaining still another embodiment (DRAM) of the present invention.

[Explanation of symbols]

 101: element layer including a transistor 102, 1101: insulator film 103, 1102: lower electrode 104: dielectric film 105: upper electrode 301: silicon oxide film

Claims (11)

[Claims] A lower electrode formed on an element layer including a transistor for each memory cell; an insulator film exposing an upper surface of the lower electrode to bury the lower electrode; And a plurality of capacitors constituted by a dielectric film continuously formed over a plurality of memory cells on both the insulator film and an upper electrode formed on the dielectric film. The dielectric film contains at least one element selected from the group consisting of lead and bismuth, and the insulator film further has a tetravalent or higher valence among the elements constituting the dielectric film. A semiconductor memory device, which is an oxide of a metal element having a valence. 2. The semiconductor memory device according to claim 1, wherein an upper surface of said lower electrode and an upper surface of said insulator film are flush with each other near a periphery of said lower electrode. 3. The semiconductor memory device according to claim 1, wherein said dielectric film is made of lead zirconate titanate. 4. The semiconductor memory device according to claim 1, wherein said dielectric film is made of strontium bismuth tantalate. 5. The semiconductor memory device according to claim 3, wherein said insulator film is made of titanium oxide. 6. A method according to claim 1, wherein at least one of said lower electrode and said upper electrode is made of a material mainly containing a metal element selected from the group consisting of platinum, iridium, ruthenium, palladium and nickel. Claim 1
The semiconductor memory device according to claim 5. 7. The semiconductor memory device according to claim 1, wherein said element layer and said plurality of capacitors form a dynamic random access memory. 8. The semiconductor memory device according to claim 1, wherein a nonvolatile memory is formed by said element layer and said plurality of capacitors. 9. The method according to claim 1, further comprising the step of forming the dielectric film by any one of a sputtering method, an evaporation method, and a solution coating method. 10. The method according to claim 1, further comprising the step of forming the insulator film by a CVD method. 11. The method according to claim 1, further comprising the step of forming said insulator film by a thermal oxidation method.