JPH1140699A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the inductance and noise of a semiconductor package having an SON structure formed by laying the outer lead sections of leads on a semiconductor chip, without sacrificing the miniaturization of the whole body of the package. SOLUTION: Each lead 12 of a lead frame is bonded to, for example, the main surface of a semiconductor chip 11 through an adhesive tape 13 carrying a conductive sheet 13b for shielding nearly the whole surface of the chip 11. Then, electrode pads 11a' assigned for grounding or power supply are electrically connected to the leads 12 with gold wires 14a and 14b through the conductive sheet 13b. Thus, the inductance and nose of a semiconductor package are reduced by setting the potentials between the semiconductor chip 11 and the leads 12 to the same potential.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, an area mount type semiconductor device, and more particularly to a semiconductor package having an SON (Small Outline Non-lead) structure in which outer leads of leads are laid out on a semiconductor chip. It is used for.

[0002]

2. Description of the Related Art As is well known, in recent years, various types of small electronic devices have been developed, as represented by portable electronic devices, and some of them have been remarkably popularized. In the development of such a small electronic device, it is essential to use a small and high-performance semiconductor package. Therefore,
With the progress of small electronic devices, the demand for miniaturization and high performance of semiconductor packages is increasing year by year.

As one of the small and high-performance semiconductor packages, an area mount type semiconductor device employing an SON structure has recently been receiving attention. This has no outer leads extending from the package, and allows mounting on a circuit board by one end surface of the leads exposed on the outer peripheral surface of the package, thereby realizing a smaller mounting area.

FIG. 6 shows a schematic configuration of the above-mentioned conventional SON structure semiconductor package. The semiconductor package 100 is a well-known TSOP (Thin Small Out).
line Package) and SOJP (Small Outline J-Lead Pac)
Similarly to the conventional LOC (Lead On Chip) structure, the configuration is similar to that of the conventional LOC (Lead On Chip).

That is, each lead 102 of a lead frame is adhered to the surface of a semiconductor chip 101 with an adhesive tape 103, and each pad 101 a on the chip 101 and an inner lead portion 102 a of each lead 102 are connected via a gold wire 104. And electrically connect the gold wire 1
04, and the periphery of the chip 101 is sealed with a mold resin 105.

Each of the leads 102 is formed in a wing shape on the outer lead portion 102b side, and is formed so as to be planarly exposed from the upper surface (mounting surface) of the mold resin 105.

The semiconductor package 100 having the SON structure
In this case, the size of the entire package is reduced by trimming the outer lead portions 102b of the respective leads 102 on substantially the same plane as the side surfaces without protruding from the outer peripheral surface of the mold resin 105.

However, in the above-described conventional semiconductor package 100 having the SON structure, the semiconductor chip 1 having the center pad structure in which the pad 101a is provided at the center of the chip is provided.
01, etc., the inductance and noise cannot be reduced as expected.
4 is connected to the inner lead portion 102 of the lead 102.
There is a problem that the position of “a” may be lowered and the surface of the chip 101 may be damaged.

[0009]

As described above, conventionally, although the size of the entire package can be reduced,
It is difficult to reduce inductance and noise, and there is a problem that the chip is damaged during wire bonding.

An object of the present invention is to provide a semiconductor device capable of reducing inductance and noise and reducing chip damage without impairing the overall miniaturization.

[0011]

In order to achieve the above object, a semiconductor device according to the present invention comprises:
A semiconductor chip in which a plurality of electrode pads are disposed along a pair of opposing sides, one end of which is disposed along another pair of opposing sides of the semiconductor chip, and the other end is the electrode A plurality of leads respectively connected to the pads, a first insulating tape attached to a main surface of the semiconductor chip except for a position at which the electrode pads are provided, a conductive thin plate provided on the first insulating tape; And a second insulating tape provided on the conductive thin plate so as to expose at least a part of the conductive thin plate, and bonding each of the leads to a main surface of the semiconductor chip. An adhesive member having a three-layer structure, connecting means for selectively connecting a part of the lead and the electrode pad through the conductive thin plate, and exposing one end of each lead. As to, and a sealing member for sealing the periphery of said semiconductor chip.

According to the semiconductor device of the present invention, the main surface of the semiconductor chip can be shielded almost entirely by the conductive thin plate. Thus, it is possible to easily set the same potential (earth or power) between the semiconductor chip and the leads.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a schematic configuration of a semiconductor package having an SON structure according to a first embodiment of the present invention. FIG. 1A is a plan view showing the inside of the package of the semiconductor package, and FIG. 1B is a sectional view taken along the line AA of FIG. 1A, and FIG. FIG. 3 is a cross-sectional view along the line BB in FIG.

The semiconductor package 10 has a well-known LOC.
For example, each lead 12 of a lead frame is adhered to the main surface of a semiconductor chip 11 via an adhesive tape (adhesive member) 13.

The semiconductor chip 11 has a plurality of electrode pads 11a disposed along a pair of opposing sides. Of the plurality of electrode pads 11a, for example, the electrode pad 11a 'at each end is assigned as a ground or power supply pad.

Each of the leads 12 is formed using a conductive material such as a 42 alloy alloy or a copper alloy, and at least a bonding surface thereof is plated with Ag or the like.

Each of the leads 12 has its inner lead portion (the other end) 12a facing the electrode pad 11a. In addition, each lead 12
Is turned around 90 degrees on the main surface of the semiconductor chip 11, and its outer lead portion (one end) 12b
The sides are arranged along the other pair of opposing sides of the semiconductor chip 11, respectively.

In this case, half of all leads 12
For example, half of the outer lead portions 12b provided along one of a pair of opposite sides of the semiconductor chip 11 and extending from the inner lead portions 12a facing the respective electrode pads 11a. Half of the outer lead portions 12b, which are provided along the other of the sides and extend from the inner lead portions 12a facing the respective electrode pads 11a, respectively, correspond to one of the other pair of opposite sides of the semiconductor chip 11. Are arranged along.

Each of the electrode pads 11a is disposed along one of a pair of opposing sides of the semiconductor chip 11.
And the other half of the outer lead portions 12b extending from the inner lead portions 12a facing each other, and each of the electrode pads 1 similarly arranged along the other of the pair of opposed sides.
The remaining half of the outer lead portions 12b extending from the inner lead portions 12a facing the first chip 1a are arranged along the other of the other pair of opposite sides of the semiconductor chip 11, respectively.

Then, the inner lead portion 12 disposed opposite to the grounding or power supply electrode pad 11a '.
The other inner lead portions 12a except for a are individually electrically connected to the opposing electrode pads 11a via gold wires 14.

Further, an electrode pad 1 for ground or power supply
A gold wire (connection means) 14a is provided between the inner lead portion 1a 'and the inner lead portion 12a disposed opposite thereto.
a, 14b and the conductive thin plate 13b of the adhesive tape 13
, And are electrically connected.

The adhesive tape 13 is provided on the semiconductor chip 1 except at least the position where the electrode pads 11a are provided.
1, a first insulating tape 13a attached to the main surface of
The conductive thin plate 1 provided on the first insulating tape 13a
3b and the conductive thin plate 13b are provided on the conductive thin plate 13b such that at least a part of the conductive thin plate 13b (the connection portion of the gold wires 14a and 14b) is exposed. It has a three-layer structure having a second insulating tape 13c for bonding on top.

In this case, the first and second insulating tapes 1
The 3a and 13c are made of, for example, a thermoplastic resin that can be bonded without curing. The conductive thin plate 13b is made of, for example, the same conductive material as the lead 12 such as a 42 alloy alloy or a copper alloy. I have.

Further, the periphery of the semiconductor chip 11 including the respective leads 12 is sealed with a molding resin 15, and from the upper surface (mounting surface) of the molding resin 15,
Each of the leads 12 is formed such that the side of the outer lead portion 12b formed into a wing shape is planarly exposed.

In the case of the semiconductor package 10 having the SON structure, the outer lead portion 12b of each lead 12 is cut out substantially on the same surface as the side surface without protruding from the outer peripheral surface of the molding resin 15, thereby reducing the size of the entire package. It is planned.

According to the semiconductor package 10 having such a structure, the main surface of the semiconductor chip 11 can be almost entirely electrically and physically shielded by the conductive thin plate 13b while the size of the entire package is reduced.

Moreover, by connecting a ground or a power supply to this, the semiconductor chip 1 can be mounted on a surface (ground plane).
It is possible to easily set the same potential between the lead 1 and the lead 12.

Therefore, the inductance and noise can be reduced, and the gold wire 14 (including the gold wire 14
a) when connecting the inner lead portion 12a of the lead 12
Can be reliably protected even if the position is lowered.

Also, a pad 11a for ground or power supply
′ And the inner lead portion 12a are connected via, for example, a conductive thin plate 13b exposed in a line corresponding to each of the electrode pads 11a. Therefore, it is easy to arrange the ground or power supply pad 11a 'at an arbitrary position, and the degree of freedom in changing the layout of the pad 11a is greatly improved.

FIG. 2 shows an example of a process for forming the above-mentioned adhesive tape 13. For example,
Thick strip-shaped first insulating tape 13a made of thermoplastic resin
A conductive thin plate 13b made of a conductive material such as a 42 alloy alloy or a copper alloy is adhered to the entire surface of the conductive thin plate 13b. The adhesive tape member 21 is formed by bonding the insulating tape 13c.

The adhesive tape member 21 is, for example, formed in a belt shape in advance and wound around a roller 22, and is cut out along a dashed line in the drawing as necessary, whereby the adhesive tape 13 is formed. It has become so.

In this case, the width of the second insulating tape 13c is set to, for example, a part (the gold wire 14) of the conductive thin plate 13b.
a, 14b) are set in such a size that they are exposed in a line shape.
The adhesive tapes 13 having the same structure can be continuously obtained, so that the adhesive tape 13 is excellent in mass productivity and suitable for improving the production rate.

When the conductive thin plate 13b is made of the same 42 alloy as the lead 12, the peeling and the warpage of the package can be suppressed, so that the stress can be improved.

As described above, the main surface of the semiconductor chip can be shielded almost entirely by the conductive thin plate. That is, each lead of the lead frame is bonded to the main surface of the semiconductor chip via an adhesive tape having a conductive thin plate. Thereby, by electrically connecting between the ground or power supply electrode pad and the inner lead portion of the lead arranged opposite thereto via a conductive thin plate of an adhesive tape by a gold wire, respectively.
It is possible to easily set the same potential between the semiconductor chip and the leads. Therefore, in the semiconductor package having the SON structure, the inductance and the noise can be reduced without impairing the miniaturization of the entire package.

Moreover, since the main surface of the semiconductor chip can be protected by the conductive thin plate of the adhesive tape, the position of the inner lead portion of the lead is lowered during bonding, and chip damage such as damage to the chip can be reduced. .

Further, since the pad allocated for the ground or the power supply is connected to the lead through the conductive thin plate, the pad for the ground or the power supply can be easily arranged at an arbitrary position. Thus, the layout of the pads can be freely changed.

In the first embodiment of the present invention, the conductive thin plate 13b in the adhesive tape 13 is used.
The case where the connection portions with the gold wires 14a and 14b are exposed linearly along all the pads 11a has been described as an example. However, the present invention is not limited to this. For example, as shown in FIG. The configuration may be such that the second insulating tape 13c is provided on the conductive thin plate 13b so that only the connection portions 13b 'to the gold wires 14a and 14b are exposed.

The S according to the second embodiment of the present invention
In the case of the semiconductor package having the ON structure, substantially the same effects as those of the semiconductor package having the SON structure according to the above-described first embodiment can be expected, and the ground or power supply pad may be allocated to, for example, other than the electrode pads at the ends. The connection portion 13b 'can be provided according to the position of the electrode pad 11a' to which the ground or the power is allocated.

In the first embodiment described above, the inner lead portion 12a of the lead 12 is
Is connected to the conductive thin plate 13b, but is not limited to this. For example, as shown in FIG. 4, at least the lower surface of the inner lead portion 12a of the lead 12 'connected to the ground or power supply pad 11a' The protruding electrode 31 is formed by metal plating, and the second insulating tape 13c is penetrated by the protruding electrode 31 so that the protruding electrode 31 can be connected to the conductive thin plate 13b.

The S according to the third embodiment of the present invention
In the case of the semiconductor package having the ON structure, the conductive thin plate 13b and the ground or power supply pad 11a 'are connected by the gold wire 14b, so that the electrical connection between the electrode pad 11a' and the lead 12 'is made. Will be connected.

In the third embodiment, substantially the same effects as those of the SON structure semiconductor package according to the first embodiment can be expected, and the SON structure semiconductor package according to the second embodiment can be expected. Similarly,
The ground or power supply pad may be assigned to, for example, an electrode pad other than the end electrode pad. The connection portion 13b 'may be provided according to the position of the electrode pad 11a' to which the ground or power supply is assigned. Protruding electrode 3
1 can also be provided.

Further, in the first embodiment described above,
The main surface of the semiconductor chip 11 is covered almost entirely with the adhesive tape 13 having the conductive thin plate 13b. However, the present invention is not limited to this. For example, as shown in FIG. Opening 13z
It is also possible to provide.

The S according to the fourth embodiment of the present invention
In the case of the semiconductor package having the ON structure, substantially the same effects as those of the semiconductor package having the SON structure according to the first embodiment can be expected, and the main structure of the semiconductor chip 11 corresponding to the opening 13z of the adhesive tape 13 can be expected. For example, it is possible to dispose an electrode pad 11a 'for the ground or the power supply on the surface portion, so that the degree of freedom of the layout of the pad is further increased, and the area is extremely superior.

In the fourth embodiment as well, similarly to the case of the SON structure semiconductor package according to the second and third embodiments, the ground or power supply pad is assigned to, for example, an electrode pad other than the end electrode pad. It is also possible to have the electrode pad 11
The connecting portion 13b 'may be provided according to the position of a', or the protruding electrode 31 may be provided. Of course, various modifications can be made without departing from the scope of the present invention.

[0045]

As described in detail above, according to the present invention, it is possible to provide a semiconductor device capable of reducing inductance and noise and reducing chip damage without impairing the overall miniaturization. .

[Brief description of the drawings]

FIG. 1 shows a SON according to a first embodiment of the present invention.
FIG. 1 is a configuration diagram schematically showing a semiconductor package having a structure.

FIG. 2 is a schematic perspective view similarly illustrating a process for forming an adhesive tape used for manufacturing a semiconductor package.

FIG. 3 is a configuration diagram schematically illustrating a semiconductor package having an SON structure according to a second embodiment of the present invention;

FIG. 4 is a configuration diagram schematically showing a semiconductor package having an SON structure according to a third embodiment of the present invention.

FIG. 5 is a configuration diagram schematically showing a semiconductor package having an SON structure according to a fourth embodiment of the present invention.

FIG. 6 is shown to explain the prior art and its problems;
FIG. 2 is a schematic configuration diagram of a semiconductor package having an SON structure.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Semiconductor package 11 ... Semiconductor chip 11a ... Electrode pad 11a '... Electrode pad (for earth or power supply) 12 ... Lead 12' ... Lead (for earth or power supply) 12a ... Inner lead part 12b ... Outer lead part 13 ... Adhesive tape 13a ... First insulating tape 13b ... Conducting thin plate 13b '... Connecting part 13c ... Second insulating tape 13z ... Opening 14,14a, 14b ... Gold wire 15 ... Mold resin 21 ... Adhesive tape member 22 ... Roller 31 ... Protrusion electrode

Claims (6)

[Claims] 1. A semiconductor chip having a plurality of electrode pads disposed along at least a pair of opposing sides, and one end disposed along another pair of opposing sides of the semiconductor chip. A plurality of leads each having the other end connected to the electrode pad; a first insulating tape attached to a main surface of the semiconductor chip except for a position at which the electrode pad is provided; A conductive thin plate provided on the conductive thin plate, and a second for bonding each of the leads on the main surface of the semiconductor chip, provided on the conductive thin plate such that at least a part of the conductive thin plate is exposed. An adhesive member having a three-layer structure having an insulating tape, and connection means for selectively connecting a part of the lead and the electrode pad via the conductive thin plate of the adhesive member. A sealing member for sealing a periphery of the semiconductor chip so as to expose one end of each of the leads. 2. The lead and the electrode pad, which are connected via the conductive thin plate by the connection means,
2. The semiconductor device according to claim 1, wherein the semiconductor device is for supplying power for operation to the semiconductor chip. 3. The semiconductor device according to claim 2, wherein the lead has a protruding electrode formed on at least a part thereof by metal plating. 4. The semiconductor device according to claim 3, wherein the lead is connected to the conductive thin plate by passing the protruding electrode through the second insulating tape. 5. The semiconductor device according to claim 1, wherein the adhesive member has an opening at a position corresponding to a center of the semiconductor chip. 6. The semiconductor device according to claim 1, wherein a part of the conductive thin plate is exposed from the second insulating tape corresponding to a position of a power supply electrode pad on the semiconductor chip. Semiconductor device.