JPH113994A - Forming method of protrusion structure, forming method of ldd structure, wiring forming method and trench forming method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a new forming method for protrusion structure. SOLUTION: The total pressure of a vacuum chamber is set to 0.3-0.4 Pa, microwave power to 400 W, the bias power of 13.56 MHz to 40 W, and Cl2 is introduced at 30 sccm and O2 at 10 sccm as a condition for etching speed in an etched layer part 42a, which is detached from an etching mask pattern 44, becomes slower than the deposition rate of a reaction product by etching. Microwave plasma etching is executed on the etched layer. Thus, trenches 46 are formed in the etched layer part 42b, which is close to the etching mask pattern 44. Thus, the trenches 46 are filled, and a protrusion structure is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a method for manufacturing a semiconductor device. More specifically, a method of forming a projection structure using plasma etching, and an LDD (lightly
The present invention relates to a method for forming a doped drain structure, a method for forming a wiring, and a method for forming a trench.

[0002]

2. Description of the Related Art Conventionally, in forming an LDD structure, usually, first ion implantation is performed on a semiconductor substrate using a gate electrode as a mask to form a low-concentration impurity diffusion region, and then both sides of the gate electrode are formed. A second ion implantation is performed on the semiconductor substrate using the spacer and the gate electrode as a mask to form a high-concentration impurity diffusion region. The spacer is formed as a residual oxide film on both sides of the gate electrode by temporarily forming an oxide film on the upper surface of the semiconductor substrate including the gate electrode and partially removing the oxide film by reactive ion etching (RIE). Was.

Conventionally, the wiring of a semiconductor device is usually
A resist pattern is formed in a region where a wiring is to be formed on the metal film, and the metal film is dry-etched using the resist pattern as an etching mask, thereby defining and forming the metal film.

[0004]

The above-mentioned conventional LDD
In the structure forming technique, RIE is performed to form spacers (sidewalls) on both sides of the gate electrode. However, according to this method, a damaged layer is formed on the semiconductor substrate by RIE. When the damaged layer is formed, the oxidation does not proceed in a subsequent oxidation step, so that it is difficult to form an oxide film having a designed thickness. Also, if a contact layer is formed in the contact hole reaching the damaged layer, the contact resistance will increase.

Therefore, it has been desired to realize a method for forming an LDD structure without forming a damaged layer.

Further, in the conventional wiring forming method using dry etching, it has been difficult to form wiring using a wiring material such as copper which produces a halogen compound having a high boiling point by dry etching. The reason is that a halogen compound having a high boiling point is not easily removed from the region to be etched. For this reason, it has been difficult to use copper as a wiring material in spite of the advantage that copper has a small electric resistance.

For this reason, it has been desired to realize a wiring forming method capable of forming a wiring using a wiring material that produces a halogen compound having a high boiling point by dry etching.

[0008]

As a result of various studies and experiments, the inventors of the present invention have found that a projection structure such as a spacer and a wiring formed in an LDD structure forming step is formed on an underlying surface. Was formed by forming a trench (groove) and embedding a required material in the trench.

Furthermore, the present inventor has found that, during plasma etching, the etching rate of the portion of the layer to be etched close to the etching mask pattern is higher than the etching rate of the portion of the layer to be etched away from the etching mask pattern. I came up with the idea of using the phenomenon to form trenches.

This phenomenon is considered to be due to the convergence (also referred to as focusing) of the plasma. In the conventional semiconductor manufacturing process, the etching rate becomes non-uniform depending on the portion of the layer to be etched, which is an undesirable phenomenon. And it was.

[0011] The convergence of plasma means that, during etching,
This is a phenomenon in which ions scattered on the side surface of the etching mask pattern (ions bounced off on the side surface) hit the portion of the layer to be etched close to the etching mask pattern, so that more ions are hit than other portions. The reactivity of radicals and the physical assisting action of ions (also referred to as ion assist or ion enhanced etching) contribute to the etching rate in plasma etching. Therefore, in the portion of the layer to be etched close to the etching mask, more ions are applied, so that the ion assist is stronger than in the other portions. Therefore, it is considered that the etching rate is higher than in other portions.

Therefore, according to the method of forming a projection structure of the present invention, (a) a step of forming a layer to be etched on a base, and (b) a step of forming an etching mask pattern on the layer to be etched. (C) a step of forming a trench reaching the base by utilizing convergence of plasma in plasma etching in a portion of the layer to be etched adjacent to the etching mask pattern; and (d) a filling portion for filling the trench in the trench. And forming a projection structure.

As described above, according to the projection structure forming method of the present invention, a trench reaching the base is formed in the portion of the layer to be etched adjacent to the etching mask pattern by utilizing the convergence of plasma in plasma etching.
Further, in order to form a trench using the convergence of plasma, the etching rate in a portion to be etched away from the etching mask pattern is lower than the deposition rate of a reaction product by etching on the portion to be etched. Below, it is preferable to perform plasma etching on the layer to be etched. In this case, the etching does not substantially proceed in the portion of the layer to be etched away from the etching mask because the deposition rate of the reaction product is higher than the etching rate. On the other hand, in the portion of the layer to be etched close to the etching mask, the plasma is converged, so that the etching rate is higher than in other portions. For this reason, the etching proceeds selectively in the portion of the layer to be etched close to the etching mask. As a result, a trench is formed in the portion of the layer to be etched adjacent to the etching mask.

Then, a material having a projecting structure is buried in the trench to form a projecting structure projecting from the underlying surface.

The shape such as the width and the depth of the trench can be controlled by the conditions of the plasma etching. For example, in plasma etching, the higher the ion energy of the plasma incident on the layer to be etched, the higher the straightness of the ions. As a result, the width of the formed trench tends to be narrow and the etching rate of the trench tends to be high. That is, the shape of the trench formed in a certain time tends to be narrow and deep.

On the other hand, the lower the ion energy of the plasma, the lower the straightness of the ions. As a result, the width of the formed trench tends to be wide, and the etching rate of the trench tends to be low. That is, the shape of the trench formed in a certain time tends to be wide and shallow.

In forming the trench, the lower the pressure in the chamber of the plasma etching apparatus, the higher the straightness of ions. As a result, the width of the formed trench tends to be narrow and the etching rate of the trench tends to be high. That is, the shape of the trench formed in a certain time tends to be narrow and deep.

On the other hand, the higher the pressure in the chamber, the lower the straightness of ions. As a result, the width of the formed trench tends to be wide, and the etching rate of the trench tends to be low. That is, the shape of the trench formed in a certain time tends to be wide and shallow.

Therefore, as the ion energy of the plasma incident on the layer to be etched is higher and the pressure of the chamber is lower, the shape of the trench formed in a given time tends to be narrower and deeper. On the other hand, as the ion energy is lower and the pressure in the chamber is higher, the shape of the trench formed in a certain time tends to be wider and shallower.

The width of the trench is not restricted by the resolution of photolithography. Therefore, according to the projection structure forming method of the present invention, for example, a trench having a width smaller than the resolution of the conventional photolithography described in Comparative Example 1 can also be formed. As a result, a projection structure narrower than the resolution of photolithography can be formed.

In carrying out the method of forming a projection structure according to the present invention, preferably, the plasma etching is microwave plasma etching.

In the case of microwave plasma etching,
The plasma density is higher than other plasma etching. Usually, the higher the plasma density, the faster the etching rate. Therefore, if microwave plasma etching is performed, the etching rate can be increased.

In a microwave plasma etching apparatus for performing microwave plasma etching, the acceleration voltage (bias power) of ions can be determined independently of the plasma generation mechanism. Therefore, the ion power determined by the ion acceleration voltage can be controlled independently of the plasma generation mechanism. As a result, the etching conditions for forming the trench can be easily determined.

In the case of microwave plasma etching, the electron temperature is higher than in other types of plasma etching. Generally, when the electron temperature is high, ion scattering is likely to occur. When ion scattering is easily caused, ion convergence is easily caused, so that a trench is easily formed. On the other hand, conventionally, it has been considered that a high electron temperature is not desirable in plasma etching because ion scattering easily occurs.

The method for forming an LDD structure according to the present invention is obtained by applying the method for forming a projection structure according to the present invention to forming an LDD structure. According to the method of forming an LDD structure of the present invention, (a) forming a conductive layer to be etched on a base constituted by a semiconductor substrate and an etching stop layer provided on the semiconductor substrate; (B) forming an etching mask pattern on the layer to be etched, and (c) forming a base layer on the layer to be etched adjacent to the etching mask pattern by utilizing the convergence of plasma in plasma etching. (D) forming a low-concentration impurity diffusion region by implanting impurities into the semiconductor substrate through an etching stop layer portion exposed at the bottom of the trench; and (e) forming a low-concentration impurity diffusion region. Forming a protruding structure with a filling portion filling the trench; (f)
Removing the remaining layer to be etched other than the portion of the layer to be etched immediately below the etching mask pattern; and (g) using the etching mask pattern and the projection structure as a mask to remove impurities from the semiconductor substrate via the etching stop layer. Forming a high-concentration impurity diffusion region having a higher impurity concentration than the low-concentration impurity diffusion region by implantation.

As described above, according to the LDD structure forming method of the present invention, the spacer (sidewall) is formed in the trench.
The spacer is formed by embedding the above material. Therefore, when forming the spacer, no damage layer is formed on the semiconductor substrate.

In carrying out the method for forming an LDD structure according to the present invention, preferably, in step (c), the plasma etching is microwave plasma etching.

Further, the method of forming a wiring according to the present invention is an application of the method of forming a projection structure of the present invention to forming wiring of a semiconductor device. According to the wiring forming method of the present invention, (a) a step of forming a layer to be etched on an insulating lower ground; (b) a step of forming an etching mask pattern on the layer to be etched; A) forming a trench in the portion of the layer to be etched adjacent to the etching mask pattern by using convergence of plasma in plasma etching, reaching a base; (d) removing the etching mask pattern; Forming a protruding structure with a filling portion filling the trench, and (f) removing the remaining etched layer,
Forming a wiring having a projection structure.

As described above, according to the wiring forming method of the present invention, the wiring is formed by embedding the wiring material in the trench. As a result, it is not necessary to perform dry etching in a step after forming a filling film to be a material for wiring. Therefore, it is possible to form a wiring using a wiring material in which a halogen compound having a high boiling point is generated by dry etching, for example, wiring using copper.

According to the wiring forming method of the present invention,
It is also possible to form a thin wiring which has conventionally been difficult to form due to the limitation of the resolution of photolithography.

In carrying out the wiring forming method of the present invention, preferably, in the step (c), the plasma etching is microwave plasma etching.

In carrying out the wiring forming method of the present invention, it is preferable to use a copper film as the filling film.
Conventional wiring materials (for example, AlSiCu
Copper) has a lower electrical resistance than alloys. Therefore, if copper is used, a wiring having a low wiring resistance can be formed.

Further, according to the trench forming method of the present invention, an etching mask pattern is formed on a base, and the convergence of plasma in plasma etching is applied to a portion of a layer to be etched adjacent to the etching mask pattern.
The method is characterized in that a trench is formed.

As described above, according to the trench forming method of the present invention, the trench is formed by using the plasma etching. For this reason, the width of the trench is not restricted by the resolution of photolithography. As a result, a trench narrower than the resolution of photolithography can be formed.

In carrying out the trench forming method of the present invention, preferably, the plasma etching is microwave plasma etching.

[0036]

Embodiments of the present invention will be described below with reference to the drawings. It should be noted that the drawings referred to merely schematically show the sizes, shapes, and arrangements of the components so that these inventions can be understood. Therefore, the present invention is not limited to the illustrated example.
In the drawings, hatching indicating a cross section may be partially omitted.

Next, in order to facilitate understanding of the present invention,
Prior to the description of each embodiment, examples of a conventional method of forming a trench, a method of forming an LDD structure, and a method of forming a wiring will be briefly described as comparative examples.

Comparative Example 1 In Comparative Example 1, FIG.
, An example of a conventional trench forming method will be briefly described. (A) and (B) of FIG. 10 are cross-sectional process drawings for explaining a conventional trench forming method.

In Comparative Example 1, first, a resist pattern 12 is formed on a base 10 for forming a trench.
This resist pattern 12 is formed in a region 14 where a trench is to be formed.
An opening 16 is provided on the upper side (FIG. 10A).

Next, using the resist pattern 12 as an etching mask, a portion of the base 10 exposed in the opening 16 is selectively dry-etched to form a trench (FIG. 10B). ).

When a trench is formed by conventional photolithography and etching, the resolution of photolithography is determined by the wavelength of a light beam (eg, ultraviolet light) used. For this reason, it has been difficult to form a trench having a width smaller than this resolution dimension. For example, in photolithography using i-line, the limit resolution is 0.3 μm, and it has been difficult to form a trench with a width smaller than 0.3 μm.

Comparative Example 2 In Comparative Example 2, FIG.
, An example of a conventional method of forming an LDD structure will be briefly described. (A) to (D) of FIG. 11 are cross-sectional process diagrams for explaining a conventional method of forming an LDD structure.

In Comparative Example 2, first, a gate electrode 22 is formed on a silicon substrate (Si substrate) 20 by photolithography and etching. On this gate electrode 22, a resist pattern 24 remains. Then, using the resist pattern 24 and the gate electrode 22 as a mask, impurities are ion-implanted from above the Si substrate 20 to form a low-concentration impurity diffusion region 26 near the surface of the Si substrate 20 other than immediately below the gate electrode 22. (FIG. 11A).

Next, an oxide film (SiO ₂ film) 28 is formed on the Si substrate 20 on which the low-concentration impurity diffusion regions 26 are formed and on the resist pattern 24 (FIG. 11B).

Next, reactive ion etching (RIE)
The oxide film 28 is removed except for the side wall portion of the gate electrode 22 by using. The remaining oxide film 28a formed on the side wall of the gate electrode 22 is hereinafter referred to as a spacer (or sidewall) 28a (FIG. 11C).

Next, using the resist pattern 24 and the spacer 28a as a mask, impurities are ion-implanted from above the Si substrate 20 to form a high-concentration impurity diffusion region 30. At this time, the low-concentration impurity diffusion region 26 becomes the low-concentration impurity diffusion region 26a remaining only in the portion immediately below the spacer 28a (FIG. 11D).

In the method of forming the LDD structure of Comparative Example 2, when reactive dry etching is performed to form the spacer (sidewall) 28a, Si
There is a problem that a damaged layer (not shown) is formed on the substrate 20.

Comparative Example 3 In Comparative Example 3, FIG.
An example of a conventional wiring forming method will be briefly described with reference to FIG. (A) and (B) of FIG. 12 are cross-sectional process drawings for explaining a conventional wiring forming method.

In Comparative Example 3, first, a metal film 34 is formed on a base 32, and a resist pattern 38 is formed in a wiring formation region 36 on the metal film 34 (FIG. 12A).

Next, dry etching is performed using this resist pattern 38 as an etching mask.
The metal film 34 other than the portion immediately below the resist pattern 38 is removed. As a result, a metal wiring 34a made of the remaining metal film 34a is formed immediately below the resist pattern 38.
(B)).

By the way, in the wiring forming method of Comparative Example 3, when copper is used as the wiring material, for example, a halogen compound having a high boiling point is generated. A halogen compound having a high boiling point tends to remain in a region to be etched. Therefore, in the wiring forming method of Comparative Example 3, it was difficult to form a wiring using a wiring material that generates a halogen compound having a high boiling point by dry etching.

In the wiring forming method of Comparative Example 3, when forming a resist pattern, it is difficult to form a resist pattern narrower than the limit of the resolution of photolithography. For this reason, it has been difficult to form a wiring having a width smaller than the resolution.

[First Embodiment] In a first embodiment, an example of a method of forming a projection structure according to the present invention will be described with reference to FIGS. (A) of FIG.
FIGS. 3A to 3C are first-half cross-sectional process diagrams for describing a method of forming a projection structure according to the first embodiment; FIGS. 2A and 2B are cross-sectional process drawings in the latter half of FIG. 1C.

(A) In the first embodiment, first, an etching target layer 42 of polysilicon having a thickness of 200 nm is formed on a base 40. The underlayer 40 is composed of a silicon substrate 40a and an oxide film (S) having a thickness of 50 nm provided as an etching stop layer on the silicon substrate 40a.
iO ₂ film) 40b (FIG. 1A).

(B) Next, an etching mask pattern 44 is formed on the layer 42 to be etched. This etching mask pattern 44 is made of TEOS (tetr
aethyl orthosilicate) layer 44a and the TEOS layer 4
An amorphous silicon layer (αSi layer) 44b having a thickness of 30 nm is laminated on the substrate 4a (FIG. 1B).

(C) Next, the etching mask pattern 44
A trench 46 reaching the base 40 is formed in the portion 42b of the layer to be etched adjacent to the base 40 by utilizing the convergence of the plasma in the plasma etching.

Here, microwave plasma etching is performed using a microwave plasma etching apparatus (model: M511-A manufactured by Hitachi, Ltd.). In performing microwave plasma etching, the total pressure of the vacuum chamber is set to 0.3 to 0.4 Pa, the microwave power is set to 400 W, and the bias power of 13.56 MHz is set to 40 W. Then, chlorine (Cl ₂ ) and oxygen (O
The mixed gas of ₂ ) is used under the condition that the ratio of O ₂ is 25% or more by volume (that is, O ₂ / (Cl ₂ + O ₂ ) ≧ 25).
%) Into the chamber. Here, Cl ₂ is 30 s
Introduce 10 cm of ccm and O ₂ .

When the microwave plasma etching is performed under the above conditions, the etching rate in the portion 42a to be etched away from the etching mask pattern 44 becomes
The rate of deposition of the reaction product on the to-be-etched layer portion 42a by the etching is lower.

As a result, a trench 46 reaching the base 40 is formed in the portion 42 b of the layer to be etched adjacent to the etching mask pattern 44 by microwave plasma etching.
Is formed (FIG. 1C).

In the first embodiment, the width of the obtained trench 46 is about 0.05 μm to 0.15 μm (50 μm).
nm to 150 nm). Therefore, a trench 46 having a width smaller than the resolution (about 0.3 μm) of photolithography using the conventional i-line was obtained. Further, the width of the trench 46 can be controlled by the conditions of the plasma etching.

(D) Next, a projection structure 52 is formed in the trench 46 with a filling portion 52 filling the trench 46.

(D1) In forming the projection structure 52, in this embodiment, first, the trench 46 is formed.
A filling film 50 is formed inside and above the remaining layer to be etched 48 in which the trench 46 is formed (FIG. 2A).

Here, several hundreds of nanometers are used as the filling film 50.
LPTEOS film (LP) having a thickness of about
TEOS method (TEOS (low press
SiO ₂ film) is formed by formed using Uretetraethyl orthosilicate) method of forming a SiO ₂ film by decomposing). The surface of the filling film 50 has a flat surface for performing the next etch back.

(D2) Next, by removing the portion of the filling film above the remaining layer to be etched 48, the trench 46 is removed.
A projection structure 52 including a filling portion 52 filling the trench 46 is formed therein (FIG. 2B).

Here, the filling film portion on the upper side of the remaining etching target layer 48 is etched back until the remaining etching target layer 48 other than immediately below the etching mask pattern 44 is exposed. For this etch back, it is preferable to use conventionally known suitable conditions and etchants.

In this embodiment, when removing the filling film portion, the etching mask pattern 44 may be left or removed. Further, for example, after forming the trench 46 and before forming the filling film 50, the etching mask pattern 44 may be removed.

In the first embodiment, about 0.05
The filling portion 52 is formed in the trench 46 having a width of about 0.1 μm to about 0.15 μm.
The projection structure 52 having a width of 05 μm to 0.15 μm can be formed.

[Second Embodiment] In a second embodiment, an example of a method of forming an LDD structure according to the present invention will be described with reference to FIGS. (A) of FIG.
(C) is a sectional process view for explaining the method of forming the LDD structure of the second embodiment. Also, FIG.
(C) is a sectional process drawing following (C) of FIG. 3. FIGS. 5A and 5B are cross-sectional process drawings following FIG. 4C.

(A) In the method of forming an LDD structure, first, a conductive etching target layer is formed on a base 58 formed by a semiconductor substrate 54 and an etching stop layer 56 provided on the semiconductor substrate 54. Form 60.

Therefore, in the second embodiment,
First, an element isolation region (not shown) is formed on the main surface of a silicon substrate (Si substrate) 54 as the semiconductor substrate 54 by using the LOCOS method. Then, an oxide film (SiO ₂ film) 56 having a thickness of about 10 nm is formed as an etching stop layer 56 on the main surface of the Si substrate 54 in the active region surrounded by the element isolation region. A part of the oxide film 56 becomes a gate oxide film having an LDD structure.

Then, a polysilicon film 60 having a thickness of about 300 nm is formed as a conductive etching target layer 60 on the oxide film 56 by LPCVD (low pressure CVD) (FIG. 3A). .

(B) Next, an etching mask pattern 62 is formed on the layer 60 to be etched. Here, in forming the etching mask pattern 62, first, LPTEOS (low pressure tetra
ethyl orthosilicate) method (TE by reduced pressure CVD method)
SiO ₂ in a manner) to form a SiO ₂ film by decomposing OS
A film (also referred to as an LPTEOS film) is formed.
A TEOS film (not shown) is formed on an etching mask pattern 62 using a conventionally known photolithography and etching technique (FIG. 3B).

(C) Next, the etching mask pattern 62
A trench 64 reaching the etching stop layer 56 of the underlayer 58 is formed in the portion 60b of the layer to be etched adjacent to the substrate 60 by utilizing the convergence of the plasma in the plasma etching (FIG. 3C).

Here, under the same conditions as the microwave plasma etching in the first embodiment described above,
Microwave plasma etching is performed. As a result, the etching rate at the portion 60a to be etched away from the etching mask pattern 62 becomes lower than the deposition rate of the reaction product by etching on the portion 60a to be etched. Here, the trench 64 having a width of about 0.05 μm to 0.15 μm is formed by microwave plasma etching.

(D) Next, impurities are ion-implanted into the semiconductor substrate 54 through the etching stop layer portion 56a exposed at the bottom 64a of the trench 64, thereby forming a low concentration impurity diffusion region 68 (FIG. 4). (A)).

Here, when the semiconductor substrate 54 is a p-type silicon substrate, as the n-type impurity, for example, phosphorus ions (P.sup. ⁺ ) Are converted to 5.times.1 at an energy of 30 keV.
It is preferable to implant ions at a dose of 0 ¹³ ions / cm ² .

When the semiconductor substrate 54 is an n-type silicon substrate, for example, boron ions (B ⁺ ) are added as p-type impurities at an energy of 20 keV to 5 × 10 5
^{It is} preferable to implant ions at a dose of ¹³ ions / cm ² .

(E) Next, a projection structure 72 is formed in the trench 64 with a filling portion 72 filling the trench 64.

(E1) In forming the projection structure 72, in this embodiment, first, the trench 64 is formed.
In addition, an insulating filling film 70 is formed above the remaining etched layer 66 in which the trench 64 is formed.
(B)).

Here, several hundreds of nanometers are used as the filling film 70.
An LPTEOS film having a thickness of about m to several thousand nm is formed. The surface of the filling film 70 has a flat surface for the next etch back.

(E2) Next, by removing the filling film portion on the upper side of the remaining etching target layer 66, the trench 64 is removed.
Then, a projection structure 72 including a filling portion 72 filling the trench 64 is formed (FIG. 4C).

Here, the filling film portion above the remaining etching target layer 66 is etched back until the remaining etching target layer 66 other than immediately below the etching mask pattern 62 is exposed. For this etch back, it is preferable to use conventionally known suitable conditions and etchants. Although the etching mask pattern 62 is slightly etched during this etch back, the etching mask pattern 62 having a reduced thickness is left here.

Instead of performing the etch back, for example, chemical mechanical polishing (Chemical Mechanical Polishing)
A filling film portion on the remaining etched layer 66 may be removed by using a CMP) method.

(F) Next, the etching mask pattern 62
The remaining etched layer 66 other than the immediately below remaining etched layer portion 66a is removed (FIG. 5A).

Here, the remaining etched layer 66 is removed by dry etching. In dry etching, SiO which is a material of the etching stop layer 56 is used.
_For an etching rate of ₂ , the remaining etched layer 66
The etching condition is such that the etching rate of polysilicon of the above material is 20 times or more.

In this dry etching, since the etching stop layer 56 covering the surface of the silicon substrate 54 remains on the silicon substrate 54, the silicon substrate 54 is not damaged.

The remaining etched layer portion 66a immediately below the etching mask pattern 62 is a portion to be a gate electrode. Further, the projection structure 72 composed of the filling portion 72 adjacent to the remaining etched layer portion 66a is formed by a conventional LDD.
It corresponds to a spacer (sidewall) of the structure.

(G) Next, the etching mask pattern 62
By using the projection structure 72 as a mask and implanting impurities into the semiconductor substrate 54 through the etching stop layer 56, the low-concentration impurity diffusion region 6 is formed.
A high-concentration impurity diffusion region 74 having an impurity concentration higher than 8 is formed (FIG. 5B).

Here, when the semiconductor substrate 54 is a p-type silicon substrate, as the n-type impurity, for example, arsenic ion (As ⁺ ) is applied at an energy of 50 keV and 8 ×
It is preferable to implant ions at a dose of 10 ¹⁵ ions / cm ² .

When the semiconductor substrate 54 is an n-type silicon substrate, for example, BF ₂ ⁺
4 × 10 ¹⁵ ions / cm at an energy of 25 keV
Ion implantation with a dose of ² is recommended.

As described above, according to the method of forming the LDD structure of this embodiment, the spacer is formed by filling the trench formed by using the plasma etching. Therefore, when forming the spacer, it is possible to avoid formation of a damaged layer as in the related art on the semiconductor substrate.

[Third Embodiment] In a third embodiment, an example of a wiring forming method according to the present invention will be described with reference to FIGS. (A) of FIG.
(C) is a first-half cross-sectional process diagram for describing the wiring formation method of the third embodiment; In addition, FIG.
FIG. 7D is a sectional process view of the latter half following FIG.

In the third embodiment, MOS L
An example of forming a metal wiring of copper (Cu) on SI will be described.

(A) According to the wiring forming method of the third embodiment, first, a layer 78 to be etched is formed on an insulating base 76 (FIG. 6A).

Here, the interlayer insulating film (S
iO ₂ ) is used as a base 76. Then, on this base 76, a layer having a thickness of 400 to 500
An m-th polysilicon film 78 is formed using the LPCVD method.

(B) Next, an etching mask pattern 80 is formed on the layer to be etched 78 (FIG. 6B).

Here, an etching mask pattern 8 of SiO ₂ having a thickness of about 300 nm is formed by using the LPTEOS method.
0 is formed. The etching mask pattern 80
Is formed along the wiring, beside the region where the wiring is formed.

(C) Next, the etching mask pattern 80
The trench 82 reaching the base 76 is formed in the portion 78b of the layer to be etched adjacent to the base layer 76 by utilizing the convergence of the plasma in the plasma etching (FIG. 6C).

Here, under the same conditions as in the microwave plasma etching in the first embodiment,
Microwave plasma etching is performed. As a result, the etching rate at the portion 78a to be etched away from the etching mask pattern 80 is lower than the deposition rate of the reaction product by etching on the portion 78a to be etched. Here, the trench 82 having a width of about 0.05 μm to 0.15 μm is formed by microwave plasma etching.

(D) Next, the etching mask pattern 80 is removed by dry etching (FIG. 7A).

Here, the etching mask pattern 80 is removed by dry etching using conventionally known suitable conditions and an etchant.

(E) Next, a stripe-shaped projection structure is formed in the trench with a filling portion filling the trench.

(E1) In this embodiment, first, a conductive filling film 86 is formed on the trench 82 and the remaining etched layer 84 in which the trench 82 has been formed (FIG. 7B). .

Here, the filling film 86 of copper (Cu) is CV
Formed using Method D.

(E2) Next, by removing the portion of the filling film on the remaining layer to be etched 84, a streak-like projection structure 88 is formed in the trench 82 by the filling portion 88 filling the trench 82 (see FIG. 4E). (C of FIG. 7).

Here, the filling film portion on the upper side of the remaining etching target layer 84 is etched back until the remaining etching target layer 84 is exposed. Further, instead of performing the etch back, for example, a CMP method may be used.

(F) Next, by removing the remaining layer 84 to be etched, the wiring 8 having the streak-like projection structure 88 is formed.
8 (FIG. 7D).

Here, the remaining etched layer 84 is removed by dry etching. Then, the time when the base 76 is exposed is defined as the end point of the etching. Further, the remaining etched layer 84 may be removed by wet etching.

The width (thickness) of the wiring 88 is determined by the width of the trench 82. Therefore, in this embodiment, a wiring having a width of about 0.05 to 0.15 μm can be formed.

In this embodiment, an example of forming a copper (Cu) wiring has been described. However, instead of copper (Cu), a tungsten (W) or Al (for example, AlSi,
The metal wiring may be formed of a material such as AlSiCu). Alternatively, the wiring may be formed using a material other than metal.

[Fourth Embodiment] In a fourth embodiment, an example of forming a trench capacitor (trench capacitor) using the trench forming method of the present invention will be described with reference to FIGS. explain. FIGS. 8A and 8B are first-half cross-sectional process diagrams for describing a method of forming a trench capacitor according to the fourth embodiment. FIG.
(A) to (C) are cross-sectional process drawings in the latter half following (B) in FIG. 8.

(A) In the fourth embodiment, first, an etching mask pattern 92 is formed on a semiconductor etching target layer 90 (FIG. 8A).

Here, an etching mask pattern 92 of SiO ₂ having a thickness of about 300 nm is formed on the silicon semiconductor layer 90 by the LPTEOS method.

(B) Next, the etching mask pattern 92
In the portion 90b of the layer to be etched adjacent to the trench 9, the convergence of the plasma in the plasma etching is utilized to form the trench 9b.
4 (FIG. 8B).

Here, under the same conditions as the microwave plasma etching in the first embodiment,
Microwave plasma etching is performed. As a result, the etching rate in the portion 90a to be etched away from the etching mask pattern 92 becomes lower than the deposition rate of the reaction product by etching on the portion 90a to be etched. Then, here, a trench 94 having a width of about 0.05 μm to 0.15 μm is formed by microwave plasma etching.

(C) Next, the etching mask pattern 92
Then, impurities are ion-implanted into the inner surface 94a of the trench 94 and the surface of the layer to be etched 96 around the trench 94 to form a diffusion region 98 (FIG. 9A). 9A to 9C, the vicinity of one of the trenches 94 shown in FIG. 8B is enlarged.

(D) Next, the inner surface 94 of the trench 94
a and remaining etched layer 96 around trench 94
(FIG. 9B).

Here, an SiO ₂ film 100 is formed as the insulating film 100.

(E) Next, the conductive layer 10 is formed on the insulating film 100.
2 (FIG. 9C).

Here, polysilicon is formed as the conductive layer 102 to fill the trench 94.

Therefore, the diffusion region 98 provided with the SiO ₂ film 100 interposed therebetween and the conductive layer 102 constitute a capacitor. Further, the diffusion region 98 and the conductive layer 102
Are connected to switching transistors, respectively, so that they can be used, for example, as trench capacitors for DRAM memory cells.

In each of the embodiments described above, the present invention has been described only with respect to an example in which a specific material is used and formed under specific conditions. However, the present invention can be modified and modified in many ways. For example, in the above-described embodiment, an example in which microwave plasma etching is performed as plasma etching has been described. However, in the present invention, plasma etching need not be limited to this. In particular, if a plasma etching apparatus is capable of controlling the ion energy (bias power) of the plasma incident on the layer to be etched independently of the plasma generation mechanism, the ion energy can be controlled independently of the state of the plasma. It is easy to perform the etching under the condition that the trench is formed. As such a plasma etching apparatus, for example, a helicon wave plasma etching apparatus and an inductively coupled plasma (ICP) etching apparatus are known in addition to the microwave plasma etching apparatus.

In the above-described embodiment, the LPTEOS film is formed as the etching mask pattern. However, the material of the etching mask pattern is not limited to this. For example, an O ₃ TEOS film, a SiO ₂ film or a TEOS film formed by a plasma CVD method, a TEOS film formed by a normal pressure CVD method, or an LPC
An etching mask pattern may be formed by defining a Si ₃ N ₄ film formed by the VD method.

[0124]

According to the projection structure forming method of the present invention, a trench reaching the base is formed in the portion of the layer to be etched adjacent to the etching mask pattern by utilizing the convergence of plasma in plasma etching. In addition, in order to form a trench by utilizing the convergence of plasma, the etching rate in a portion of the layer to be etched away from the etching mask pattern is lower than the deposition rate of a reaction product by etching. On the other hand, plasma etching is preferably performed. In this case, the etching does not substantially proceed in the portion of the layer to be etched away from the etching mask because the deposition rate of the reaction product is higher than the etching rate. On the other hand, in the portion of the layer to be etched close to the etching mask, the plasma is converged, so that the etching rate is higher than in other portions. For this reason, the etching proceeds selectively in the portion of the layer to be etched close to the etching mask. As a result, a trench is formed in the portion of the layer to be etched adjacent to the etching mask.

By embedding a material having a projection structure in the trench, a projection structure projecting from the underlying surface can be formed.

The shape such as the width and depth of the trench can be controlled by the conditions of plasma etching. For example, as the ion energy of the plasma incident on the layer to be etched is higher and the pressure of the chamber is lower, the shape of the trench formed in a certain time tends to be narrower and deeper. On the other hand, ion energy is low,
In addition, as the pressure in the chamber is higher, the shape of the trench formed in a certain time tends to be wider and shallower.

Further, the width of the trench is not restricted by the resolution of photolithography. Therefore, a trench having a width smaller than the resolution of the conventional photolithography can be formed. As a result, a projection structure narrower than the resolution of photolithography can be formed.

According to the LDD structure forming method of the present invention, the spacer is formed by embedding the material of the spacer (sidewall) in the trench. Therefore, when forming the spacer, no damage layer is formed on the semiconductor substrate.

Further, according to the wiring forming method of the present invention,
The wiring is formed by embedding the wiring material in the trench. As a result, it is not necessary to perform dry etching in a step after forming a filling film to be a material for wiring. For this reason, the wiring can be formed using a material in which a halogen compound having a high boiling point is generated by the drain etching, for example, copper.

According to the wiring forming method of the present invention,
Conventionally, it is difficult to form the wiring due to the limitation of the resolution of the photolithography.

Further, according to the trench forming method of the present invention, the trench is formed by using plasma etching. For this reason, the width of the trench is not restricted by the resolution of photolithography. As a result, a trench narrower than the resolution of photolithography can be formed.

Further, in carrying out the invention according to the present application, preferably, when performing plasma etching, microwave plasma etching is performed. In the case of microwave plasma etching, the density of plasma is lower than in other plasma etching. high. Generally, the higher the plasma density, the higher the etching rate. Therefore, the microwave plasma etching can increase the etching rate.

In a microwave plasma etching apparatus for performing microwave plasma etching, the ion acceleration voltage (bias power) can be determined independently of the plasma generation mechanism. Therefore, the ion power determined by the ion acceleration voltage can be controlled independently of the plasma generation mechanism. As a result, the conditions for forming the trench can be easily achieved.

In the case of microwave plasma etching, the electron temperature is higher than in other types of plasma etching. If the electron temperature is high, scattering of ions tends to occur. When the scattering of ions easily occurs, the convergence of ions easily occurs, so that a trench is easily formed.

[Brief description of the drawings]

FIGS. 1A to 1C are first-half cross-sectional process diagrams for describing a method of forming a projection structure according to a first embodiment;

FIGS. 2A and 2B are cross-sectional process views in the latter half following FIG. 1C.

FIGS. 3A to 3C are LDDs according to a second embodiment;
It is sectional process drawing provided for description of the formation method of a structure.

4 (A) to 4 (C) are cross-sectional process drawings following FIG. 3 (C).

FIGS. 5A and 5B are cross-sectional process views following FIG. 4C.

FIGS. 6A to 6C are first-half cross-sectional process diagrams for describing a wiring forming method according to a third embodiment;

7 (A) to 7 (D) are cross-sectional process drawings in the latter half following FIG. 6 (C).

FIGS. 8A and 8B are first-half cross-sectional process diagrams for describing a method of forming a trench capacitor according to a fourth embodiment;

9 (A) to 9 (C) are cross-sectional process drawings in the latter half following FIG. 8 (B).

FIGS. 10A and 10B are cross-sectional process diagrams for explaining a conventional method for forming a trench of Comparative Example 1. FIGS.

FIGS. 11A to 11D show a conventional LDD of Comparative Example 2;
It is sectional process drawing provided for description of the formation method of a structure.

FIGS. 12A and 12B are cross-sectional process diagrams for explaining a conventional wiring forming method of Comparative Example 3. FIGS.

[Explanation of symbols]

10: Underlayer 12: Resist pattern 14: Trench formation planned area 16: Opening 18: Trench 20: Silicon substrate (Si substrate) 22: Gate electrode 24: Resist pattern 26, 26a: Low concentration impurity diffusion region 28: Oxide film ( SiO ₂ film) 30: high concentration impurity diffusion region 32: base 34: metal film 34a: residual metal film, a metal wiring 36: wiring formation region 38: resist pattern 40: base 40a: silicon substrate 40b: oxide film (SiO ₂ 42): Etched layers 42a, 42b: Etched layer portions 44: Etching mask pattern 44a: TEOS layer 44b: Amorphous silicon layer (αSi layer) 46: Trench 48: Remaining etched layer 50: Filled film 52: Filling portion 54: semiconductor substrate, silicon substrate 56: etching stop layer, acid Film (SiO ₂ film) 56a: etching stop layer portion 58: base 60: etched layer 60a, 60b: layer to be etched portion 62: etching mask pattern 64: trenches 64a: bottom 66: remaining etched layer 66a: remaining to be etched Layer portion 68: low-concentration impurity diffusion region 70: filling film 72: filling portion, projection structure 74: high-concentration impurity diffusion region 76: base 78: layers 78a, 78b to be etched: layer portion to be etched 80: etching mask pattern 82: Trench 84: Remaining etched layer 86: Filled film 88: Filled portion, protrusion structure, wiring 90: Etched layer 90a, 90b: Etched layer portion 92: Etching mask pattern 94: Trench 94a: Inner surface 96: Remaining etched Layer 98: diffusion region 100: insulating film 102 Conductive layer

Claims (9)

[Claims] (A) forming a layer to be etched on a base; (b) forming an etching mask pattern on the layer to be etched; and (c) forming a layer adjacent to the etching mask pattern. Forming a trench in the etching layer portion to reach the base by utilizing convergence of plasma in plasma etching; and (d) forming a protruding structure in the trench with a filling portion filling the trench. And a step of forming a projection structure. 2. The method for forming a projection structure according to claim 1, wherein, in the step (c), the plasma etching is microwave plasma etching. 3. A step of forming a conductive layer to be etched on a base formed by a semiconductor substrate and an etching stop layer provided on the semiconductor substrate; and A step of forming an etching mask pattern on the etching layer; and (c) a step of forming a trench reaching the base in a portion of the layer to be etched adjacent to the etching mask pattern by utilizing convergence of plasma in plasma etching. (D) forming a low-concentration impurity diffusion region by injecting impurities into the semiconductor substrate through the etching stop layer portion exposed at the bottom of the trench; Forming a protruding structure with a filling portion that fills the trench; and (f) remaining etching target immediately below the etching mask pattern. (G) implanting impurities into the semiconductor substrate through the etching stop layer using the etching mask pattern and the projection structure as a mask. Forming a high-concentration impurity diffusion region having a higher impurity concentration than the low-concentration impurity diffusion region. 4. The LDD structure forming method according to claim 3, wherein the plasma etching is microwave plasma etching in the step (c).
The method of forming the structure. 5. A step of forming a layer to be etched on an insulating lower ground; a step of forming an etching mask pattern on the layer to be etched; and A step of forming a trench reaching the base by utilizing convergence of plasma in plasma etching in a portion of the layer to be etched adjacently; (d) removing the etching mask pattern; and (e) forming a trench in the trench. Forming a projection structure with a filling portion filling the trench; and (f) removing the remaining layer to be etched,
Forming a wiring having the protrusion structure. 6. The wiring forming method according to claim 5, wherein in the step (c), the plasma etching is microwave plasma etching. 7. The wiring forming method according to claim 5, wherein the filling film is formed using copper. 8. An etching mask pattern is formed on a layer to be etched, and a trench is formed in a portion of the layer to be etched adjacent to the etching mask pattern by utilizing convergence of plasma in plasma etching. Trench forming method. 9. The trench forming method according to claim 8, wherein said plasma etching is microwave plasma etching.