JPH1139044A - Power circuit - Google Patents

Power circuit

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Publication number
JPH1139044A
JPH1139044A JP18954997A JP18954997A JPH1139044A JP H1139044 A JPH1139044 A JP H1139044A JP 18954997 A JP18954997 A JP 18954997A JP 18954997 A JP18954997 A JP 18954997A JP H1139044 A JPH1139044 A JP H1139044A
Authority
JP
Japan
Prior art keywords
power supply
voltage
fet
reverse current
channel mos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18954997A
Other languages
Japanese (ja)
Inventor
Fuminori Sato
文法 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Information Technology Co Ltd
Original Assignee
Hitachi Ltd
Hitachi Information Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Information Technology Co Ltd filed Critical Hitachi Ltd
Priority to JP18954997A priority Critical patent/JPH1139044A/en
Publication of JPH1139044A publication Critical patent/JPH1139044A/en
Pending legal-status Critical Current

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  • Control Of Voltage And Current In General (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)

Abstract

PROBLEM TO BE SOLVED: To flatten the voltage-current characteristics of the DC outputs of plural power circuits operating in parallel and to prevent sudden change of load voltage at the time of a reverse current preventing operation by detecting the potential difference of both terminals in a reverse current preventing element. SOLUTION: P channel MOS-FET 1 is used for the reverse current preventing element inserted into the +-side of a DC stabilization source 2. The voltage of the drain-side of P channel MOS-FET 1 is detected in resistances 3 and 4 and detection voltage Vd is generated. The voltage of the source-side of P channel MOS-FET 1 is detected in resistances 5 and 6 and detection voltage Vs is generated. An error amplifier 13 and resistances 11 and 12 control a transistor 10 with detection voltages Vs and Vd as inputs. Namely, the value of the gate voltage Vg of P channel MOS-FET 1 is changed by a transistor 9, a transistor 10 and resistances 7 and 8, which are the driving circuits of P channel MOS-FET 1. The on-resistance of P channel MOS-FET 1 is controlled.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、並列動作が必要な
電子機器に使用される電源回路に関し、特に、内部部品
のショート等の異常時に異常が発生した電源装置へ電流
が流れ込むのを防止する逆電流防止素子を有する電源回
路に適用して有効な技術に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply circuit used for an electronic device requiring parallel operation, and more particularly, to preventing a current from flowing into a power supply device in which an abnormality has occurred when an abnormality such as a short-circuit of an internal component occurs. The present invention relates to a technology effective when applied to a power supply circuit having a reverse current prevention element.

【0002】[0002]

【従来の技術】従来の電源回路において複数の電源装置
を並列に接続して負荷へ電力を供給している場合に、内
部部品ショート等の何らかの原因によりある電源装置で
出力停止等の異常が発生すると、給電ラインを通して正
常動作中の電源装置から異常が発生した電源装置へ電流
が流れ込み、負荷への安定した電圧の供給を妨げてしま
う。
2. Description of the Related Art In a conventional power supply circuit, when a plurality of power supply devices are connected in parallel to supply power to a load, an abnormality such as an output stop or the like occurs in a certain power supply device due to an internal component short circuit or the like. Then, a current flows from the power supply device that is operating normally to the power supply device in which the abnormality has occurred through the power supply line, thereby preventing a stable supply of voltage to the load.

【0003】そこで、従来の複数の電源装置を並列に接
続して負荷へ電力を供給する電源回路では、正常動作中
の電源装置から異常が発生した電源装置へ電流が流れ込
む逆電流を防ぐ逆電流防止素子を各電源装置の出力部に
設けることが一般的である。
Therefore, in a conventional power supply circuit that supplies power to a load by connecting a plurality of power supply units in parallel, a reverse current for preventing a reverse current from flowing from a power supply unit in normal operation to a power supply unit in which an abnormality has occurred is provided. It is common to provide a prevention element at the output of each power supply.

【0004】以下に、従来の電源回路における逆電流防
止素子の動作について図3及び図4により説明する。
The operation of the reverse current prevention element in the conventional power supply circuit will be described below with reference to FIGS.

【0005】図3は、従来のダイオードを逆電流防止素
子とする電源回路の概要を示す図である。図3に示す様
に従来のダイオードを逆電流防止素子とする電源回路
は、複数の電源装置21を並列に接続し、給電ライン1
6を介して負荷15に電力を供給しており、各々の電源
装置21は、内部部品2aを有する直流安定化電源2
と、逆電流防止素子であるダイオード20とを備えてい
る。
FIG. 3 is a diagram showing an outline of a conventional power supply circuit using a diode as a reverse current prevention element. As shown in FIG. 3, a conventional power supply circuit using a diode as a reverse current prevention element includes a plurality of power supply devices 21 connected in parallel,
6, the power supply 21 supplies power to the load 15 via a DC stabilized power supply 2 having an internal component 2a.
And a diode 20 which is a reverse current prevention element.

【0006】正常動作中の「No.1」の電源装置21
は、直流安定化電源2で出力される出力電圧Voを、逆
電流防止素子のダイオード20を通して負荷15に接続
している給電ライン16へ供給する構成になっている。
The "No. 1" power supply 21 in normal operation
Is configured to supply the output voltage Vo output from the stabilized DC power supply 2 to the power supply line 16 connected to the load 15 through the diode 20 as a reverse current prevention element.

【0007】また、他の電源装置21も同様に、正常動
作中に直流安定化電源2で出力される出力電圧Voを、
逆電流防止素子のダイオード20を通して負荷15に接
続している給電ライン16へ供給している。
[0007] Similarly, the other power supply device 21 also changes the output voltage Vo output from the stabilized DC power supply 2 during normal operation.
The power is supplied to the power supply line 16 connected to the load 15 through a diode 20 serving as a reverse current prevention element.

【0008】ここで、例えば「No.1」の電源装置2
1の直流安定化電源2の内部部品2aがショートする等
の異常が発生すると、直流安定化電源2の出力電圧Vo
が0Vになり、正常動作中の他の電源装置21から給電
ライン16を通して「No.1」の電源装置21へ電流
が流れ込もうとする。
[0008] Here, for example, the power supply device 2 of "No. 1"
1 when the internal component 2a of the DC stabilized power supply 2 is short-circuited, the output voltage Vo of the DC stabilized power supply 2
Becomes 0 V, and the current tries to flow from the other power supply device 21 during normal operation to the power supply device 21 of “No. 1” through the power supply line 16.

【0009】しかし、「No.1」の電源装置21のダ
イオード20が逆方向である為、ダイオード20は、逆
電流防止素子として働き、「No.1」の電源装置21
へ電流が流れる逆電流の発生を防止する。
However, since the diode 20 of the "No. 1" power supply 21 is in the opposite direction, the diode 20 functions as a reverse current prevention element, and the "No. 1" power supply 21
To prevent the generation of a reverse current in which a current flows to

【0010】この様に、ダイオード20は、正常動作中
の他の電源装置21から負荷15への安定した電圧の供
給を妨げてしまうことを防ぐ逆電流防止機能を果たして
いるが、直流安定化電源2から負荷15へ大電流を供給
する場合にはダイオード20での損失が大きくなる。
As described above, the diode 20 has a reverse current preventing function of preventing the supply of a stable voltage from the other power supply device 21 to the load 15 during normal operation. When a large current is supplied from 2 to the load 15, the loss in the diode 20 increases.

【0011】また、逆電流防止素子にダイオード20を
使用した場合には、前段の直流安定化電源2の電圧−電
流特性が平坦であっても、逆電流防止素子のダイオード
特性に影響され、結果として給電ライン16での電圧−
電流特性が悪化する。
When the diode 20 is used as the reverse current prevention element, even if the voltage-current characteristic of the DC stabilized power supply 2 at the preceding stage is flat, the diode characteristic is affected by the diode characteristic of the reverse current prevention element. The voltage on the feed line 16
Current characteristics deteriorate.

【0012】図4は、従来の電源回路のMOS−FET
を逆電流防止素子とする電源回路を示す回路図である。
図4に示す様に従来の電源回路は、逆電流防止素子での
損失低減の為にMOS−FET1(Metal Oxi
de Semiconductor Field Ef
fect Transistor)を使用し、複数の電
源装置34を並列に接続し、給電ライン16を介して負
荷15に電力を供給しており、各々の電源装置34は、
内部部品2aを有する直流安定化電源2と、逆電流防止
素子であるMOS−FET1とを備えている。
FIG. 4 shows a MOS-FET of a conventional power supply circuit.
FIG. 3 is a circuit diagram showing a power supply circuit having a reverse current prevention element.
As shown in FIG. 4, a conventional power supply circuit uses a MOS-FET 1 (Metal Oxi) to reduce loss in a reverse current prevention element.
de Semiconductor Field Ef
A plurality of power supply devices 34 are connected in parallel by using the power supply device 16, and the power supply device 34 supplies power to the load 15 via the power supply line 16.
A DC stabilized power supply 2 having an internal component 2a and a MOS-FET 1 as a reverse current prevention element are provided.

【0013】正常動作中の「No.1」の電源装置34
は、直流安定化電源2で出力される出力電圧Voを抵抗
30及び31と比較増幅器33とで検出し、MOS−F
ET1の駆動回路であるトランジスタ9や抵抗7及び8
を介してMOS−FET1のゲート電圧VgをLowに
することにより逆電流防止素子のMOS−FET1をオ
ンにして、負荷15に接続している給電ライン16へ電
力を供給する構成になっている。
The "No. 1" power supply 34 in normal operation
Detects the output voltage Vo output from the stabilized DC power supply 2 by the resistors 30 and 31 and the comparison amplifier 33,
The transistor 9 and the resistors 7 and 8 which are the driving circuit of the ET1
, The gate voltage Vg of the MOS-FET 1 is set to Low to turn on the MOS-FET 1 as a reverse current prevention element, and power is supplied to the power supply line 16 connected to the load 15.

【0014】また、他の電源装置34も同様にして、逆
電流防止素子のMOS−FET1をオンにして、直流安
定化電源2で出力される出力電圧Voを、負荷15に接
続している給電ライン16へ供給している。
Similarly, the other power supply unit 34 turns on the MOS-FET 1 as a reverse current prevention element, and supplies the output voltage Vo output from the stabilized DC power supply 2 to the power supply connected to the load 15. It supplies to line 16.

【0015】ここで「No.1」の電源装置34の直流
安定化電源2の内部部品2aがショートすると、出力電
圧Voが低下し始め、やがて0Vになるが、出力電圧V
oが低下していることを抵抗30及び31と比較増幅器
33とで検出すると、MOS−FET1の駆動回路であ
るトランジスタ9や抵抗7及び8を介してMOS−FE
Tゲート電圧VgをHighにし、逆電流防止素子のM
OS−FET1をオフにする。
When the internal component 2a of the stabilized DC power supply 2 of the power supply unit 34 of "No. 1" is short-circuited, the output voltage Vo starts to decrease and eventually becomes 0V.
is detected by the resistors 30 and 31 and the comparison amplifier 33, the MOS-FE is connected via the transistor 9 and the resistors 7 and 8 which are the driving circuit of the MOS-FET 1.
The T gate voltage Vg is set to High, and the M
OS-FET1 is turned off.

【0016】この様に、MOS−FET1がオフとなる
ことにより電源装置34へ電流が流れ込む逆電流の発生
が防止され、負荷15へは正常動作中の他の電源装置2
1から安定した電圧の供給が行われる。
In this way, the turning off of the MOS-FET 1 prevents the occurrence of a reverse current in which a current flows into the power supply unit 34, and supplies the load 15 with another power supply unit 2 which is operating normally.
The supply of a stable voltage from 1 is performed.

【0017】[0017]

【発明が解決しようとする課題】従来の電源回路におい
て、逆電流防止素子にダイオードを使用した場合には、
ダイオードでの損失が大きいという問題がある。
In a conventional power supply circuit, when a diode is used as a reverse current prevention element,
There is a problem that the loss in the diode is large.

【0018】また、前段の直流安定化電源出力の電圧−
電流特性が平坦であっても逆電流防止素子のダイオード
特性に影響され結果として給電ラインでの電圧−電流特
性が悪化するという問題がある。
Further, the voltage of the output of the DC stabilized power supply of the preceding stage-
Even if the current characteristics are flat, there is a problem that the voltage-current characteristics in the power supply line deteriorate as a result of being affected by the diode characteristics of the reverse current prevention element.

【0019】更に、逆電流防止素子にMOS−FETを
使用した場合には、オン状態のMOS−FETは一定の
抵抗値である為、電流が増えると電圧降下が増し、結果
として給電ラインでの電圧−電流特性が悪化するという
問題がある。
Further, when a MOS-FET is used as the reverse current prevention element, the MOS-FET in the ON state has a constant resistance value, so that the voltage increases as the current increases, and as a result, the voltage in the power supply line increases. There is a problem that the voltage-current characteristics deteriorate.

【0020】また、逆電流防止素子にMOS−FETを
使用した場合には、電源装置で異常が発生してからMO
S−FETをオフにする出力電圧を検出するまでの切換
の時間に電源装置へ電流が流れ込む為、直流電圧低下が
発生し、結果として給電ラインの電圧急変を招くという
問題がある。
When a MOS-FET is used as the reverse current preventing element, the MO
Since current flows into the power supply during the switching time until the output voltage for turning off the S-FET is detected, a DC voltage drop occurs, resulting in a sudden change in the voltage of the power supply line.

【0021】本発明の目的は、上記問題を解決し、複数
台で並列動作する電源回路の直流出力の電圧−電流特性
を平坦にすると共に、逆電流防止動作時の負荷電圧急変
を防止することが可能な技術を提供することにある。
An object of the present invention is to solve the above problems, to flatten the voltage-current characteristics of the DC output of a power supply circuit operated in parallel by a plurality of units, and to prevent a sudden change in load voltage during a reverse current prevention operation. Is to provide a possible technology.

【0022】[0022]

【課題を解決するための手段】本発明は、並列に接続さ
れた複数の電源装置により負荷に電力を供給する電源回
路において、逆電流防止素子の両端の電位差を検出して
逆電流防止素子の動作を制御するものである。
SUMMARY OF THE INVENTION The present invention relates to a power supply circuit for supplying power to a load by a plurality of power supply devices connected in parallel. It controls the operation.

【0023】本発明の電源回路の駆動回路は、逆電流防
止素子の両端の電位差を検出し、直流安定化電源側から
負荷側へ電流が流れる様に前記電位差が生じている場合
には、逆電流防止素子をオン状態にして正常動作を行わ
せる。
The drive circuit of the power supply circuit according to the present invention detects the potential difference between both ends of the reverse current prevention element, and when the potential difference is generated so that the current flows from the DC stabilized power supply side to the load side, the reverse direction is detected. The normal operation is performed by turning on the current preventing element.

【0024】ここで、直流安定化電源中の内部部品がシ
ョートする等の異常が発生すると、他の正常動作中の電
源装置から異常が発生した電源装置に電流が流れ込もう
とする。
Here, when an abnormality such as a short-circuit of an internal component in the stabilized DC power supply occurs, current tries to flow from another power supply apparatus in normal operation to the power supply apparatus in which the abnormality has occurred.

【0025】すると、逆電流防止素子の両端の電位差
は、「0」または負荷側から直流安定化電源側へ電流が
流れる方向に変化するので、駆動回路は、前記電位差の
変化を検出し、逆電流防止素子をオフ状態にして逆電流
防止動作を行わせる。
Then, the potential difference between both ends of the reverse current preventing element changes to “0” or a direction in which current flows from the load side to the DC stabilized power supply side. Therefore, the drive circuit detects the change in the potential difference and performs the reverse operation. The current prevention element is turned off to perform a reverse current prevention operation.

【0026】また、本発明の電源回路が正常動作中に、
負荷により直流出力電流が変化した場合には、駆動回路
は、逆電流防止素子の両端の電位差の変化を検出し、前
記検出した変化に応じて逆電流防止素子のオン抵抗を変
化させて、逆電流防止素子の両端の電圧降下を一定に保
つ。これにより、逆電流防止素子の電圧−電流特性が平
坦となる。
Also, during normal operation of the power supply circuit of the present invention,
When the DC output current changes due to the load, the drive circuit detects a change in the potential difference between both ends of the reverse current prevention element, and changes the on-resistance of the reverse current prevention element in accordance with the detected change, and The voltage drop across the current prevention element is kept constant. Thereby, the voltage-current characteristics of the reverse current prevention element become flat.

【0027】以上の様に、本発明の電源回路によれば、
逆電流防止素子の両端の電位差を検出して、その動作を
制御するので、複数台で並列動作する電源回路の直流出
力の電圧−電流特性を平坦にすると共に、逆電流防止動
作時の負荷電圧急変を防止することが可能である。
As described above, according to the power supply circuit of the present invention,
Since the operation is controlled by detecting the potential difference between both ends of the reverse current prevention element, the voltage-current characteristics of the DC output of the power supply circuit operating in parallel with a plurality of units are flattened, and the load voltage during the reverse current prevention operation is reduced. It is possible to prevent sudden changes.

【0028】[0028]

【発明の実施の形態】以下に、複数の電源装置を並列に
接続して負荷へ電力を供給し、特定の電源装置で出力停
止等の異常が発生したときに逆電流の発生を防止する一
実施形態の電源回路について説明する。
BEST MODE FOR CARRYING OUT THE INVENTION A plurality of power supplies are connected in parallel to supply power to a load so as to prevent the occurrence of a reverse current when an abnormality such as an output stop occurs in a specific power supply. A power supply circuit according to the embodiment will be described.

【0029】図1は、本実施形態の電源回路の概略構成
を示す図である。図1に示す様に本実施形態の電源回路
は、複数の電源装置14を並列に接続し、給電ライン1
6を介して負荷15に電力を供給しており、各々の電源
装置14は、内部部品2aを有する直流安定化電源2
と、逆電流防止素子であるPチャネルMOS−FET1
とを備えている。
FIG. 1 is a diagram showing a schematic configuration of the power supply circuit of the present embodiment. As shown in FIG. 1, the power supply circuit according to the present embodiment includes a plurality of power supply devices 14 connected in parallel,
6, the power supply 14 supplies power to the load 15 via a DC stabilized power supply 2 having an internal component 2a.
And a P-channel MOS-FET 1 serving as a reverse current prevention element
And

【0030】本実施形態の電源回路では、直流安定化電
源2の+側に挿入する逆電流防止素子にPチャネルMO
S−FET1を用いてPチャネルMOS−FET1のド
レイン側の電圧を抵抗3及び4で検出して検出電圧Vd
を生成する。
In the power supply circuit according to the present embodiment, the P-channel MO
Using the S-FET1, the voltage on the drain side of the P-channel MOS-FET1 is detected by the resistors 3 and 4, and the detected voltage Vd
Generate

【0031】また、PチャネルMOS−FET1のソー
ス側の電圧を抵抗5及び6で検出して検出電圧Vsを生
成し、誤差増幅器13、抵抗11及び12により、検出
電圧Vs及びVdを入力としてトランジスタ10の制御
を行う。
The voltage on the source side of the P-channel MOS-FET 1 is detected by the resistors 5 and 6 to generate a detection voltage Vs, and the error amplifier 13 and the resistors 11 and 12 receive the detection voltages Vs and Vd as input transistors. 10 is performed.

【0032】すなわち、PチャネルMOS−FET1の
駆動回路であるトランジスタ9、トランジスタ10、抵
抗7及び8により、PチャネルMOS−FET1のゲー
ト電圧Vgの値を変化させ、PチャネルMOS−FET
1のオン抵抗Ronを制御する。
That is, the value of the gate voltage Vg of the P-channel MOS-FET 1 is changed by the transistor 9, the transistor 10, and the resistors 7 and 8 which are the driving circuit of the P-channel MOS-FET 1.
1 is controlled.

【0033】以下に、本実施形態の電源回路の第1の段
階として、電源装置14が正常動作中のときの逆電流防
止素子であるPチャネルMOS−FET1の動作につい
て説明する。
Hereinafter, as the first stage of the power supply circuit of the present embodiment, the operation of the P-channel MOS-FET 1 as the reverse current prevention element when the power supply device 14 is operating normally will be described.

【0034】第1の段階として電源装置14が正常動作
中の場合には、直流安定化電源2が動作開始の時、直流
出力電圧Voがボディーダイオード1aを通して負荷1
5へ供給される。
As a first step, when the power supply device 14 is operating normally, when the stabilized DC power supply 2 starts operating, the DC output voltage Vo passes through the load 1 through the body diode 1a.
5.

【0035】電源装置14は、正常に動作しているの
で、数1に示す様に検出電圧Vdは検出電圧Vsよりも
大きくなる。
Since the power supply 14 is operating normally, the detection voltage Vd becomes higher than the detection voltage Vs as shown in Expression 1.

【0036】[0036]

【数1】Vd>Vs その際、PチャネルMOS−FET1の両端の電圧降下
は、検出電圧Vdと検出電圧Vsとの差で得ることがで
きる為、誤差増幅器出力値Vaは、数2に示す様にな
り、トランジスタ10を駆動し、ゲート電圧Vgを下
げ、PチャネルMOS−FET1をオンにする。
Vd> Vs At this time, the voltage drop across the P-channel MOS-FET 1 can be obtained by the difference between the detection voltage Vd and the detection voltage Vs. As a result, the transistor 10 is driven, the gate voltage Vg is reduced, and the P-channel MOS-FET 1 is turned on.

【0037】[0037]

【数2】Va=A(Vd−Vs) その時のPチャネルMOS−FET1での電圧降下Vx
は、数3に示す様になる。
## EQU2 ## Va = A (Vd-Vs) The voltage drop Vx at the P-channel MOS-FET 1 at that time
Becomes as shown in Expression 3.

【0038】[0038]

【数3】Vx=Ron・Io 以下に、本実施形態の電源回路の第2の段階として、電
源装置14が正常動作中のときに負荷15により直流出
力電流Ioが変化した場合のPチャネルMOS−FET
1の動作について説明する。
Vx = Ron · Io As a second stage of the power supply circuit according to the present embodiment, a P-channel MOS when the DC output current Io changes due to the load 15 when the power supply device 14 is operating normally. -FET
1 will be described.

【0039】第2の段階として、電源装置14が正常動
作中に負荷15により直流出力電流IoがΔIoだけ変
化した場合には、数3は以下の数4の様になり、Pチャ
ネルMOS−FET1の両端の電圧降下が変化する。
In the second stage, when the DC output current Io changes by ΔIo due to the load 15 during the normal operation of the power supply device 14, the equation 3 becomes the following equation 4, and the P-channel MOS-FET 1 The voltage drop between both ends changes.

【0040】[0040]

【数4】(Vx+ΔVx)=Ron・(Io+ΔIo) また、検出電圧Vsも変化する為、数2は数5の様にな
り、トランジスタ10ベース電圧が変化する。
(Vx + ΔVx) = Ron · (Io + ΔIo) Further, since the detection voltage Vs also changes, Expression 2 becomes Expression 5 and the base voltage of the transistor 10 changes.

【0041】[0041]

【数5】Va+ΔVa=A(Vd−(Vs+ΔVs)) この為、ゲート電圧Vg及びオン抵抗Ronが変化し、
数4は数6となり、結果的にPチャネルMOS−FET
1の両端の電圧降下Vxが一定に保たれる様に動作す
る。これにより、給電ライン16での電圧−電流特性が
平坦になる。
Va + ΔVa = A (Vd− (Vs + ΔVs)) Therefore, the gate voltage Vg and the on-resistance Ron change.
Equation 4 becomes Equation 6, resulting in a P-channel MOS-FET
1 operates such that the voltage drop Vx across the terminals 1 is kept constant. Thereby, the voltage-current characteristics in the power supply line 16 become flat.

【0042】[0042]

【数6】 Vx=(Ron+ΔRon)・(Io+ΔIo) 図2は、本実施形態の電圧−電流特性の概要を示す図で
ある。図2に示す様に本実施形態の電圧−電流特性は、
直流電源出力、従来の電源回路で逆電流防止素子として
ダイオード20を用いた場合、従来の電源回路でMOS
−FET1を用いた場合及び本実施形態の電源回路でP
チャネルMOS−FET1を用いた場合の電圧−電流特
性を表している。
## EQU00006 ## Vx = (Ron + .DELTA.Ron). (Io + .DELTA.Io) FIG. 2 is a diagram showing an outline of the voltage-current characteristics of the present embodiment. As shown in FIG. 2, the voltage-current characteristics of this embodiment are as follows.
When a diode 20 is used as a reverse current prevention element in a DC power supply output and a conventional power supply circuit, a MOS
-When the FET 1 is used and in the power supply circuit of the present embodiment, P
This shows voltage-current characteristics when the channel MOS-FET 1 is used.

【0043】本実施形態の電源回路では、前記の様に結
果的にPチャネルMOS−FET1の両端の電圧降下V
xが一定に保たれる様に動作する為、給電ライン16で
の電圧−電流特性が図2の電源出力値14xに示す様に
平坦になる。
In the power supply circuit of this embodiment, as described above, as a result, the voltage drop V across the P-channel MOS-FET 1
Since the operation is performed so that x is kept constant, the voltage-current characteristic in the power supply line 16 becomes flat as shown by the power supply output value 14x in FIG.

【0044】一方、図3の様に従来の電源回路で逆電流
防止素子にダイオード20を使用した場合には、損失が
大きいばかりではなく、前段の直流安定化電源2の出力
の電圧−電流特性が図2の直流安定化電源出力値2xに
示す様に平坦であっても、逆電流防止素子のダイオード
特性に影響され、結果として給電ライン16での電圧−
電流特性が図2の電源出力値21xに示す様に悪化す
る。
On the other hand, when the diode 20 is used as the reverse current prevention element in the conventional power supply circuit as shown in FIG. 3, not only the loss is large but also the voltage-current characteristic of the output of the DC stabilized power supply 2 in the preceding stage. Is flat as shown by the DC stabilized power supply output value 2x in FIG. 2, it is affected by the diode characteristics of the reverse current prevention element, and as a result, the voltage −
The current characteristics deteriorate as shown by the power supply output value 21x in FIG.

【0045】また、図4の様に従来の電源回路で逆電流
防止素子にMOS−FET1を使用した場合には、オン
状態のMOS−FET1は一定の抵抗値である為、電流
が増えると電圧降下が増し、結果として給電ライン16
での電圧−電流特性が図2の電源出力値34xに示す様
に悪化する。
When the MOS-FET 1 is used as the reverse current prevention element in the conventional power supply circuit as shown in FIG. 4, the MOS-FET 1 in the ON state has a constant resistance value. The descent increases, and as a result, the feed line 16
The voltage-current characteristics at the point (1) deteriorate as shown by the power supply output value 34x in FIG.

【0046】以下に、本実施形態の電源回路の第3の段
階として、電源装置14の直流安定化電源2の内部部品
2aがショートし、電源装置14が異常となった場合の
PチャネルMOS−FET1の動作について説明する。
Hereinafter, as a third stage of the power supply circuit according to the present embodiment, a P-channel MOS-type power supply in the case where the internal component 2a of the DC stabilized power supply 2 of the power supply 14 short-circuits and the power supply 14 becomes abnormal will be described. The operation of the FET 1 will be described.

【0047】第3の段階で「No.1」の電源装置14
の直流安定化電源2の内部部品2aがショートする等の
異常が発生して出力電圧Voが0Vになると、正常動作
中の他の電源装置14から給電ライン16を通して「N
o.1」の電源装置14へ電流が流れ込もうとするが、
その時は既に「No.1」の電源装置14の直流出力電
流Ioが流れていない為、PチャネルMOS−FET1
の両端の電圧降下が発生せず、数7若しくは数8の状態
となる。
In the third stage, the “No. 1” power supply device 14
When the output voltage Vo becomes 0 V due to an abnormality such as a short circuit of the internal component 2a of the DC stabilized power supply 2 of FIG.
o. The current tries to flow into the power supply 14 of "1",
At that time, since the DC output current Io of the power supply device No. 1 has not already flowed, the P-channel MOS-FET 1
No voltage drop occurs at both ends, and the state of Equation 7 or 8 is obtained.

【0048】[0048]

【数7】Vd=VsVd = Vs

【0049】[0049]

【数8】Vd<Vs この為、数1の誤差増幅器出力値Vaは、「0」若しく
は「−」の値となるのでトランジスタ10を駆動でき
ず、ゲート電圧Vgがソース電圧と同電位になり、Pチ
ャネルMOS−FET1がオフになって、切換時間が発
生することなく、逆電流防止動作が行われる。
Vd <Vs Because of this, the error amplifier output value Va of Expression 1 becomes “0” or “−”, so that the transistor 10 cannot be driven, and the gate voltage Vg becomes the same potential as the source voltage. , The P-channel MOS-FET 1 is turned off, and the reverse current preventing operation is performed without any switching time.

【0050】尚、本実施形態の電源回路では、逆電流防
止素子にPチャネルMOS−FET1を使用した例で説
明したが、NチャネルMOS−FETを使用して直流安
定化電源2の−側に挿入しても同様であり、逆電流防止
素子にバイポーラトランジスタ等のリニアに制御できる
素子ならば種類を問わない。
In the power supply circuit of the present embodiment, an example has been described in which a P-channel MOS-FET 1 is used as a reverse current prevention element. The same applies even if the element is inserted, and any element can be used as the reverse current prevention element as long as the element can be controlled linearly such as a bipolar transistor.

【0051】また、電流容量が大きいときに使用する場
合は逆電流防止素子を複数個並列接続するとより効果を
得られる。
Further, when the device is used when the current capacity is large, more effects can be obtained by connecting a plurality of reverse current preventing elements in parallel.

【0052】更に、本実施形態の電源回路を、集積回路
(ハイブリットIC、モノリシックIC)化しても良
く、また、直流電源として交流電源を整流して得た直流
を用いても良い。
Further, the power supply circuit of the present embodiment may be formed as an integrated circuit (hybrid IC, monolithic IC), or a DC obtained by rectifying an AC power supply may be used as a DC power supply.

【0053】以上説明した様に、本実施形態の電源回路
によれば、逆電流防止素子の両端の電位差を検出して、
その動作を制御するので、複数台で並列動作する電源回
路の直流出力の電圧−電流特性を平坦にすると共に、逆
電流防止動作時の負荷電圧急変を防止することが可能で
ある。
As described above, according to the power supply circuit of the present embodiment, the potential difference between both ends of the reverse current prevention element is detected,
Since the operation is controlled, it is possible to flatten the voltage-current characteristics of the DC output of the power supply circuits operating in parallel by a plurality of units and to prevent a sudden change in the load voltage during the reverse current prevention operation.

【0054】[0054]

【発明の効果】本発明によれば、逆電流防止素子の両端
の電位差を検出して、その動作を制御するので、複数台
で並列動作する電源回路の直流出力の電圧−電流特性を
平坦にすると共に、逆電流防止動作時の負荷電圧急変を
防止することが可能である。
According to the present invention, since the potential difference between both ends of the reverse current prevention element is detected and its operation is controlled, the voltage-current characteristic of the DC output of the power supply circuits operating in parallel by a plurality of units is made flat. In addition, it is possible to prevent a sudden change in the load voltage during the reverse current prevention operation.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本実施形態の電源回路の概略構成を示す図であ
る。
FIG. 1 is a diagram illustrating a schematic configuration of a power supply circuit according to an embodiment.

【図2】本実施形態の電圧−電流特性の概要を示す図で
ある。
FIG. 2 is a diagram showing an outline of a voltage-current characteristic of the present embodiment.

【図3】従来のダイオードを逆電流防止素子とする電源
回路の概要を示す図である。
FIG. 3 is a diagram showing an outline of a conventional power supply circuit using a diode as a reverse current prevention element.

【図4】従来の電源回路のMOS−FETを逆電流防止
素子とする電源回路を示す回路図である。
FIG. 4 is a circuit diagram showing a power supply circuit using a MOS-FET of a conventional power supply circuit as a reverse current prevention element.

【符号の説明】[Explanation of symbols]

1a…ボディーダイオード、3〜6…抵抗、10…トラ
ンジスタ、11及び12…抵抗、13…誤差増幅器、1
4…電源装置、2…直流安定化電源、2a…内部部品、
15…負荷、16…給電ライン、20…ダイオード、2
1…電源装置、1…MOS−FET、7及び8…抵抗、
9…トランジスタ、30及び31…抵抗、33…比較増
幅器、34…電源装置。
1a: body diode, 3-6: resistor, 10: transistor, 11 and 12: resistor, 13: error amplifier, 1
4 power supply device, 2 DC stabilized power supply, 2a internal components,
15 load, 16 feed line, 20 diode, 2
DESCRIPTION OF SYMBOLS 1 ... Power supply device, 1 ... MOS-FET, 7 and 8 ... Resistance,
9 ... transistors, 30 and 31 ... resistors, 33 ... comparative amplifiers, 34 ... power supply devices.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 並列に接続された複数の電源装置により
電力を供給する電源回路において、 複数の電源装置の内の特定の装置で異常が発生した場合
に正常動作中の電源装置から異常が発生した電源装置に
電流が流れる逆電流の発生を防止する逆電流防止素子
と、前記逆電流防止素子の両端の電位差を検出して前記
逆電流防止素子の動作を制御する駆動回路とを備えるこ
とを特徴とする電源回路。
In a power supply circuit for supplying power from a plurality of power supply units connected in parallel, when an abnormality occurs in a specific one of the plurality of power supply units, an abnormality occurs from a power supply unit that is operating normally. A reverse current prevention element for preventing generation of a reverse current in which a current flows through the power supply device, and a drive circuit for detecting the potential difference between both ends of the reverse current prevention element and controlling the operation of the reverse current prevention element. Characteristic power supply circuit.
JP18954997A 1997-07-15 1997-07-15 Power circuit Pending JPH1139044A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18954997A JPH1139044A (en) 1997-07-15 1997-07-15 Power circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18954997A JPH1139044A (en) 1997-07-15 1997-07-15 Power circuit

Publications (1)

Publication Number Publication Date
JPH1139044A true JPH1139044A (en) 1999-02-12

Family

ID=16243187

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18954997A Pending JPH1139044A (en) 1997-07-15 1997-07-15 Power circuit

Country Status (1)

Country Link
JP (1) JPH1139044A (en)

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