JPH11355713A - Data processing unit, data processing method and served medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To record video data of pluralities of systems. SOLUTION: An extract section 25 extracts a flag to identify the NTSC or PAL system of a CIP(common isochronous packet) header and frame pulse data from a packet. A synchronization control section 22 sets a system (NTSC or PAL) of a signal to be outputted, confirms an identification flag of a system fed from the extract section 25 to control a software PLL processing section 21 and a data processing section 24. The software PLL processing section 21 generates a frame pulse synchronizing with frame pulse data supplied from the extract section 25. A frame pulse count processing section 23 discriminates whether or not the frame pulse from the software PLL processing section 21 corresponds to the setting by a synchronization control section 22 and sets a count of the counter. A data processing section 24 instructs a recording reproducing section 19 to record or stop data depending on the count.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a data processing device,
More particularly, the present invention relates to a data processing device, a data processing method, and a providing medium that can reliably process a plurality of types of video data transmitted via a bus.

[0002]

2. Description of the Related Art FIG. 9 is a diagram showing a connection example of devices connected by an IEEE1394 serial bus. Digital VTR1 is I
EEE1394 serial bus 3 with video camera integrated digital V
Connected to TR2, video data of a predetermined system is supplied. There are a plurality of video data formats, such as the 525/60 system data format defined in ITU-R Recommendation 601 represented by the so-called NTSC (National Television System Committee) format, and PAL (Phase Alternating by Line color tele).
vision system) as defined in ITU-R Recommendation 601
There are 625/50 system data systems, etc. Digital VTR
The data system in which 1 can be recorded is determined by the circuit configuration of the digital VTR 1, and is usually limited to one of the 525/60 system data system and the 625/50 system data system.

[0003]

[Problems to be Solved by the Invention] Conventional digital VTR 1
Is configured to record only video data of one of the 525/60 system and the 625/50 system, and cannot record video data of another system different from that.

SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and has as its object to switch the synchronization timing in accordance with the type of video data to be input and to enable recording of video data of a plurality of types. And

[0005]

According to a first aspect of the present invention, there is provided a data processing apparatus for generating a frame pulse synchronized with a frame pulse input from a bus, and a generating means based on a set signal system. Changing means for changing the synchronization timing of the input frame pulse, counting means for counting the frame pulse generated by the generating means,
An instruction unit for instructing another function of the data processing apparatus to perform a predetermined process based on the value counted by the counting unit is provided.

According to a second aspect of the present invention, there is provided a data processing method comprising: a generating step of generating a frame pulse synchronized with a frame pulse input from a bus; and a frame pulse input in the generating step based on a set signal system. A changing step of changing the synchronization timing, a counting step of counting the frame pulses generated by the generating step, and an instruction step of instructing another function of the data processing device to perform a predetermined process based on the value counted by the counting step. And characterized in that:

According to a third aspect of the present invention, there is provided a providing medium, comprising: a generating step of generating a frame pulse synchronized with a frame pulse input from a bus to a data processing device; A changing step of changing the synchronization timing of the generated frame pulse, a counting step of counting the frame pulse generated by the generating step, and a predetermined process for other functions of the data processing device based on the value counted by the counting step. A computer-readable program for executing a process including an instruction step of instructing is provided.

In the data processing apparatus, the data processing method, and the providing medium according to the present invention, the synchronizing timing of the frame pulse is changed according to the signal system to generate a frame pulse synchronized with the frame pulse input from the bus.
The frame pulse is counted, and a predetermined process is executed based on the count value.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below. In order to clarify the correspondence between each means of the invention described in the claims and the following embodiments, each means is described. When the features of the present invention are described by adding the corresponding embodiment (however, an example) in parentheses after the parentheses, the result is as follows. However, of course, this description does not mean that each means is limited to those described.

That is, the data processing device according to the first aspect is provided with a generating means (for example, the software PLL processing unit 21 in FIG. 2) for generating a frame pulse synchronized with the frame pulse input from the bus. Changing means (for example, the synchronization control unit 2 in FIG. 2) for changing the synchronization timing of the input frame pulse of the generation means based on the signal system;
2), counting means for counting the frame pulses generated by the generating means (for example, frame pulse count processing unit 23 in FIG. 2), and a predetermined function for other functions of the data processing device based on the value counted by the counting means. (For example, the data processing unit 24 in FIG. 2).

Next, a digital VTR 1 to which the present invention is applied will be described. The basic connection state is the same as that shown in FIG.

FIG. 1 is a hardware configuration diagram of the digital VTR 1. An MPU (Micro Processing Unit) 11 actually executes various programs. ROM (Read Only Memory)
Reference numeral 12 stores basically fixed data among programs and calculation parameters used by the MPU 11. RAM (Rand
The om Access Memory 13 stores a program used in the execution of the MPU 11 and parameters that change as appropriate in the execution. The IEEE1394 interface 14
This is an input / output interface based on IEEE1394 to which the IEEE1394 serial bus 3 is connected.

An LCD (Liquid Crystal Display) 16 and a touch panel 17 are connected to an internal bus via an input / output interface 15. The LCD 16 has a decoding unit 18, a recording / playback unit 19, an MPU 11, or an IEEE 1
394 The display data supplied from the interface 14 is displayed. The touch panel 17 supplies a signal corresponding to a user's operation to the input / output interface 15. The decoding unit 18 converts video data and audio data supplied from the IEEE1394 interface 14 or the recording / reproducing unit 19 into an analog video signal and an analog audio signal. The recording / reproducing unit 19 generates a digital VTR 1 based on the input data.
Data is recorded or reproduced on a video tape (not shown) mounted on the. MPU11, ROM12, RAM1
3, the IEEE1394 interface 14, the input / output interface 15, the decode unit 18, and the recording / reproducing unit 19 are interconnected by an internal bus.

FIG. 2 shows an embodiment of the present invention, MP
It is a functional block diagram of a decoder realized by U11 executing a program. The packet input via the IEEE1394 serial bus 3 is supplied to the extraction unit 25 of the IEEE1394 interface 14, and the extraction unit 25 converts the packet into frame pulse data and CIP (Comm.
on isochronous Packet) header, and extract the flag that identifies the NTSC or PAL method.
It is supplied to the L processing unit 21 and the synchronization control unit 22. In the synchronization control unit 22, the format of the signal to be output (NTSC or PAL) is set based on the data stored in the ROM 12.
The synchronization control unit 22 checks the NTSC or PAL system identification flag supplied from the extraction unit 25 based on the set signal system, and controls the software PLL processing unit 21 and the data processing unit 24. Software PLL processing unit 21
Generates a frame pulse synchronized with the frame pulse data supplied from the extraction unit 25 under the control of the synchronization control unit 22 and supplies the frame pulse to the synchronization control unit 22 and the frame pulse count processing unit 23.

The frame pulse count processing unit 23 determines whether the frame pulse from the software PLL processing unit 21 corresponds to the setting in the synchronization control unit 22, and if so, increments the counter value. If not, the counter value is cleared. The frame pulse count processing unit 23 supplies the value of the counter to the data processing unit 24. The data processing unit 24 instructs the recording / reproducing unit 19 to record data when the counter value of the frame pulse count processing unit 23 reaches a predetermined value. When the counter value of the frame pulse count processing unit 23 is equal to or smaller than a predetermined value, the data processing unit 24 instructs the recording / reproducing unit 19 to stop recording, and causes the LCD 16 to display a predetermined message.

Next, a digital VTR 2 integrated with a video camera
A data system supplied to the digital VTR 1 will be described. FIG. 3 shows a DVCR (Digita
1 is a diagram showing data of one track, which is a part of data of the Video Cassette Recorder system. The data of the DVCR method is output in order from the header packet (H0) on the left side of the figure, and after outputting a predetermined header packet (H0 to VA0),
Packets (Video) containing video data and packets (Audio) containing audio data are sequentially output at a ratio of 15: 1. FIG. 4 is a diagram showing a configuration of a packet of data of the DVCR system. Each packet has a length of 80 bytes.

FIG. 5 shows a digital VTR integrated with a video camera.
2 is connected to the IEEE1394 serial bus 3 by isochronous (Iso
When data is transmitted by synchronous communication, an isochronous packet (Isochronous P
FIG. 9 is a diagram for explaining conversion to an (acket). In FIG. 5, 480-byte source packets (Source Packets)
Is composed of six packets in the DVCR format. The source packet is divided into one to eight data blocks after adding a predetermined source packet header or the like. An isochronous packet includes a predetermined packet header, a CIP header, and zero or several data blocks.

FIG. 6 is a diagram showing a configuration of an isochronous packet. 2 from the transmitting side of the isochronous packet
Quadlet is a packet header. Data field of isochronous packet
The CIP header is stored in the first two quadlets.

FIG. 7 is a diagram showing main components of the CIP header. In the CIP header, DBS (Data Block Size in quadlets) storing the size of the data block, FN (Fraction Number) storing the number of divisions of the source block, N
50/60 for identifying the TSC or PAL system is arranged. When the video camera-integrated digital VTR 2 outputs real-time data, the MSB (Most S
ignitant Bit) stores “0”. At this time, SYT
(Not shown in the figure) contains 16-bit "111110111111"
A time stamp composed of a bit pattern of 1111 "is stored. When the transmitted data has the DVCR system," 0 "is stored in all the remaining 5 bits of the FMT.

Next, referring to the flowchart of FIG.
The data recording operation of the digital VTR 1 will be described. In step S11, the digital VTR 1 uses the data stored in the ROM 12 to set the type of signal to be identified (NTSC or PAL) in the synchronization control unit 22. The synchronization control unit 22 of the digital VTR 1 stores the set signal type, and requests the software PLL processing unit 21 to perform an operation corresponding to the signal type. In step S12, the synchronization control 22 requests the frame pulse count processing unit 23 to clear the counter.
Clears the counter in response to the request. In step S13, the synchronization control unit 22
2. Clear the CIP50 / 60 storage register inside 2.

The software PLL processing unit 21 includes the extraction unit 2
5 generates a frame pulse synchronized with the frame pulse transmitted. Frame pulse count processing unit 2
3. In step S14, the generation timing of the frame pulse generated by the software PLL processing unit 21 is
It is determined whether the method matches the method set in the synchronization control unit 22. If it is determined that they match, the process proceeds to step S16, and the frame pulse count processing unit 23 increments the counter value. If it is determined that they do not match, the process proceeds to step S15, and the frame pulse count processing unit 23 clears the counter value.

In step S17, the data processing unit 2
4 determines whether or not the counter value of the frame pulse count processing unit 23 exceeds a predetermined threshold value, in this case 8; If it is determined that the counter value exceeds 8, in step S18, the data processing unit 24 instructs the recording / reproducing unit 19 to execute recording, and the procedure returns to step S14 to continue the processing.

At step S17, the counter value becomes 8
If it is determined to be the following, in step S19, the data processing unit 24 instructs the recording / reproducing unit 19 to stop recording.

In step S20, the synchronization control unit 22
Is NTSC or P of the CIP header transmitted from the extraction unit 25.
It is determined whether or not the flag for identifying the AL method matches the contents of the CIP50 / 60 storage register. If it is determined that the content of the CIP50 / 60 storage register matches the signal type of the packet header, the procedure proceeds to step S21. At step 21, the synchronization control unit 22
Requests the L processing unit 21 to perform an operation corresponding to the type of the flag for identifying the NTSC or PAL system of the CIP header,
Returning to step S14, the processing is continued.

If it is determined in step S20 that the content of the CIP50 / 60 storage register does not match the signal type of the packet header, the synchronization control unit 22 stores the NTIP or PAL of the CIP header in the CIP50 / 60 storage register. Is set, and the procedure returns to step S14 to continue the processing.

This process is completed when the user operates the touch panel 17 corresponding to the end of the recording operation.

As described above, the digital VTR 1 is based on the IEEE139
(4) A plurality of types of data supplied via the serial bus 3 are reliably recorded.

[0028] As a providing medium for providing a user with a computer program for performing the above processing, there are provided:
In addition to recording media such as magnetic disks, CD-ROMs, and solid-state memories, communication media such as networks and satellites can be used.

[0029]

As described above, according to the data processing device, the data processing method, and the providing medium of the present invention, the synchronization timing is switched in accordance with the format of the input video data. It is possible to record video data of a system.

[Brief description of the drawings]

FIG. 1 is a hardware configuration diagram of a digital VTR.

FIG. 2 is a functional block diagram of a digital VTR.

FIG. 3 is a diagram showing data of one track, which is a part of data of the DVCR system.

FIG. 4 is a diagram showing a configuration of a packet of data of the DVCR system.

FIG. 5 is a diagram for explaining data conversion from output data of the DVCR system to an isochronous packet.

FIG. 6 is a diagram showing a configuration of an isochronous packet.

FIG. 7 is a diagram showing main components of a CIP header.

FIG. 8 is a flowchart illustrating a recording operation of a digital VTR.

FIG. 9 is a diagram illustrating a connection example of devices connected by an IEEE1394 serial bus.

[Explanation of symbols]

1 digital VTR, 25 extraction unit, 21 software PLL processing unit, 22 synchronization control unit, 23 frame pulse count processing unit, 24 data processing unit

Claims (3)

[Claims] 1. A data processing device for processing video data input via a bus, comprising: a generation unit configured to generate a frame pulse synchronized with a frame pulse input from the bus; Changing means for changing the synchronization timing of the input frame pulse of the generating means; counting means for counting the frame pulses generated by the generating means; and data processing based on the value counted by the counting means. A data processing apparatus comprising: an instruction unit configured to instruct another function of the apparatus to perform a predetermined process. 2. A data processing method for processing video data input via a bus, comprising: a generating step of generating a frame pulse synchronized with a frame pulse input from the bus; A changing step of changing the synchronization timing of the input frame pulse in the generating step, a counting step of counting the frame pulse generated by the generating step, and the data processing based on the value counted by the counting step. An instruction step of instructing another function of the apparatus to perform a predetermined process. 3. A data processing device for processing video data input via a bus, comprising: a generating step of generating a frame pulse synchronized with the frame pulse input from the bus; A changing step of changing the synchronization timing of the input frame pulse in the generating step, a counting step of counting the frame pulse generated by the generating step, and the data processing based on the value counted by the counting step. A providing medium for providing a computer-readable program for executing a process including an instruction step of instructing another function of the device to perform a predetermined process.