JPH11355645A - Head separation type image pickup system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a head separation type image pickup system and a phase synchronization method capable of correctly processing the chrominance signals of output images by correcting the phase difference of a clock and a synchronizing signal generated by the length of a cable, evading the deviation of image signals by correcting delay time by the cable length and normally outputting images at all times even when the cable length is changed. SOLUTION: This head separation type image pickup system is constituted by connecting a camera head 100 provided with an oscillation circuit 104 for outputting clock signals and a signal processor 200 provided with a synchronizing signal generation circuit 201 for generating the synchronizing signals based on the clock signals by the cable 300 and is provided with a phase comparator circuit 208 for detecting the phase difference of the synchronizing signals and the clock signals in the camera head and a delay circuit 202 for delaying the synchronizing signals corresponding to the phase difference detected by the phase comparator circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a head-separated imaging system, and more particularly to a head-separated imaging system for correcting a delay time caused by a length of a cable connecting a connected camera head and a signal processing device. About.

[0002]

2. Description of the Related Art Conventionally, in an imaging system using a solid-state imaging device such as a CCD, an imaging section (camera head) and a signal processing section for processing and outputting signals from the imaging section are separated, and a cable or the like is interposed therebetween. Many image pickup systems to be connected, so-called so-called head-separated cameras, have been proposed.

An image pickup system of this type is configured as shown in FIG. 17, and the length of a cable to be connected is determined by a delay time setting circuit for determining a fixed delay time.
Hereinafter, a conventional imaging system will be described with reference to FIG.

[0004] In Fig. 17, 100p is a camera head, 200p is a signal processing unit for performing signal processing of an image signal picked up by the camera head 100p, and 300p is a cable connecting the camera head 100p and the signal processing unit 200p.

In the camera head 100p, reference numeral 11 denotes a CCD as photoelectric conversion means, and reference numeral 12 denotes a timing signal generation circuit (TG) which converts a signal photoelectrically converted by the CCD 11 into a signal to be described later.
The horizontal black level portion is clamped at the timing of the sampling pulse output from the sampler 13, the captured image signal and the vertical and horizontal black level portions are sampled, and an amplification factor according to a control signal from the microcomputer 15 described later. CDS / AG that amplifies the signal and blanks and outputs a portion other than the image or the black level signal at the timing of a blanking pulse output from a TG 13 described later.
A C circuit 13 is a clock CLK of an oscillation circuit 14 described later.
And a timing signal generating circuit (T) that outputs a drive signal of the CCD 11 and a sampling / blanking pulse of the CDS / AGC circuit 12 in synchronization with a synchronization signal described later.
G) and 14 are connected to the TG 103, and the TG 103 and a synchronous signal generation circuit (SS
G) Oscillation circuit composed of a crystal oscillator, which outputs CLK serving as a clock for 21;
Microcomputer 16 that controls the overall operation of
5 and an image signal from the CDS / AGC circuit 12.

In the signal processing unit 200p, 21
Is the clock CL sent from the camera head 100p
K based on signal processing unit 200p and camera head 1
A synchronization signal generation circuit (SSG) for generating a reference synchronization signal SYNC used in 00p, a delay time setting circuit 22 for outputting the synchronization signal SYNC generated by the SSG 21 with a predetermined time delay, and a camera head 100p A separation circuit that separates the composite signal from the image signal into an image signal and a control signal, inputs the image signal to a signal processing circuit 26 described later, and inputs the control signal to a microcomputer 25 described later.
0p is a microcomputer for controlling the overall operation of the camera head, 26 is a signal processing circuit for processing the image signal, and 27 is a power supply voltage controlled by the microcomputer 25 to supply power to the camera head 100p.
Is a power supply circuit for supplying power to the power supply.

Next, the operation of the imaging system having the above configuration will be described.

First, when DC power is supplied to the signal processing unit 200p, the microcomputer 25 starts up and performs initialization. When the initialization of the microcomputer 25 is completed,
The microcomputer 25 controls the power supply circuit 27 to supply power of a predetermined voltage to the camera head 100p. When power is supplied to the camera head 100p, the camera head 100p
Microcomputer 105 starts up and performs initialization.
Further, the oscillation circuit 14 starts oscillating, and the clock CLK is output and supplied to the SSG 21 via the cable 300p. The SSG 21 generates a synchronization signal SYNC based on the supplied clock CLK, and outputs it to the camera head 100p via the cable 300p.

The TG 13 generates a drive signal based on the synchronization signal SYNC and drives the CCD 11. The signal output from the CCD 11 is subjected to signal processing by the CDS / AGC circuit 12 and input to the adder circuit 16 as an image signal. The adder circuit 16 superimposes the input image signal and the control signal input from the microcomputer 15 and sends the composite signal to the signal processing unit 200p. Separation circuit 24 of signal processing unit 200p
Receives the transmitted composite signal, separates it into an image signal and a control signal, and outputs the image signal to the signal processing unit 26 and the control signal to the microcomputer 25.

The synchronizing signal generated by the SSG 21 is transmitted to the camera head 100p and is simultaneously output to the delay time setting circuit 22. The synchronization signal sync delayed for a predetermined time by the delay time setting circuit 22 is output to the signal processing circuit 2
6 and the signal processing circuit 26 outputs the synchronization signal sync
The image signal is processed according to.

[0011]

However, in the market, in order to cope with various usage forms, a small camera head having characteristics suitable for the application and a signal processing unit for performing signal processing suitable for them are separated. In addition, it is desired to connect between them by a cable having a length suitable for use conditions. However, as described above, if the connection is made with a cable other than the prescribed cable length, the timing of processing in the signal processing unit is shifted, so that a cable other than a fixed length cannot be used.

In particular, when the camera head has a motor drive system such as a zoom lens, the power supply voltage supplied to the signal amplification circuit system of the camera head is increased due to an increase in current flowing when the motor is driven. There is a problem in that the output image signal is dropped as it becomes longer, and remarkable low-frequency noise is superimposed on the output image signal.

Therefore, the present invention corrects the phase difference between the clock and the synchronizing signal caused by the length of the cable so that the color signal of the output image can be correctly processed. It is therefore an object of the present invention to provide a head-separated imaging system capable of avoiding a shift in the timing of image signal processing by correcting, and always outputting an image normally even when the cable length is changed.

[0014] Further, the power supply may be constituted by a power supply whose output power supply voltage on the supply side can be changed so as to correct the drop of the supply power supply voltage in accordance with the cable length. And set
It is an object of the present invention to provide a head-separated imaging system capable of selecting an arbitrary cable length according to a purpose of use without causing image disturbance.

[0015]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and a head-separated imaging system according to the present invention has an image pickup apparatus having a reference signal generating means for generating and outputting a reference signal. And a signal processing device having a synchronization signal generating means for generating a synchronization signal based on the reference signal. A first delay unit that delays a synchronization signal generated by the synchronization signal generation unit in accordance with the phase difference detected by the phase difference detection unit.

Further, according to one aspect of the present invention, the phase difference detecting means and the first delay means are on the imaging device side.

According to another aspect of the present invention, the phase difference detecting means and the first delay means are on the signal processing device side.

Preferably, the phase difference detecting means includes:
An analog integrator that is reset at the timing of inputting the reference signal and starts integration, and a sampling unit that reads a voltage of the analog integrator at the timing of input of a synchronization signal.

Preferably, the apparatus further comprises means for outputting a synchronization signal generated by the synchronization signal generation means to the imaging device, and means for inputting the output synchronization signal and feeding it back to the signal processing device. The phase difference detection means detects a phase difference between a reference signal generated by the reference signal generation means and input via the cable, and a synchronization signal returned from the imaging device.

Preferably, a measuring means for measuring a time difference between the synchronizing signal output by the synchronizing signal generating means and the synchronizing signal fed back, and an output of the synchronizing signal delayed according to the time difference measured by the measuring means. And second delay means for causing the delay to occur.

According to another aspect of the present invention, a head-separated type imaging system includes an imaging device having a reference signal generating means for generating and outputting a reference signal, and generating a synchronization signal based on the reference signal. A signal processing device having a synchronizing signal generating means connected by a cable, configured to output a synchronizing signal generated by the synchronizing signal generating means to an imaging device; and Means for feeding back the signal to the signal processing device; measuring means for measuring a time difference between the synchronizing signal generated by the synchronizing signal generating means and the synchronizing signal fed back from the imaging device; and a means for measuring a time difference measured by the measuring means. Delay means for delaying the output of the synchronization signal.

Preferably, the second delay means or the delay means delays the output of the synchronization signal in units of the reference signal.

According to one aspect of the present invention, the measuring means includes a pulse signal generating means for outputting a pulse signal which rises by a synchronization signal output from the synchronization signal generation circuit and falls by a feedback synchronization signal. The pulse signal generated by the pulse signal generating means is HIGH.
And an analog integrating means for integrating during the period, and the delay time is controlled by the second delay means or the delay means according to the voltage of the analog integrating means.

According to another aspect of the present invention, the measuring means outputs a pulse signal which rises by a synchronization signal output from the synchronization signal generation circuit and outputs a pulse signal which falls by a feedback synchronization signal. And the pulse signal generated by the pulse signal generating means is HIG
And counting means for counting the reference signal during the period of H, and the delay time is controlled by the second delay means or the delay means according to the count number of the counting means.

Preferably, a measuring means for measuring a time difference between the synchronizing signal output by the synchronizing signal generating means and the synchronizing signal fed back, and a signal supplied to the imaging device in accordance with the time difference measured by the measuring means. And a power supply voltage increasing / decreasing means for varying the power supply voltage.

Preferably, when the time difference measured by the measuring means is large, the power supply voltage is increased, and when the time difference is small, the power supply voltage is decreased.

Preferably, the signal processing device further includes a separating unit for separating a signal input from the image pickup device into a feedback signal and a signal other than the feedback signal. The signal and another signal are multiplexed and output to the signal processing device.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] An embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a basic configuration of a head-separated camera (imaging system) according to an embodiment of the present invention.

In FIG. 1, reference numeral 100 denotes a camera head for capturing an image of a subject; 200, a signal processing unit for performing signal processing on an image signal captured by the camera head 100; 300, a cable for connecting the camera head 100 and the signal processing unit 200;
Reference numeral 401 denotes a monitor for displaying and outputting a video signal captured by the camera head 100 and subjected to signal processing by the signal processing unit 200. Reference numeral 402 denotes an AC adapter for supplying power to the signal processing unit and the camera head.

FIG. 2 is a block diagram showing the internal configuration of the camera head 100 and the signal processing section 200 shown in FIG.

In the camera head 100 shown in FIG.
101 is a CCD which is a photoelectric conversion means, 102 is a CCD1
01, the black level portion in the horizontal direction is clamped at the timing of a sampling pulse output from a timing signal generation circuit (TG) 103 described later,
The taken image signal and the black level portions in the vertical and horizontal directions are sampled and amplified at an amplification factor according to a control signal from the microcomputer 105, which will be described later.
A CDS / AGC circuit that blanks and outputs a portion other than an image or a black level signal at the timing of a blanking pulse output from the reference numeral 03. A timing signal generation circuit (TG) 104 that synchronously outputs a drive signal of the CCD 101 and a sampling / blanking pulse of the CDS / AGC circuit 102, and 104 is a TG 103
TG 103 and a signal processing unit 20 described later.
Oscillation circuit composed of a crystal oscillator, which outputs CLK which is a clock of a synchronization signal generation circuit (SSG) 201 of 0, a microcomputer 105 for controlling the overall operation of the camera head 100, and a signal processing unit 200 Is a buffer circuit that returns a synchronization signal SYNC ′ input from the signal processing unit 200 to the signal processing unit 200.

In the signal processing section 200, 201
Is the clock CLK sent from the camera head 100
Processing unit 200 and camera head 100 based on
A synchronizing signal generation circuit (SSG) 202 for generating a reference synchronizing signal SYNC to be used in step S202; a delay circuit 203 for delaying and outputting the synchronizing signal SYNC output from the SSG 201 in accordance with a control signal of a phase comparison circuit 208 described later; Is S
A flip-flop circuit (F) that outputs as a pulse the time difference between the synchronization signal SYNC output from the SG 201 and the synchronization signal SYNC "returned from the camera head 100.
F) and 204 are time-voltage (T) for outputting a voltage corresponding to the pulse signal output from the flip-flop circuit 203.
-V) a conversion circuit; 205, a microcomputer for controlling the overall operation of the signal processing unit 200; 206, a camera head 100;
A signal processing circuit for performing signal processing on an image signal transmitted from the microcomputer 205; a power supply circuit 207 for supplying power to the camera head 100 at a power supply voltage controlled by the microcomputer 205;
208 is a clock C transmitted from the camera head 100
This is a phase comparison circuit that compares the phase of LK with the synchronization signal SYNC "and outputs the result to the delay circuit 202.

Next, the operation of the imaging system having the above configuration will be described.

First, when DC power is supplied to the signal processing unit 200, the microcomputer 205 starts up and performs initialization. When the initialization of the microcomputer 205 is completed, the microcomputer 205 uses the control signal CTL to supply power of a predetermined voltage from the power supply circuit 207 to the camera head 1.
Supply to 00. When power is supplied to the camera head 100, the microcomputer 105 of the camera head 100 starts up and performs initialization. Further, the oscillation circuit 104 starts oscillating, and the clock CLK is output and supplied to the SSG 201 and the phase comparator 208 via the cable 300. The SSG 201 generates a synchronization signal SYNC based on the supplied clock CLK, and outputs it to the delay circuit 202. The delay circuit 202 delays the input synchronization signal SYNC based on the initial value input from the phase comparison circuit 208, and outputs the delayed synchronization signal SYNC 'to the camera head 100 via the cable 300.

The synchronization signal S input to the camera head 100
YNC ′ is input to the TG 103 and the buffer circuit 106, and the buffer circuit 106 returns the input synchronization signal to the signal processing unit 200. From the buffer 106 to the signal processing unit 2
00 is returned to the phase comparator 208.
And FF203. Here, first, details of the phase comparator 208 will be described.

FIG. 3 is a block diagram showing the internal configuration of the phase comparison circuit 208 and the delay circuit 202 shown in FIG.
FIG. 4 is a timing chart showing signals output from each circuit shown in FIG.

In FIG. 3, reference numeral 2081 denotes a differentiating circuit;
Reference numeral 82 denotes an integration circuit, and reference numeral 2083 denotes a synchronizing signal SYNC "(FIG. 4D) returned from the buffer circuit 106 of the camera head 100 based on the integration waveform (FIG. 4C) of the integration circuit 2082.
And a sampling circuit 2084 for amplifying the voltage (FIG. 4E) sampled by the sampling circuit 2083. The delay circuit 202 controls a delay time added to the synchronization signal SYNC input from the SSG 201 according to the voltage output from the amplifier circuit 2084.

In FIG. 3, first, the differentiating circuit 2081 generates a pulse (FIG. 4B) which becomes HIGH for a very short time in synchronization with the rising of the input clock CLK (FIG. 4A). . This differential pulse is HIGH
During this period, the integration circuit 2082 discharges and is reset, and when it becomes LOW, it is charged with a predetermined current.
The waveform of the integrating circuit 2082 that repeats the discharging and charging in this manner has a saw-tooth shape as shown in FIG. The sampling circuit 20 converts the sawtooth voltage waveform into a synchronizing signal SYNC "returned from the camera head 100.
By sampling at 83, the phase relationship between the clock CLK and the synchronization signal SYNC "is detected as a voltage (FIG. 4E). In this case, the clock CLK and the synchronization signal SYNC" are transmitted from the camera head 100 to the same cable 300. Therefore, the phase of the clock and the synchronization signal in the camera head 100 is maintained. Therefore, the phase relationship detected here is equal to the phase relationship between the synchronization signal CLK and the synchronization signal SYNC 'in the camera head 100.

As for the phase relationship, the synchronization signal SYN
If the switching timing of C "is exactly in the middle of the rising edge of the clock CLK, a synchronization shift is unlikely to occur even under the influence of external noise or the like. ,
If the synchronization signal SYNC "is earlier and the detected voltage is lower, or if the synchronization signal SYNC" is later and the detected voltage is higher, the voltage is amplified according to the voltage amplified by the next-stage amplifier circuit 2084. The delay time is adjusted by the delay circuit 202.

FIG. 5 shows a configuration example of the delay circuit 202. In the figure, reference numeral 2021 denotes a buffer circuit for inputting a synchronization signal SYNC output from the SSG 201;
A buffer circuit for outputting YNC ′, a resistor 2022 inserted between the buffer 2021 and the buffer 2023,
2024 is a capacitor, 2026 is a varicap diode, 2025 is a resistor for applying the output voltage of the amplifier 2084 to the varicap diode 2026,
The capacitance of the varicap diode 2026 changes according to the voltage applied from the resistor 2025.

In the delay circuit shown in FIG. 5, since an LPF having a load of a varicap diode 2026 biased by an input voltage (the output of the amplifier 2084, a signal obtained by amplifying FIG. 4E) is formed. When the input voltage is low, the capacitance of the varicap diode 2026 increases, the delay amount of the delay circuit 202 increases, and the output timing of the synchronization signal SYNC 'is delayed. Of course,
Since the timing of the transmitted synchronization signal SYNC 'is delayed, the timing of the returned synchronization signal SYNC "is also delayed, and the phase difference between the clock CLK and the synchronization signal SYNC" is increased. If the timing of the synchronization signal SYNC ′ is delayed, the varicap diode 202
6, the timing at which the synchronizing signal SYNC 'is output is advanced, and the phase difference between the clock CLK and the synchronizing signal SYNC "is reduced. In this way, the position of the clock CLK and the synchronizing signal SYNC" is reduced. The phase difference is adjusted to be approximately one half of the duration of the clock CLK.

In parallel with the delay time adjustment by the delay circuit 202, the sampling signal output from the amplifier 2084 is A / D-converted by an A / D circuit (not shown) and input to the microcomputer 205. The microcomputer 205 determines whether or not the obtained value is within a range of a preset value. As described above, by detecting that the timing is within the range of the preset value, it is possible to detect a state where the timing of the synchronization signal SYNC "is just in the middle of the clock CLK.

As described above, when the microcomputer 205 detects that the timing of the synchronization signal SYNC "is exactly in the middle of the clock CLK, the microcomputer 205 uses the synchronization signal SYNC output from the SSG 201 and the camera head 100 in the same manner. , Which is a time difference from the synchronization signal SYNC "returned from.

Synchronization signal SY output from SSG 201
Since NC is a signal inside the signal processing unit 200, it is input to the delay circuit 202 and the FF circuit 203 with almost no delay. On the other hand, a synchronization signal SYNC "which is the other input signal of the FF circuit 203 is input to the camera head 100 via the cable through the delay circuit 202, and is received by the buffer 106 of the camera head 100. From the buffer 106 again via the cable, the signal processing unit 20
It returns to 0 and is input. Therefore, the synchronization signal SYNC "is input after being delayed from the synchronization signal SYNC, and the amount of delay is
It is roughly the sum of the time spent through the delay circuit and the two cables.

Note that the period T of the synchronization signal SYNC is about 63
In the case of μsec, the cable length is at least 6.3 km in order to cause a delay of one cycle or more due to the cable length.
become. Realistically, considering the voltage drop of the power supplied to the camera head 100, the practical range is several tens of meters, so that the synchronizing signal SYNC "cannot be delayed more than one cycle from the synchronizing signal SYNC.

However, this delay time becomes longer,
When it reaches one clock for reading each pixel,
A timing shift occurs in the processing of the image signal sent from the camera head 100. Since the image signal is the same as the array of signals output from the CCD, for example, cyan, magenta, green, and yellow are sequentially input, respectively. If this signal is processed in accordance with a synchronization signal shifted by one clock, there is a problem that a magenta color signal is processed as a cyan color signal and a green color signal is processed as a magenta color signal.

The input order of the color signals is uniquely determined by the CCD, but the start timing is determined by the synchronization signal SYNC 'sent from the SSG 201 via the delay circuit 202. Therefore, if a delay due to the cable occurs, a time lag occurs between the start of signal processing in the signal processing circuit 206 and the start of image reading in the camera head 100, and transmission of an image signal from the camera head 100. Accordingly, the image signal reaching the signal processing circuit 206 is delayed and a further time lag occurs. Therefore, it is necessary to correct the difference between the time at which the signal processing circuit 206 starts processing and the time until the image signal is input to the signal processing circuit 106.

The operation of detecting the delay time will be described below.

FIG. 6 is a block diagram showing the internal configuration of the TV conversion circuit 204 and the flip-flop circuit 203 of FIG. FIG. 7 is a timing chart showing signals of respective units in the configuration example shown in FIG. Less than,
Each configuration shown in FIG. 6 will be described with reference to the timing chart of FIG.

In FIG. 6, reference numeral 203 denotes a flip-flop circuit which outputs a time difference between a synchronization signal SYNC input from the SSG 201 and SYNC "input from the buffer circuit 106 of the camera head 100 as a pulse signal,
Reference numeral 2041 denotes a charging circuit which charges only during a period when the output pulse signal of the flip-flop circuit 203 is HIGH and discharges by a reset pulse φR from a mono-multi circuit (MM) 2043 described later. The sampling circuit 2043 performs sampling by the sampling pulse φSPL from the MM 2043 and outputs a voltage signal. The sampling circuit 2043 performs the sampling pulse φSPL after a predetermined time from the synchronization signal SYNC.
And a mono-multi circuit (MM) that outputs a reset pulse φR.

From the camera head 100 to the signal processing unit 200
The synchronization signal SYNC "(FIG. 7B) returned to
Synchronization signal SYNC output from 201 (FIG. 7A)
And input to the flip-flop circuit 203. In the flip-flop circuit 203, the synchronization signal SYNC output from the SSG 201 is input to the SET input terminal, and the synchronization signal SYNC "returned from the buffer 106 of the camera head 100 is input to the RESET input terminal. The output is set to HIGH at the falling edge of the synchronization signal SYNC, and the synchronization signal SYNC is
The output is made LOW at the falling edge of C "(FIG. 7
(C)).

Here, since the output pulse signal of the FF circuit 203 is the round trip time of the synchronization signal, this is from the input of the synchronization signal SYNC to the signal processing circuit 206 until the reception of the image signal from the camera head 100. The time difference. Therefore, this time difference, that is, the duration of the output pulse is measured, and the signal processing circuit 2 is provided by the time difference.
If the timing of the synchronizing signal sync input to 06 is delayed, signal processing, particularly color processing, can be performed at correct timing.

In the first embodiment, the FF circuit 20 which is the time difference between the synchronization signals SYNC and SYNC "is used.
The output pulse signal of No. 3 is input to the charging circuit 2041. The charging circuit 2041 performs charging only while the pulse is HIGH (FIG. 7D). Note that, as described above, the charging circuit 2041 performs the reset pulse φ from the MM circuit 2043.
It is reset by R (FIG. 7 (F)). Since the charging result corresponds to the output pulse length of the FF circuit 203 on a one-to-one basis, if this voltage is detected, the delay time can be correctly determined. Accordingly, the sampling circuit 2042 samples the output signal of the charging circuit 2041 at the timing of the sampling signal φSPL (FIG. 7E) output from the MM circuit 2043, and outputs it.

Then, the sampling signal (FIG. 7 (G)) output from the TV circuit 204 is A / D converted by an A / D circuit (not shown) and input to the microcomputer 205. The microcomputer 205 controls the SSG 201 to delay the synchronization signal SYNC by a time corresponding to the input value, and outputs a delayed synchronization signal sync to the signal processing circuit 206.

In the above-mentioned operation, "judging correctly" means judging a delay time during which a color signal is processed correctly by the signal processing circuit 206. Will be described.

In order to correctly process a color signal, it is necessary to have an accuracy of a clock unit. However, since the synchronization signal output from the SSG 201 to the signal processing circuit 206 is generated from a clock input to the SSG 201, The phase difference becomes constant. Therefore, it is only necessary to absorb a time lag caused by jitter or the like. Therefore, the accuracy is ± 15
An accuracy of about nsec is sufficient. Therefore, if the output voltage of the sampling circuit 2042 is subjected to data conversion by an 8-bit A / D circuit, the detectable range is 30 (nsec) × 255 = 7650 (nsec) =
7.65 μsec. This corresponds to a cable length of about 750 m (considering the delay time due to the delay circuit 202 and the like). As described above, the camera head 100
Considering the voltage drop of the power supplied to the cable, the practical range is several tens of meters. Therefore, it is practically sufficient if a cable length up to about 750 m can be handled. Therefore, in the present embodiment, the MM circuit 2043 10 μsec after the synchronization signal SYNC.
, A sampling pulse φSPL is output and the data is held. After about 20 μsec, a reset pulse φR is output and the charging circuit 2041 is discharged to be in a state of waiting for the next charging.

Since the delay time is uniquely determined by the cable length, it is not necessary to always detect the delay time, and once the initialization is performed while the camera head 100 is connected to the camera head 100, the delay time is thereafter determined. What is necessary is just to hold a state.

As described above, the microcomputer 205 controls the FF 20
3, the output voltage of the charging circuit 2041 charged only during the HIGH period of the pulse output from the sampling circuit 2042, that is, the voltage signal output from the sampling circuit 2042,
A / D conversion is performed by a D circuit, the data is captured as digital data, and the timing of the image signal sent from the CCD is calculated according to the value. Based on the calculated timing, it is determined which of the cyan, magenta, green and yellow color signals the color signal to be fetched and processed by the clock CLK is.

The above-mentioned determination by the microcomputer 205 is based on the fact that the feedback synchronization signal SYNC "is used as it is by the signal processing circuit 206.
Can be made unnecessary by entering
In the first embodiment, since the synchronization signal SYNC "is sent only at the time of initialization, it is necessary to measure a phase difference and hold the state.

Finally, the microcomputer 205 calculates the cable length based on the detected delay time. As described above, the detected delay time is mainly the sum of the delay time due to the delay circuit 202 and the time required for the signal to travel round the cable 300. Therefore, calculation is performed by a preset calculation formula based on the detected delay time, or a lookup table indicating the relationship between the delay time and the cable length is stored in advance, and the cable length is determined. , Cable length.

The voltage supplied to the camera head 100 is controlled by controlling the power supply circuit 207 according to the detected cable length. The amount of voltage lowered by the cable varies depending on the current consumption, but is usually about 70 mV /
m. Therefore, for example, when the cable length obtained from the delay time is 11 m, 11 (m) × 70 (mV /
m) may be increased at the output stage. In this regard, since a regulator IC capable of controlling the output voltage is commercially available, the voltage of the control terminal may be controlled. As an example of such a regulator IC, FIG. 16 shows a simplest circuit example using a feedback-type operational amplifier.

In the figure, reference numeral 701 denotes a power input terminal;
02, a power output terminal; 703, an output voltage control signal input terminal; 711, a power transistor for supplying power;
Is a transistor, 713 is an operational amplifier, 714, 715
Is a resistor for detecting an output power supply voltage, 716 and 717 are a resistor and a capacitor for LPF for removing a noise component of a control signal, 718 is a resistor, and a circuit divided by resistors 714 and 715 is a control input terminal. Since the operation is performed so as to be equal to the voltage input to the resistor 703, for example, the resistor 71
When 4 and the resistor 715 are equal, 35 mV per meter
If the control signal is increased, the output voltage becomes 70 / m
An increase in mV is obtained, which can compensate for the voltage lost in the cable.

In the above description, the hardware configuration such as control has been described. However, a part of voltage detection and the like can be processed by the microcomputer.

In the first embodiment, the phase comparison circuit 208 and the delay circuit 202 are provided on the signal processing unit 200 side, but may be provided on the camera head 100 side.

As described above, according to the first embodiment, even when the length of the cable connecting the connected camera head and the signal processing device is different, the delay time caused by the cable length is corrected. Thus, correct signal processing can be performed.

Further, it is possible to correct a drop in the power supply voltage due to the cable length.

[Second Embodiment] Hereinafter, a second embodiment of the present invention will be described.

FIG. 8 is a schematic diagram showing the configuration of an imaging system according to the second embodiment. 8, the same components as those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted. In the second embodiment, the clock CLK output from the oscillation circuit 104 is also input to the TV conversion circuit 204, and the delay circuit 600 controlled by the TV conversion circuit 204 operates between the SSG 201 and the signal processing circuit 206. Has been inserted.

In FIG. 8, the phase comparison circuit 208 and the delay circuit 202 are provided on the signal processing unit 200 side, but may be provided on the camera head 100 side.

In the second embodiment, TV
The internal configuration of the conversion circuit 204 is different from that described in the first embodiment with reference to FIG. Hereinafter, the configuration and operation will be described.

FIG. 9 is a block diagram showing another example of the internal configuration of the TV conversion circuit 204 of FIG. FIG. 10 is a timing chart showing signals of respective units in the configuration example shown in FIG. Hereinafter, FIG.
Will be described with reference to the timing chart of FIG.

When the synchronization signal SYNC (FIG. 10A) is input, the output of the flip-flop circuit 203 becomes HIGH.
H, and when a synchronization signal SYNC "(FIG. 10B) is input, the output is set LOW to output a pulse signal (FIG. 10D) indicating a phase difference. This pulse signal is a counter circuit 2044. The counter circuit 2044 receives the clock signal CLK (FIG. 10C) input to the clock terminal and outputs a pulse signal HI.
It is counted only during the period of GH.

That is, the output signal of the counter circuit 2044 (FIG. 10 (E) is 3 bits in this example) counts the number of clocks only when the output signal of the flip-flop circuit 203 is HIGH, and counts the counted clock. The number is output as a 4-bit digital signal. This signal is held by the next-stage latch circuit 2045 by the sampling signal φSPL (FIG. 10F) output from the MM circuit 2043 (FIG. 10H).

Next, counter circuit 2044 is reset in preparation for the next count by reset signal φR (FIG. 10 (G)) output from MM circuit 2043.

The delay time is measured as described above, and the synchronization signal SYNC is delayed based on the delay time,
G201, the delay synchronization signal syn is transmitted to the signal processing circuit 206.
c is output.

FIG. 11 shows a configuration for realizing this delay method.

In the figure, 601 is an input terminal for a clock CLK, 602 is an input terminal for a synchronization signal SYNC, and 60
Reference numeral 3 denotes a synchronizing signal output terminal output to the signal processing circuit 206, 604, 605, and 606 denote data signal input terminals for selecting the amount of delay of the synchronizing signal, and 610 to 617 denote synchronizing signals having the clock signal CLK as a clock input. A shift register 618 is a switch circuit for selecting either the synchronization signal SYNC input from the input terminal 602 or each output signal of the shift registers 610 to 616.

Synchronization signal SY input to input terminal 602
NC is latched by a shift register in response to a clock CLK, and the latched signal is input to the next-stage shift register 611 and similarly latched by the clock CLK.
Since 0 and 611 are latched by the same clock signal, the output signal of the shift register 611 is output one clock later than the output signal of the shift register 1. Similarly, a synchronization signal delayed by one clock is generated from the shift registers 612 to 616. The signals output from the respective shift registers with the clock CLK are input to the next-stage shift register and also to the switch circuit 618 at the same time.

A selection signal is input to the data input terminals 604 to 606. This selection signal is supplied to the latch circuit 20
4 bits latched by 45, MSB
Is input to 606, and the LSB is input to 604. The switch circuit 618 is switched according to the selection signal, and a synchronization signal corresponding to the delay time selected by the selection signal is output to an output terminal thereof, and is input to the shift register 617.

The shift register 617 outputs the clock CL
A synchronization signal synchronized with K is output, and output to the signal processing circuit 206 via the output terminal 603.

As described in the first embodiment,
Since the phase difference between the clock CLK and the synchronization signal SYNC "is controlled by the delay circuit 202 described above, F
Even if the clock signal CLK is counted only during the period when the pulse of the F circuit 203 is HIGH, accurate determination can be made.

According to the second embodiment, the same effects as those of the first embodiment can be obtained.

[Third Embodiment] Next, a third embodiment will be described.

FIG. 12 is a block diagram showing the configuration of an imaging system according to the third embodiment.

In FIG. 12, components similar to those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted. 107
Is the synchronization signal SYN input to the camera head 100
C ′, control signals CNTL and CDS from the microcomputer 105
The adder circuit 208 adds the image signal IM from the / AGC 102 and outputs it as a composite signal CMP. The adder 208 divides the composite signal CMP sent from the camera head 100 into an image signal, a synchronization signal IM and a control signal CNTL, and This is a separation circuit that outputs the signal IM to the signal processing circuit 206, the synchronization signal SYNC ′ to the flip-flop circuit 203, and the control signal CNTL to the microcomputer 205.

In the first embodiment, the number of signal lines is increased by one in order to feed back the synchronization signal SYNC ′ as compared with the conventional example. The increase in the number of signal lines means that the cable becomes thicker, which leads to a slightly harder routing and a higher cost in manufacturing. Therefore, in the third embodiment, the signal lines are shared to avoid a thick cable.

FIG. 13 shows a configuration example of the adder circuit 107.
5, reference numeral 501 denotes an input terminal of a control signal from the microcomputer 105; 502, an image signal input terminal from the CDS / AGC circuit 102; 503, an input terminal of a synchronization signal SYNC '; 504, an output terminal of a composite signal CMP; Is a buffer for the image signal IM, and 511 is a control signal CNTL is H
At the time of IGH, a switch circuit for operating a current mirror circuit 530 to be described later is 512. A switch circuit for operating a current mirror circuit 531 to be described later when the synchronization signal SYNC 'is LOW, 520 is a resistor, and 530 is predetermined by a switch circuit 511. A current mirror circuit 531, which outputs a given current, is a current mirror circuit 540, which draws a predetermined current by the switch circuit 512.
Is the output terminal 50 as the composite signal CMP
4 is a buffer circuit to be output.

FIG. 14 shows the waveforms of the signals output from the respective parts in FIG. FIG. 15 is a detailed circuit diagram of FIG. 13, but the description is omitted, and the operation will be described with reference to FIG.

First, the image signal IM is input from the input terminal 502 to the buffer circuit 510, and the image signal IM is directly input to the buffer circuit 540 via the resistor 520 (R). If the current mirror circuits 530 and 531 are not operating, the image signal is input to the buffer circuit 540 as it is, and output from the output terminal 504 as it is. Here, the control signal CNTL is
5 is input to the input terminal 501, the switch circuit 51
1 operates, and the current mirror circuit 530 operates only while the control signal CNTL is HIGH, and outputs a predetermined current i1 (mA). Thereby, the buffer circuit 5
At the input terminal 40, the current i1 from the current mirror circuit 530 flows to the resistor 520, so that the voltage is R × i1 (m
V). Thereby, the control signal CNTL is superimposed on the image signal IM.

Similarly, the synchronization signal SYNC 'is also supplied to the input terminal 50.
3 is input to the switch circuit 512, the switch circuit 512 outputs the current mirror circuit 531 only during the LOW period.
, The current mirror circuit 531 draws the current i2 (mA) only during the period when the synchronization signal SYNC ′ is LOW, and the input stage of the buffer circuit 540 outputs Rx
The voltage shifts to a voltage lower by i2 (mA).

As described above, the signal is superimposed by the voltage shift of the blanking period of the image signal IM by the control signal CNTL and the synchronization signal SYNC '. In the separation circuit 108 of the signal processing unit 200, the composite signal CM
P is separated by an A / D conversion circuit (not shown) of an image signal performed to process the image signal IM.
Digital signal or synchronizing signal (SYN)
Since it is easy to extract C "), the description is omitted.

Thus, the synchronizing signal SYNC from the SSG 201 and the composite signal CMP
After obtaining the synchronization signal SYNC "returned as
With the device configuration described in the first or second embodiment,
The timing of signal processing in the signal processing circuit 206 can be controlled.

As described above, according to the third embodiment of the present invention, the same effect as that of the first embodiment can be obtained, and at the same time, the third embodiment is used in the first and second embodiments. Since one signal line can be reduced as compared with a cable, the system can be configured using a thinner cable.

[0095]

As described above, the color signal of the output image can be correctly processed by correcting the phase difference between the clock and the synchronization signal caused by the length of the cable. Further, by correcting the delay time due to the cable length, it is possible to avoid a shift of the image signal, and to always output an image normally even if the cable length is changed. Also, the third
As shown in the embodiment, when the image signal and the synchronization signal are superimposed and realized without increasing the number of signal lines in the cable, the cable connecting the imaging unit and the signal processing unit does not become thick. It is possible to

Further, in order to set the power supply voltage to be supplied in relation to the cable delay time in accordance with the cable length so as to correct the drop of the power supply voltage in accordance with the cable length,
Any length of cable can be selected according to the purpose of use without causing image distortion.

[0097]

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a basic configuration of an imaging system according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of an imaging system according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing an internal configuration and a delay circuit of the phase comparison circuit shown in FIG. 2;

FIG. 4 is a timing chart illustrating waveforms of signals in a phase comparison circuit according to the first embodiment.

FIG. 5 is a detailed circuit diagram of the delay circuit shown in FIG. 2;

6 is a block diagram showing an internal configuration of the TV conversion circuit shown in FIG. 2 and a flip-flop circuit.

FIG. 7 is a timing chart showing signals of respective units in the configuration example shown in FIG.

FIG. 8 is a block diagram illustrating a configuration of an imaging system according to a second embodiment of the present invention.

FIG. 9 is a block diagram showing another example of the internal configuration of the TV conversion circuit of FIG. 2;

FIG. 10 is a timing chart showing signals of respective units in the configuration example shown in FIG. 9;

11 is a diagram illustrating a configuration example of a delay circuit illustrated in FIG. 8;

FIG. 12 is a block diagram illustrating a configuration of an imaging system according to a third embodiment of the present invention.

FIG. 13 is a block diagram illustrating a configuration example of an addition circuit.

FIG. 14 shows waveforms of signals output from respective units in FIG.

FIG. 15 is a detailed circuit diagram of FIG. 13;

FIG. 16 is a circuit diagram of a voltage control circuit in the power supply circuit.

FIG. 17 is a block diagram illustrating a configuration of a conventional imaging system.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 Camera head 101 CCD 102 CDS / AGC circuit 103 Timing signal generation circuit 104 Oscillation circuit 105 Microcomputer 106 Buffer circuit 200 Signal processing unit 201 Synchronization signal generation circuit 202 Delay circuit 203 Flip-flop circuit 204 TV conversion circuit 205 Microcomputer 206 Signal processing Circuit 207 Power supply circuit 208 Phase comparison circuit 300 Cable 600 Delay circuit

Claims (19)

[Claims] An image pickup apparatus having a reference signal generating means for generating and outputting a reference signal, and a signal processing apparatus having a synchronous signal generating means for generating a synchronous signal based on the reference signal are connected by a cable. A head-separated imaging system configured, comprising: a phase difference detection unit that detects a phase difference between a synchronization signal and a reference signal in the imaging device; and a phase difference detected by the phase difference detection unit.
A first delay unit that delays the synchronization signal generated by the synchronization signal generation unit. 2. The head-separated imaging system according to claim 1, wherein said phase difference detection means and said first delay means are provided on an imaging device side. 3. The signal processing device according to claim 1, wherein said phase difference detection means and said first delay means are provided on a signal processing device side.
2. The head-separated imaging system according to 1. 4. The phase difference detecting means includes: an analog integrating means which is reset at the timing of inputting the reference signal and starts integration; and a sampling means which reads a voltage of the analog integrating means at a timing of inputting a synchronization signal. The head-separated imaging system according to any one of claims 1 to 3, further comprising: 5. The image processing apparatus further comprises: means for outputting a synchronization signal generated by the synchronization signal generation means to the imaging device; and means for inputting the output synchronization signal and feeding it back to the signal processing device. 2. The apparatus according to claim 1, wherein the phase difference detection unit detects a phase difference between a reference signal generated by the reference signal generation unit and input through the cable and a synchronization signal returned from the imaging device. A head-separated imaging system according to any one of claims 1 to 4. 6. A measuring means for measuring a time difference between the synchronizing signal output by the synchronizing signal generating means and the synchronizing signal fed back; and a delay means for delaying the output of the synchronizing signal according to the time difference measured by the measuring means. 6. The head-separated imaging system according to claim 5, further comprising two delay units. 7. The head-separated imaging system according to claim 6, wherein said second delay means delays the output of the synchronization signal in units of said reference signal. 8. The pulse signal generation means for outputting a pulse signal which rises in response to a synchronization signal output from the synchronization signal generation circuit and which falls in response to the feedback synchronization signal, and which is generated by the pulse signal generation means. 8. An analog integrating means for integrating the pulse signal during a HIGH period, wherein a delay time is controlled by a second delay means according to a voltage of the analog integrating means. Head separated type imaging system. 9. The pulse signal generating means for outputting a pulse signal which rises according to a synchronization signal output from the synchronization signal generation circuit and falls by a feedback synchronization signal, and which is generated by the pulse signal generation means. And a counting means for counting the reference signal during a period in which the pulse signal is HIGH, wherein the delay time is controlled by a second delay means according to the count number of the counting means. 8. The head separated type imaging system according to 7. 10. A measuring means for measuring a time difference between a synchronizing signal output by the synchronizing signal generating means and a synchronizing signal fed back, and a power supply voltage to be supplied to the imaging device according to the time difference measured by the measuring means. The head-separated imaging system according to any one of claims 5 to 9, further comprising a power supply voltage increasing / decreasing means for varying the power supply voltage. 11. The power supply voltage is increased when the time difference measured by the measuring means is large, and the power supply voltage is reduced when the time difference is small.
2. The head-separated imaging system according to 1. 12. The signal processing device further includes a separation unit that separates a signal input from the imaging device into a feedback synchronization signal and another signal, and wherein the synchronization signal feedback unit includes: a synchronization signal; 12. The head-separated imaging system according to claim 5, wherein another signal is multiplexed and output to a signal processing device. 13. An image pickup apparatus having reference signal generation means for generating and outputting a reference signal, and a signal processing apparatus having a synchronization signal generation means for generating a synchronization signal based on the reference signal, connected by a cable. A head-separated imaging system configured, comprising: a unit that outputs a synchronization signal generated by the synchronization signal generation unit to an imaging device; and a unit that inputs the output synchronization signal and feeds back the signal to the signal processing device. Measurement means for measuring a time difference between a synchronization signal generated by the synchronization signal generation means and a synchronization signal returned from the imaging device; and delaying output of the synchronization signal according to the time difference measured by the measurement means. And a delay unit for causing the head to separate. 14. The apparatus according to claim 13, wherein said delay means delays the output of the synchronization signal in units of said reference signal.
2. The head-separated imaging system according to 1. 15. The pulse signal generation means for outputting a pulse signal which rises by a synchronization signal output from the synchronization signal generation circuit and which falls by a feedback synchronization signal, and which is generated by the pulse signal generation means. 15. The head separation device according to claim 13, further comprising analog integration means for integrating the pulse signal during a HIGH period, wherein the delay time is controlled by the delay means according to the voltage of the analog integration means. Type imaging system. 16. The pulse signal generation means for outputting a pulse signal which rises by a synchronization signal output from the synchronization signal generation circuit and falls by a feedback synchronization signal, and which is generated by the pulse signal generation means. 15. A counting means for counting the reference signal during a period in which the pulse signal is HIGH, wherein a delay time is controlled by a delay means according to a count number of the counting means. Head separated type imaging system. 17. The apparatus according to claim 13, further comprising a power supply voltage increasing / decreasing means for varying a power supply voltage supplied to said imaging device according to a time difference measured by said measuring means. Head separated type imaging system. 18. The power supply voltage is increased when the time difference measured by the measuring means is large, and the power supply voltage is reduced when the time difference is small.
2. The head-separated imaging system according to 1. 19. The signal processing apparatus further includes a separation unit that separates a signal input from the imaging device into a feedback synchronization signal and a signal other than the synchronization signal. 19. The head-separated imaging system according to claim 13, wherein another signal is multiplexed and output to a signal processing device.