JPH11355129A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an IC incorporating a frequency dividing circuit by which an unnecessary frequency component included in an output signal where an input signal is frequency-divided into 1/n (an odd number) is easily and sufficiently reduced and its practical use is enabled even for a purpose where the radiation of the unnecessary frequency component is strictly restricted. SOLUTION: An IC is provided with the frequency dividing circuit 10 which is formed inside the IC through the use of an emitter coupling logical circuit, divides the frequency of the input signal into 1/n (the odd number) and generates a frequency dividing output signal being 1/2 in duty ratio and with an external terminal 11 for connecting a filter F, to which the frequency dividing output signal of the circuit 10 is supplied. Besides, a buffer circuit 12 inserted between the frequency dividing output node of the circuit 10 and the external terminal 11 is arranged.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a frequency dividing circuit for dividing an input signal to a frequency of 1 / n (n is an odd number). Things.

[0002]

2. Description of the Related Art Various frequency dividers for generating a low frequency output signal by dividing a sine wave or rectangular wave input signal have been realized.
By the way, recently, for example, G
It has become necessary to incorporate a circuit for dividing a high-frequency signal in the Hz band into an integrated circuit. Circuit technology different from that of a conventional general divider circuit, radiation of unnecessary frequency components included in a divided output signal ( Specific issues such as the importance of spurious countermeasures arise.

[0003] In view of such circumstances, in terms of circuit technology, an ECL (emitter coupled logic) circuit is used to increase the speed of operation, and as a measure against spurious, a high frequency cutoff characteristic connected to the outside of the integrated circuit is taken. It is conceivable to remove unnecessary frequency components of the frequency-divided output signal using a filter having

However, for example, when a three-frequency dividing circuit is formed, the input signal is frequency-divided by three using, for example, a general ring circuit as shown in FIG. 12, and the duty ratio as shown in FIG. When the output signal of No. 3 is generated, it is difficult to sufficiently reduce unnecessary frequency components included in the frequency-divided output signal, which makes practical use difficult.

[0005] This point will be specifically described below. In the divide-by-3 circuit shown in FIG. 12, CK is an input signal, RST is a reset signal, 121 is an inverter circuit,
122 and 123 are D-type flip-flop circuits;
Reference numeral 4 denotes a two-input NOR circuit.

FIG. 13 is a timing chart showing signal waveforms at main nodes when the divide-by-3 circuit of FIG. 12 operates. Here, the duty ratio of the divided output signal T3 is 1/3.
(= 33.3%).

FIG. 14 simulates the operation of a circuit prototyped using an ECL circuit to divide an input signal CK having a constant input frequency fin at about 2.5 GHz, for example, as the divide-by-3 circuit of FIG. The waveform of the frequency-divided output signal T3 at the time (the waveform of the differential voltage of the complementary frequency-divided output signal) is shown.

FIG. 15 shows a frequency versus level distribution obtained by Fourier transforming the frequency-divided output signal of FIG. here,
The vertical axis is the peak value of the signal. It can be seen from FIG.
In addition to the level of the signal component of the divided output frequency fin / 3,
2 · fin / 3 signal component, fin signal component, 4 · fin /
There are a signal component of 3, a signal component of 5 · fin / 3, a signal component of 2 · fin, and a signal component of 7 · fin / 3.
That is, a signal component of in / 3 and a signal component of 4 · fin / 3 are present at a considerable level.

FIG. 16 shows a waveform of a filter output signal when a filter circuit (not shown) having a high-frequency cutoff characteristic is connected to the output side of the divide-by-3 circuit of FIG. By connecting the filter circuit, the harmonic signal for the signal component of the divided output frequency fin / 3 is reduced,
It can be seen that the waveform of the divided output signal is a smooth sine wave.

FIG. 17 shows a frequency versus level distribution obtained by Fourier transforming the frequency-divided output signal of FIG. here,
The vertical axis is the peak value of the signal. According to FIG. 17, high-order harmonic signal components with respect to the signal component of the divided output frequency fin / 3 are removed, but the signal component of 2 · fin / 3 remains at a certain level. I understand.

[0011]

As described above, the conventional divide-by-3 circuit generates an output signal having a duty ratio of 1/3, so that unnecessary frequency components included in the divided output signal are sufficiently reduced. However, there is a problem that practical use is difficult in applications where the radiation of unnecessary frequency components is severely restricted.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and can sufficiently reduce unnecessary frequency components included in an output signal obtained by dividing an input signal to a frequency of 1 / n (n is an odd number, for example, 3). It is an object of the present invention to provide a semiconductor integrated circuit having a built-in frequency dividing circuit that can be easily reduced and can be put to practical use even in applications where the radiation of unnecessary frequency components is severely restricted.

[0013]

A semiconductor integrated circuit according to the present invention is formed by using an emitter-coupled logic circuit, divides an input signal into a frequency of 1 / n (n is an odd number), and has a duty ratio of 1 / n. A frequency divider circuit for generating a frequency-divided output signal, and an external terminal for supplying a frequency-divided output signal of the frequency divider circuit and connecting a filter.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a logic circuit diagram showing a main part of a divide-by-3 circuit according to a first embodiment of the semiconductor integrated circuit of the present invention.

In FIG. 1, reference numeral 10 is formed inside an integrated circuit, divides an input signal CK to a frequency of 1/3, and generates a frequency-divided output signal having a duty ratio of 1/2 (= 50%). It is a divide-by-3 circuit.

Reference numeral 11 denotes an external terminal to which a frequency-divided output signal of the frequency-divider circuit 10 is supplied. A filter circuit F for removing unnecessary frequency components contained in the frequency-divided output signal of the frequency-divider circuit 3 is provided. Externally connected. In this case, it is desirable to insert a buffer circuit 12 between the frequency division output node of the frequency division circuit 10 and the external terminal 11 inside the integrated circuit.

The filter circuit F has an equivalent circuit in which a capacitor C and a resistance element R2 are respectively connected in parallel to an inductor L as shown in FIG.
It has bandpass characteristics. The resistance element R1 connected in series to the inductor L indicates the internal equivalent resistance of the inductor L.

The frequency-divided output signal from which unnecessary frequency components have been removed by the filter circuit F is supplied to a desired internal circuit via, for example, an amplifier circuit (not shown) inside the integrated circuit. The frequency dividing circuit 10, the buffer circuit 12, the amplifier circuit, and the like are formed of an ECL circuit for high-speed operation.

The divide-by-3 circuit 10 includes two D-type flip-flop circuits with reset terminals (hereinafter simply referred to as FF circuits) 101 and 102, one data latch circuit 103, and two inverters. The circuit includes circuits 104 and 105 and two two-input NOR circuits 106 and 107, and is configured as described below.

Each of the FF circuits 101 and 102 is reset by receiving a reset signal RST at a reset terminal R, and receives a complementary input signal composed of the input signal CK and its inverted signal from a pair of complementary clock input terminals CK, CK. The data input terminal D receives the data input from the data input terminal D and outputs it to the data output terminal Q.

In this case, the output signal of the inverter circuit 105 is input to the data input terminal D of the first FF circuit 101, and the data input terminal D of the second FF circuit 102 is input to the data input terminal D of the first FF circuit 101. The output signal of the output terminal Q is input. The inverted signal of the input signal CK is the input signal C
K is generated by input to the inverter circuit 104.

In the present embodiment, the FF circuits 101 and 102 with reset terminals R are used for the sake of simulating the circuit operation. The reset terminal R and the reset operation may be omitted.

The first NOR circuit 106 is connected to the first FF.
The output signal of the inverted data output terminal QN of the circuit 101 and the output signal of the inverted data output terminal QN of the second FF circuit 102 are input, and the output signal of the first NOR circuit 106 is input to the first inverter circuit 104. To enter.

The data latch circuit 103 is connected to the first
The output signal of the data output terminal Q of the FF circuit 101 is input to the data input terminal D, and the complementary input signal is received by a pair of complementary clock input terminals CK and CKN. And outputs it to the inverted data output terminal QN.

The second NOR circuit 107 is connected to the first FF.
The output signal of the inverted data output terminal QN of the circuit 101 and the output signal of the inverted data output terminal QN of the data latch circuit 103 are input, and the output signal of the second NOR circuit 107 becomes the divided output signal.

FIG. 2 is a timing chart showing signal waveforms at main nodes when the divide-by-3 circuit 10 of FIG. 1 operates. This timing chart is characterized in that the duty ratio of the divided output signal OUT is 1/2 (= 50%).

According to the divide-by-3 circuit 10 configured as described above, the duty ratio of the output signal obtained by dividing the input signal to a frequency of 1/3 is 1/2. It becomes easy to sufficiently reduce unnecessary frequency components contained in the frequency-divided output signal OUT, and practical use is possible even in applications where the radiation of unnecessary frequency components is severely restricted.

FIG. 3 is a circuit diagram showing a specific example of the circuit of FIG. In FIG. 3, reference numeral 20 denotes an integrated circuit, and 30 denotes an external circuit externally connected to the external terminals 111 and 112 of the integrated circuit 20, and includes a filter circuit F.

In the integrated circuit 20, an inverter circuit block 21, a first FF circuit block 22, a second
FF circuit block 23, data latch circuit block 2
4. The NOR gate circuit block 25 forms a circuit corresponding to the divide-by-3 circuit 10 in FIG.

The inverter circuit block 21 is shown in FIG.
8 corresponds to the first inverter circuit 104 in FIG.
The circuit configuration shown in FIG. The first FF circuit block 22 includes a first NOR gate 106 shown in FIG.
, And has a circuit configuration as shown in FIG. 9A, for example.

The second FF circuit block 23 has a structure shown in FIG.
9B corresponds to the second FF circuit 102 in FIG.
The circuit configuration shown in FIG. The data latch circuit block 24 corresponds to the data latch circuit 103 in FIG. 1, and has a circuit configuration as shown in FIG. 10, for example.

The NOR gate circuit block 25 has a structure shown in FIG.
The second NOR gate 107 has a circuit configuration as shown in FIG. 11, for example. Further, the integrated circuit 2
Inside 0, a buffer circuit block 26 corresponding to the buffer circuit 12 in FIG. 1, a circuit element (bipolar transistor, resistance element) for a bias circuit and a current source, a MOS transistor for a dummy circuit, and the like are formed. Have been.

The buffer circuit block 26 comprises an ECL circuit in which a frequency-divided output signal output as a complementary signal from the NOR gate / emitter follower circuit block 25 is input to a pair of bases, and a pair of open collectors of the ECL circuit are integrated. The first external terminal 111 and the second external terminal 112 of the circuit 20 are connected.

The external circuit 30 includes a high frequency blocking inductor L1 connected between an external power supply node having a power supply voltage Vcc and the first external terminal 111, an external power supply node and the second external A filter circuit F having a high-frequency cutoff characteristic and an inductor L2 for blocking high frequency are connected between the terminal 112 and the terminal 112.

The equivalent circuit of the filter circuit F has a capacitor C and a resistance element R2 connected in parallel to an inductor L, and has a band-pass characteristic. As described above, the resistance element R1 connected in series to the inductor L indicates the internal equivalent resistance of the inductor L.

Further, the external circuit 30 is connected between the first external terminal 111 and an external power supply node and between the second external terminal 112 and the external power supply node in a forward direction. Diode D for absorbing voltage surge
1. Negative voltage surge absorbing diodes D2 connected in opposite directions between the first external terminal 111 and the external ground node and between the second external terminal 112 and the external ground node, respectively. Have been.

With the above-described configuration, the external circuit 30 supplies the power supply voltage Vcc to the pair of collectors of the ECL circuit of the buffer circuit 26, and the second external terminal 11
The filter circuit F connected to 2 has an action of removing unnecessary frequency components of the frequency-divided output signal.

FIG. 4 is a circuit diagram of FIG. 3 in which complementary input signals A and AN having a constant input frequency fin of, for example, about 2.5 GHz are inputted through a coupling capacitor to the frequency-divided-by-3 circuit in FIG. (The ECL of the buffer circuit 26)
5 shows a waveform of a difference voltage between a pair of bases of a circuit.

FIG. 5 shows a frequency versus level distribution obtained by Fourier transforming the frequency-divided output signal of FIG. Here, the vertical axis is the peak value of the signal. It can be seen from FIG. 5 that, besides the level of the signal component of the divided output frequency fin / 3, 2 · f
There are levels of a signal component of in / 3, a signal component of fin, a signal component of 4 · fin / 3, a signal component of 5 · fin / 3, and a signal component of 7 · fin / 3. 5 fin
/ 3 signal component is present at a significant level.

FIG. 6 shows a waveform of a signal at the second external terminal 112 to which the filter circuit F in FIG. 3 is connected.
By connecting the filter circuit F to the frequency-divided output signal of the frequency-divided circuit 3, the harmonic signal for the signal component of the frequency-divided output frequency fin / 3 is reduced, and the waveform of the frequency-divided output signal becomes a smooth sine wave. You can see that it is.

FIG. 7 shows a frequency versus level distribution obtained by Fourier transforming the frequency-divided output signal of FIG. Here, the vertical axis is the peak value of the signal. According to FIG. 7, it can be seen that high-order harmonic signal components with respect to the signal component of the divided output frequency fin / 3 are almost completely removed.

Next, the inverter circuit block (FIN3DIV) 21, the first FF circuit block (VDDE50) 22, and the second FF circuit block (D
FC50) 23, data latch circuit block (DLA5)
0) 24, NOR gate circuit block (OR-DIV3)
Each of the 25 will be briefly described.

The inverter circuit block (FI) shown in FIG.
N3DIV) is an NPN transistor for an inverter,
It consists of an NPN transistor for emitter follower and a resistance element, A and AN are complementary input signal terminals,
VBB is a current source bias voltage input terminal, YE and YEN are output terminals of complementary output signals output from the emitter follower, and the output signals of these output terminals YE and YEN are complementary input signals CK and CK in FIG. Used as equivalent to CKN.

The first FF circuit block (VDDE50) shown in FIG. 9A is composed of an NPN transistor for a NOR gate, an NPN transistor for an FF circuit, an NPN transistor for an emitter follower, and a resistance element. , D2 is a data input terminal, VT is a bias input voltage terminal, VBB is a current source bias voltage input terminal, C
K and CKN are complementary clock input terminals, Q and QN are complementary data output terminals, and QE and QEN are output terminals for complementary output signals output from the emitter follower.

The second FF circuit block (DFC50) shown in FIG. 9B is composed of an NPN transistor and a resistance element for the FF circuit, and D and DN are complementary data input terminals, CK and CKN. Is a complementary clock input terminal, VBB is a current source bias voltage, and Q and QN are complementary data outputs.

The data latch circuit block (DLA50) shown in FIG. 10 is composed of an NPN transistor and a resistance element. D and DN are complementary data input terminals.
CK and CKN are complementary clock input terminals, VBB is a current source bias voltage, and Q and QN are complementary data outputs.

The NOR gate circuit block (O) shown in FIG.
R-DIV3) is composed of an NPN transistor for a NOR gate, an NPN transistor for an emitter follower, and a resistance element, D and DN are complementary data input terminals, and A and AN are complementary first input signals. Terminal, B, B
N is a complementary second input signal terminal, VBB is a current source bias voltage input terminal, YE and YEN are output terminals of complementary output signals output from the emitter followers, and output signals of these output terminals YE and YEN are provided. Are used as complementary divided output signals.

It should be noted that the present invention is not limited to the three-frequency divider circuit of the above-described embodiment, but can be applied to a circuit for dividing an input signal to an odd-numbered frequency. By forming a logic circuit to generate an output signal,
Needless to say, the same effects as in the above embodiment can be obtained.

[0049]

As described above, according to the present invention, it is easy to sufficiently reduce unnecessary frequency components included in an output signal obtained by dividing an input signal to a frequency of 1 / n (n is an odd number). Further, it is possible to provide a semiconductor integrated circuit having a built-in frequency dividing circuit that can be put to practical use even in applications where the radiation of unnecessary frequency components is severely restricted.

[Brief description of the drawings]

FIG. 1 is a logic circuit diagram showing a main part of a divide-by-3 circuit according to a first embodiment of a semiconductor integrated circuit of the present invention.

FIG. 2 is a timing chart showing signal waveforms at main nodes when the divide-by-3 circuit of FIG. 1 operates.

FIG. 3 is a circuit diagram showing a specific example of the circuit in FIG. 1;

FIG. 4 is a diagram showing a waveform of a frequency-divided output signal when simulating an operation of dividing the input signal CK having a constant frequency fin at about 2.5 GHz with respect to the frequency-divided circuit of FIG.

FIG. 5 is a diagram showing a frequency versus level distribution obtained by performing a Fourier transform on the frequency-divided output signal of FIG. 4;

FIG. 6 is a diagram showing a signal waveform of a second external terminal to which the filter circuit F in FIG. 3 is connected.

FIG. 7 is a diagram illustrating a frequency versus level distribution obtained by performing a Fourier transform on the frequency-divided output signal of FIG. 6;

FIG. 8 is a circuit diagram showing an example of an inverter circuit block in FIG. 3;

FIG. 9 is a circuit diagram illustrating an example of a flip-flop circuit in FIG.

FIG. 10 is a circuit diagram showing an example of a data latch circuit in FIG. 3;

FIG. 11 is a circuit diagram showing an example of an output-side NOR gate circuit in FIG. 3;

FIG. 12 is a logic circuit diagram showing a divide-by-3 circuit having a general ring circuit configuration.

FIG. 13 is a timing chart showing signal waveforms at main nodes during the operation of the divide-by-3 circuit of FIG. 12;

14 is a waveform of a frequency-divided output signal obtained by simulating an operation of dividing an input signal CK having a constant frequency fin at about 2.5 GHz for a circuit prototyped using an ECL circuit as the frequency-divided circuit of FIG. FIG.

FIG. 15 is a diagram illustrating a frequency versus level distribution obtained by performing a Fourier transform on the frequency-divided output signal of FIG. 14;

FIG. 16 is a diagram showing a waveform of a filter output signal when a filter circuit is connected to the output side of the divide-by-3 circuit of FIG.

FIG. 17 is a diagram showing a frequency versus level distribution obtained by performing a Fourier transform on the frequency-divided output signal of FIG. 16;

[Explanation of symbols]

 10: 3 divider circuit, 101: first FF circuit, 102: second FF circuit, 103: data latch circuit, 104, 105: inverter circuit, 106, 107: two-input NOR circuit, 11: external terminal , 12: Buffer circuit, F: Filter.

Claims (3)

[Claims] An input signal is formed by using an emitter-coupled logic circuit to divide an input signal to a frequency of 1 / n (n is an odd number).
A semiconductor integrated circuit, comprising: a frequency dividing circuit for generating a frequency divided output signal having a duty ratio of 1/2; and an external terminal for supplying a frequency divided output signal of the frequency dividing circuit and connecting a filter. . 2. The semiconductor integrated circuit according to claim 1, further comprising a buffer circuit inserted between a frequency division output node of said frequency division circuit and said external terminal. 3. The semiconductor integrated circuit according to claim 1, wherein said frequency dividing circuit is a frequency dividing circuit, and receives a data input from a data input terminal by receiving an input signal at a clock input terminal to output data. A first flip-flop circuit that outputs the data to a data input terminal of the first flip-flop circuit from a data output terminal of the first flip-flop circuit to a data input terminal, and receives the input signal at a clock input terminal to input a data input of the data input terminal. A second flip-flop circuit which takes in the data and outputs it to a data output terminal; a logical sum of an output signal of an inverted data output terminal of the first flip-flop circuit and an output signal of an inverted data output terminal of the second flip-flop circuit A first logic circuit for inputting the data to a data input terminal of the first flip-flop circuit; A data latch circuit that receives an output signal of a data output terminal of a flop circuit at a data input terminal, receives the input signal at a clock input terminal, takes in a data input of the data input terminal, and outputs the data to an inverted data output terminal; A second logic circuit that performs a logical sum of an output signal of the inverted data output terminal of the first flip-flop circuit and an output signal of the inverted data output terminal of the data latch circuit, and outputs a divided output signal. A semiconductor integrated circuit characterized by the following.