JPH11354653A - Nonvolatile semiconductor memory and fabrication thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory in which a silicon substrate can be prevented against contamination, dielectric film is protected against deterioration and generation of leakage current can be prevented. SOLUTION: A memory cell transistor 60a comprises a silicon substrate 1, a floating gate 4a formed on the silicon substrate 1, an interlayer insulating film 13 having contact holes 13a, a lower electrode 6a formed to be connected electrically with the floating gate 4a, a dielectric film 7a formed on the lower electrode 6a, an upper electrode 8a formed on the dielectric film 7a, and a control gate electrode 9a formed on the upper electrode 8a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a nonvolatile semiconductor memory device using a ferroelectric film.

[0002]

2. Description of the Related Art Conventionally, as a nonvolatile semiconductor memory device,
Flash memory and EEPROM (Electrically Erasa
Non-volatile semiconductor memory devices such as a ble and programmable read only memory) are known, but in recent years, research and development of a non-volatile semiconductor memory device using a ferroelectric has been advanced.

Here, a ferroelectric substance will be described. When an electric field is externally applied to the dielectric, dielectric polarization occurs in the dielectric. However, even when the value of the externally applied electric field is set to 0, there is a dielectric in which the value of the dielectric polarization does not become 0 and takes a constant value. Such an action of dielectric polarization is called spontaneous polarization. In particular, a substance in which the direction of spontaneous polarization is reversed by the direction of an electric field applied to a dielectric is called a ferroelectric. In other words, it can be said that the ferroelectric substance maintains the polarized state without applying an electric field, and can further reverse the direction of spontaneous polarization depending on the direction in which the electric field is applied. As such ferroelectrics, for example, PZT (lead zirconate titanate) and PLZT (lead lanthanum zirconate titanate) are known.

When a ferroelectric is used as a nonvolatile semiconductor memory device, a ferroelectric film is formed on, for example, a p-type silicon substrate. An n-type source region and a drain region are formed on both sides of the ferroelectric film at a distance from each other.
A control gate electrode is formed on the ferroelectric film.

In the nonvolatile semiconductor memory device thus configured, since the lattice constant of silicon constituting the silicon substrate is different from that of the ferroelectric film, the ferroelectric film is directly formed on the silicon substrate. There is a problem that it is difficult to form a film. Further, there is a problem that mass production cannot be performed because many interface states are generated at the interface between the silicon substrate and the ferroelectric film.

In order to solve the above-mentioned problems, Japanese Patent Laid-Open No.
In Japanese Patent Application Laid-Open No. 1-108582, a nonvolatile semiconductor memory device in which an insulating layer is interposed between a silicon substrate and a ferroelectric film is proposed. In the nonvolatile semiconductor memory device described in this publication, a polysilicon film as an electrode is formed on a silicon substrate with a silicon oxide film interposed. Bismuth titanate as a ferroelectric film as an insulating layer is formed on a polysilicon film, and a gate electrode is formed on bismuth titanate.

With this configuration, it is possible to suppress the generation of the interface state between the silicon substrate and the ferroelectric film to some extent. However, since polysilicon is amorphous, it has been difficult to form a ferroelectric film on polysilicon.

When a ferroelectric film is formed on polysilicon, an oxidizing atmosphere is used, so that a silicon oxide film is formed on the surface of the polysilicon. Since the silicon oxide film is also amorphous, it has been difficult to form a ferroelectric film on the silicon oxide film.

To solve these problems, Japanese Patent Application Laid-Open No. 7-202035 discloses a nonvolatile semiconductor memory device in which a ferroelectric film is formed on a floating gate electrode made of platinum. FIG. 19 is a plan view of the nonvolatile semiconductor memory device described in the above publication, and FIG.
0 is a diagram showing a cross section viewed along line XX-XX in FIG.

Referring mainly to FIG. 19, a control gate electrode (word line) is formed on a silicon substrate so as to extend in one direction at a distance from each other. A plurality of drive lines 558 are formed at a distance from each other so as to extend in the same direction as the direction in which control gate electrode 556 extends. A plurality of bit lines 557 are formed at a distance from each other so as to extend in a direction orthogonal to the direction in which control gate electrode 556 and drive line 558 extend.

An isolation oxide film 559 is formed between a plurality of bit lines 557. An active region 561 is formed below the plurality of bit lines 557. A memory cell transistor is formed in active region 561.

A floating gate 554 is provided at a portion where bit line 557 and control gate electrode 556 intersect.
And a ferroelectric film 555 are formed.

Since the floating gate electrode 554 and the ferroelectric film 555 have an island shape, the ferroelectric film 55
The control gate electrode 556 is formed along the step at the corner 555a of No.5.

Referring mainly to FIG. 20, silicon substrate 55
1, an n-type well region 551a is formed. An isolation oxide film 559 is formed on the surface of silicon substrate 551. A source region 552a and a drain region 552b are formed on the surface of the well region 551a at a distance from each other. Source region 552a and drain region 5
A gate insulating film 553 is formed on the surface of the silicon substrate 551 between the gate insulating film 553 and the gate insulating film 553.

On the gate insulating film 553, a floating gate electrode 554 made of platinum (Pt) is formed. On the floating gate electrode 554, a ferroelectric film 555 made of PZT is formed. Ferroelectric film 55
5, a control gate electrode 556 is formed.

Drive line 558 is formed to be in contact with drain region 552b. An interlayer insulating film 561 is formed to cover control gate electrode 556 and drive line 558. On the interlayer insulating film 561, a bit line 557 extending in a direction orthogonal to the direction in which the control gate electrode 556 extends is formed. Bit line 55
7, an interlayer insulating film 560 is formed.

In the nonvolatile semiconductor memory device thus configured, the lattice constant of platinum forming the floating gate electrode 554 and the ferroelectric film 555 are close to each other. Further, the surface of the floating gate electrode 554 does not oxidize even if an oxidizing atmosphere is used when forming the ferroelectric film 555. Therefore, the ferroelectric film 555 can be formed on the surface of the floating gate electrode 554.

[0018]

However, FIG.
In a conventional nonvolatile semiconductor memory device as shown in FIG. 20, a control gate electrode 556 is formed along a corner 555a of a ferroelectric film 555. The corner 555a becomes a step, and there is a problem that an electric field is concentrated at the corner 555a to cause a leak current and a breakdown voltage is reduced.

When the floating gate electrode 554 and the ferroelectric film 555 have the same size, the corner 555a is located below the corner 555a of the ferroelectric film 555.
The non-volatile semiconductor memory device does not operate because the control gate electrode 556 and the floating gate electrode 554 formed along the line are in contact with each other.

In the above publication, FIGS.
Does not disclose any method for manufacturing a nonvolatile semiconductor memory device, but it is considered that the following process is used to manufacture this semiconductor device.

First, a well region 5 is formed on a silicon substrate 551.
51a and an isolation oxide film 559 are formed. A thermal oxide film is formed on the surface of the silicon substrate 551, and the thermal oxide film is patterned into a predetermined shape to form a gate insulating film 5.
53 is formed. Platinum film and PZ on gate insulating film 553
A ferroelectric film 5 is formed by forming a T film and patterning the PZT film and the platinum film according to a resist pattern.
55 and a floating gate electrode 554 are formed.
Using the ferroelectric film 555 as a mask, p-type impurity ions are implanted into the silicon substrate 551, and the impurity ions are thermally diffused (heat-treated) to form a source region 552a and a drain region 552b. Then drive line 55
8, a control gate electrode 556 and a bit line 557 are formed.

According to such a process, there is a problem that when the PZT film is etched to form the ferroelectric film 555, heavy metals such as lead in the PZT film scatter and contaminate the silicon substrate 551.

Further, during the heat treatment for forming the source region 552a and the drain region 552b, since the temperature of the ferroelectric film 555 also becomes high, there is a problem that the characteristics of the ferroelectric are deteriorated.

Therefore, the present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a method for manufacturing a ferroelectric film between a ferroelectric film and an electrode in contact with the ferroelectric film. It is an object of the present invention to provide a nonvolatile semiconductor memory device in which no leak current is generated and a method of manufacturing the same.

It is another object of the present invention to provide a nonvolatile semiconductor memory device in which a semiconductor substrate is not contaminated even when a ferroelectric film is formed, and a method for manufacturing the same.

Still another object of the present invention is to provide a nonvolatile semiconductor memory device in which characteristics of a ferroelectric film are not deteriorated, and a method of manufacturing the same.

[0027]

A method of manufacturing a nonvolatile semiconductor memory device according to one aspect of the present invention includes the following steps.

(1) A step of forming a floating gate electrode on a semiconductor substrate with a gate insulating film interposed.

(2) Impurity ions are implanted into the semiconductor substrate using the floating gate electrode as a mask and then heat-treated to form a pair of source and drain regions at a distance from each other on the semiconductor substrate on both sides of the floating gate electrode. Forming step.

(3) forming an interlayer insulating film covering the floating gate electrode and the semiconductor substrate on which the pair of source and drain regions are formed;

(4) A step of forming a hole reaching the floating gate electrode in the interlayer insulating film. (5) forming a first conductive film that is electrically connected to the floating gate electrode through the hole;

(6) A step of forming a ferroelectric film so as to be in contact with the first conductive film. (7) A step of forming a second conductive film so as to be in contact with the ferroelectric film.

(8) The lower electrode electrically connected to the floating gate electrode through the hole by etching the second conductive film, the ferroelectric film, and the first conductive film according to a mask having a predetermined pattern. Forming a ferroelectric film remaining in contact with the lower electrode and an upper electrode contacting the remaining ferroelectric film.

(9) A step of forming a control gate electrode electrically connected to the upper electrode.

In the method of manufacturing a nonvolatile semiconductor memory device having such steps, first, source and drain regions are formed on the surface of a semiconductor substrate. Thereafter, the semiconductor substrate on which the source and drain regions are formed is covered with an interlayer insulating film, and a lower electrode, a ferroelectric film, and an upper electrode are formed. Therefore, the ferroelectric film does not exist when forming the source and drain regions. As a result, there is no problem that the characteristics of the ferroelectric film are deteriorated by the heat treatment for forming the source and drain regions.

A method for manufacturing a nonvolatile semiconductor memory device according to another aspect of the present invention includes the following steps.

(1) A step of forming a floating gate electrode on a semiconductor substrate with a gate insulating film interposed.

(2) A step of forming an interlayer insulating film covering the semiconductor substrate and the floating gate electrode.

(3) A step of forming a hole reaching the floating gate electrode in the interlayer insulating film. (4) forming a first conductive film that is electrically connected to the floating gate electrode through the hole;

(5) A step of forming a ferroelectric film so as to be in contact with the first conductive film. (6) forming a second conductive film so as to be in contact with the ferroelectric film;

(7) By etching the second conductive film, the ferroelectric film and the first conductive film according to a mask having a predetermined pattern, the lower portion electrically connected to the floating gate electrode through the hole. Forming an electrode, a ferroelectric film remaining in contact with the lower electrode, and an upper electrode in contact with the remaining ferroelectric film.

(8) A step of forming a control gate electrode electrically connected to the upper electrode.

In the method of manufacturing a nonvolatile semiconductor memory device having such steps, first, a semiconductor substrate and a floating gate electrode formed thereon are covered with an interlayer insulating film. Thereafter, a lower electrode, a ferroelectric film, and an upper electrode are formed on the interlayer insulating film. Therefore, even if the ferroelectric film is etched, the material constituting the ferroelectric film only adheres to the surface of the interlayer insulating film and does not reach the surface of the semiconductor substrate. Therefore, the semiconductor substrate is not contaminated.

A method for manufacturing a nonvolatile semiconductor memory device according to still another aspect of the present invention includes the following steps.

(1) A step of forming a floating gate electrode on a semiconductor substrate with a gate insulating film interposed.

(2) Impurity ions are implanted into the semiconductor substrate using the floating gate electrode as a mask and then heat-treated to form a pair of source and drain regions on the semiconductor substrate on both sides of the floating gate electrode at a distance from each other. Forming step.

(3) A step of forming a first interlayer insulating film covering the floating gate electrode and the semiconductor substrate on which the pair of source and drain regions are formed.

(4) A step of forming a first hole reaching the floating gate electrode in the first interlayer insulating film.

(5) A step of forming a first conductive film electrically connected to the floating gate electrode through the first hole.

(6) A step of forming a ferroelectric film so as to be in contact with the first conductive film. (7) A step of forming a second conductive film so as to be in contact with the ferroelectric film.

(8) The second conductive film, the ferroelectric film, and the first conductive film are electrically connected to the floating gate electrode through the first hole by etching according to a mask having a predetermined pattern. Forming a lower electrode to be formed, a ferroelectric film remaining in contact with the lower electrode, and an upper electrode in contact with the remaining ferroelectric film.

(9) A step of forming a second interlayer insulating film covering the upper electrode. (10) A step of forming a second hole reaching the upper electrode in the second interlayer insulating film.

(11) A step of forming a control gate electrode electrically connected to the upper electrode through the second hole.

In the method of manufacturing a nonvolatile semiconductor memory device having such steps, the first conductive film, the ferroelectric film, and the second conductive film are etched according to the same mask, so that the remaining ferroelectric The upper electrode is formed only on the upper part of the film. For this reason, the upper electrode is not formed along the corner of the ferroelectric film, and it is possible to prevent a leak current from occurring at the corner and a decrease in breakdown voltage. Further, since the control gate electrode is also formed so as to be electrically connected to the upper electrode via the second hole, the control gate electrode is not formed along the corner of the ferroelectric film. . For this reason, it is possible to prevent the occurrence of a leak current at the corner and a decrease in the withstand voltage.

A nonvolatile semiconductor memory device according to one aspect of the present invention comprises a semiconductor substrate, a floating gate electrode, an interlayer insulating film, a lower electrode, a ferroelectric film, an upper electrode, and a control gate electrode. And

The floating gate electrode is formed on a semiconductor substrate with a gate insulating film interposed. The interlayer insulating film has a hole that covers the floating gate electrode and reaches the floating gate electrode. The lower electrode is formed on the interlayer insulating film so as to be electrically connected to the floating gate electrode through the hole. The ferroelectric film is formed so as to contact the lower electrode. The upper electrode is formed so as to be in contact with the ferroelectric film. The control gate electrode is formed to be electrically connected to the upper electrode.

In the nonvolatile semiconductor memory device having the above-described structure, the interlayer insulating film is formed by forming an interlayer insulating film covering the floating gate electrode formed on the semiconductor substrate and then forming a lower electrode on the interlayer insulating film. A step of forming a dielectric film and an upper electrode can be adopted. Therefore, even if a ferroelectric film is formed by etching, components constituting the ferroelectric film adhere to the surface of the interlayer insulating film and do not reach the silicon substrate. Therefore, there is no contamination of the semiconductor substrate. Further, in the case where an impurity region is formed on the surface of the semiconductor substrate, a step of forming the impurity region after forming the floating gate electrode and forming an interlayer insulating film covering the impurity region and the floating gate electrode can be employed. Therefore, even if a ferroelectric film is formed thereafter, the ferroelectric film does not exist when the impurity region is formed. As a result, there is no problem that the ferroelectric film is deteriorated by the heat treatment for forming the impurity region.

A nonvolatile semiconductor memory device according to another aspect of the present invention comprises a semiconductor substrate, a floating gate electrode, a lower electrode, a ferroelectric film, an upper electrode, an interlayer insulating film, a control gate electrode And

The floating gate electrode is formed on a semiconductor substrate with a gate insulating film interposed. The lower electrode is
It is formed on the floating gate electrode so as to be electrically connected to the floating gate electrode. The ferroelectric film is formed so as to contact the lower electrode. The upper electrode is formed so as to be in contact with the ferroelectric film. The interlayer insulating film has a hole covering the upper electrode and reaching the upper electrode.
The control gate electrode is formed on the interlayer insulating film so as to be electrically connected to the upper electrode via the hole.

In the nonvolatile semiconductor memory device thus configured, since the upper electrode is formed on the ferroelectric film, the upper electrode may be formed along the corner of the ferroelectric film. Absent. Further, since the control gate electrode is electrically connected to the upper electrode via the hole, the control gate electrode is not formed along the corner of the ferroelectric film. Therefore, it is possible to suppress the occurrence of a leakage current at the corner of the ferroelectric film. Further, it is possible to prevent the breakdown voltage at the corner of the ferroelectric film from being lowered.

The nonvolatile semiconductor memory device further comprises a pair of source and drain regions formed on the semiconductor substrate,
Preferably, the semiconductor device further includes a wiring layer electrically connected to the drain region.

The wiring layer may be located on the control gate electrode. Further, the wiring layer may be located below the control gate electrode.

It is preferable that the nonvolatile semiconductor memory device further includes a barrier layer formed between the floating gate electrode and the lower electrode. In this case, the barrier layer can prevent mutual diffusion of the material forming the lower electrode and the material forming the floating gate electrode.

Further, it is preferable that the floating gate electrode, the lower electrode, the ferroelectric film, and the upper electrode have substantially the same plane area. In this case, the plane area of the nonvolatile semiconductor memory device can be reduced.

[0065]

(First Embodiment) FIG. 1 is a plan view of a nonvolatile semiconductor memory device according to a first embodiment of the present invention. FIG. 2 is a sectional view taken along the line II-II in FIG. Referring to FIG. 1, source regions 2a and 2c are formed on a silicon substrate so as to extend in one direction. Isolation oxide film 2 between source regions 2a and 2c
2 are formed. The gate oxide film 3a, the floating gate electrode 4a, and the plug layer 1
2a, a barrier layer 5a, a lower electrode 6a, a ferroelectric film 7a, and an upper electrode 8a are formed by lamination. Floating gate electrode 4a, lower electrode 6a, ferroelectric film 7a, and upper electrode 8a have substantially the same plane area.

Control gate electrodes (word lines) 9a, 9b, 9c and 9d are formed at a distance from each other so as to extend in the same direction as the source regions 2a and 2c. Contact holes 14a, 14b, 14c, 14d, 114a, 11 for electrically connecting these control gate electrodes to the upper electrode.
4b, 114c and 114d are formed.

Bit lines 11a and 11b are formed to extend in a direction substantially perpendicular to the direction in which source regions 2a and 2c and control gate electrodes 9a, 9b, 9c and 9d extend. Bit lines 11a and 11b
Contact hole 16 for electrically connecting the semiconductor substrate and the silicon substrate is formed. Contact hole 14
a, 14b, 14c, 14d, 114a, 114b, 1
Non-volatile memory cell transistors 60a, 60b, 60c, and 60 are formed in portions where 14c and 114d are formed.
d, 160a, 160b, 160c and 160d are formed.

Referring to FIG. 2, source regions 2a and 2c, which are n-type impurity regions, and n-type drain regions 2b and 2d, are formed on the surface of p-type silicon substrate 1 as a semiconductor substrate. Is formed. Source regions 2a and 2c and drain regions 2b and 2d are formed apart from each other.

On the surface of silicon substrate 1, floating gate electrodes 4a, 4b and 4c made of doped polysilicon are formed with gate oxide films 3a, 3b and 3c interposed. An interlayer insulating film 13 made of a silicon oxide film is formed so as to cover silicon substrate 1 and floating gate electrodes 4a, 4b and 4c. The interlayer insulating film 13 includes a floating gate electrode 4
Contact holes 13a, 13b and 13c are formed to reach a, b and c respectively.

Contact holes 13a, 13b and 1
Plug layers 12a, 12b and 12c made of doped polysilicon are formed so as to fill 3c.
Barrier layers 5a, 5b and 5c having a two-layer structure of titanium and titanium nitride are formed on interlayer insulating film 13 so as to be electrically connected to plug layers 12a, 12b and 12c. Lower electrodes 6a, 6b and 6c made of platinum are formed on the barrier layers 5a, 5b and 5c. Ferroelectric films 7a, 7b and 7c made of PZT are formed so as to be in contact with lower electrodes 6a, 6b and 6c. The ferroelectric films 7a, 7b and 7c
May be a ferroelectric film of layered perovskite structure of PLZT or bismuth it is not limited to PZT, further Sr ₂
The Nb ₂ O ₇ family may be used.

The upper electrodes 8a and 8b made of platinum are in contact with the ferroelectric films 7a, 7b and 7c, respectively.
And 8c are formed. The materials of the lower electrodes 6a, 6b and 6c and the upper electrodes 8a, 8b and 8c include not only platinum but also ruthenium (Ru), ruthenium dioxide (RuO ₂ ), iridium (Ir), iridium oxide (IrO ₂ ) or a material thereof. A complex may be used.

The lower electrode 6a, the ferroelectric film 7a and the upper electrode 8a form a capacitor 50a, the lower electrode 6b, the ferroelectric film 7b and the upper electrode 8b form a capacitor 50b, and the lower electrode 6c The dielectric film 7c and the upper electrode 8c form a capacitor 50c.

Capacitors 50a, 105b and 50c
Is formed to cover the substrate. In the interlayer insulating film 14, contact holes 14a, 14b and 14c reaching the upper electrodes 8a, 8b and 8c are formed. Control gate electrodes 9a, 9b and 9c made of tungsten are formed so as to fill contact holes 14a, 14b and 14c and electrically connect to upper electrodes 8a, 8b and 8c, respectively. Control gate electrodes 9a, 9b and 9
An interlayer insulating film 15 is formed so as to cover c.

A contact hole 16 reaching drain region 2b is formed in interlayer insulating films 13, 14, and 15. A barrier layer 10 made of titanium nitride is formed on the bottom of the contact hole 16 and the top of the interlayer insulating film 15. The contact hole 16 is filled and electrically connected to the drain region 2b, and the interlayer insulating film 15
A bit line 11a as a wiring layer made of aluminum is formed so as to cover.

A pair of source region 2a and drain region 2b, floating gate electrode 4a, plug layer 1
2a, barrier layer 5a, capacitor 50a, and control gate electrode 9a
a.

A pair of source region 2c and drain region 2b, floating gate electrode 4b, plug layer 1
2b, barrier layer 5b, capacitor 50b, and control gate electrode 9b
b.

A pair of source region 2c and drain region 2d, floating gate electrode 4c, plug layer 1
2c, barrier layer 5c, capacitor 50c, and control gate electrode 9c
Construct c.

FIG. 3 is a sectional view taken along the line III-III in FIG. Referring to FIG. 3, silicon substrate 1
A plurality of isolation oxide films 22 are formed on the surface of the substrate at a distance from each other. The region surrounded by isolation oxide film 22 is the active region, and floating gate electrodes 4a and 10 made of doped polysilicon are provided on the surface of silicon substrate 1 in the active region with gate oxide films 3a and 103a interposed therebetween.
4a are formed. Floating gate electrode 4a
And 104a, an interlayer insulating film 13 is formed. A contact hole 13a reaching the floating gate electrodes 4a and 104a is formed in the interlayer insulating film 13.
And 113a are formed.

Plug layers 12a and 112a of doped polysilicon are formed to fill contact holes 13a and 113a. Plug layer 12
a and a barrier layer 5 having a two-layer structure of titanium nitride on interlayer insulating film 13 so as to be in contact with 112a.
a and 105a are formed.

The lower electrodes 6a and 106a made of platinum are formed on the barrier layers 5a and 105a. Ferroelectric films 7a and 107a made of PZT are formed on lower electrodes 6a and 106a so as to be in contact therewith. Upper electrodes 8a and 108a made of platinum are formed on and in contact with the ferroelectric films 7a and 107a. End 7 of ferroelectric films 7a and 107a
7a and 177a along with the upper electrodes 8a and 108
a is not formed. The lower electrode 106a, the ferroelectric film 107a, and the upper electrode 108a
a.

An interlayer insulating film 14 is formed so as to cover capacitors 50a and 150a. Interlayer insulating film 14
Are formed with contact holes 14a and 114a reaching the upper electrodes 8a and 108a. Fill the contact holes 14a and 114a to form the upper electrode 8
A control gate electrode 9a is formed on interlayer insulating film 15 so as to connect to a and a. An interlayer insulating film 15 is formed on control gate electrode 9a, and bit lines 11a and 11b made of aluminum are formed on interlayer insulating film 15. A pair of source and drain regions (not shown in FIG. 3), floating gate electrode 104a, and plug layer 112a
, Barrier layer 105a, capacitor 150a, and control gate electrode 9a are connected to memory cell transistor 1
60a.

Next, the operation of the nonvolatile semiconductor memory device (memory cell transistor 60a) shown in FIGS. 1 to 3 will be described. First, the write operation will be described.
As potentials corresponding to the state of “1”, the potential of the control gate electrode 9a is set to H, and the potential of the bit line 11a is set to L
(Potential lower than H). Thereby, the upper electrode 8
The portion of the ferroelectric film 7a in contact with a is negatively charged, and the portion of the ferroelectric film 7a in contact with the lower electrode 6a is positively charged.
Therefore, the portion of the silicon substrate 1 below the floating gate electrode 4a is negatively charged (inverted to n-type), and a current flows between the source region 2a and the drain region 2b.

The potential of the control gate electrode 9a is set to L and the potential of the bit line 11a is set to H as the potential corresponding to the state of "0". In this case, the portion of the ferroelectric film 7a in contact with the upper electrode 8a is positively charged, and the lower electrode 6a
The portion of the ferroelectric film 7a in contact with is charged negatively. Therefore, the portion of the silicon substrate 1 below the floating gate electrode 4a is positively charged (not inverted to n-type) and the source region 2
No current flows between a and the drain region 2b.

Since the ferroelectric film 7a remains polarized even when the potentials of the control gate electrode 9a and the bit line 11a are set to 0, once the state is "1" or "0", the control gate electrode 9a Even if the potential of bit line 11a is set to 0, the state of "1" or "0" is maintained.

Next, the erasing operation will be described. When the above-mentioned “1” state is set to the erase state, the potential of the control gate electrode is set to H so that all the memory cell transistors in the “0” state are set to the “1” state, and the bit line Is set to L and erased collectively. The unselected control gate electrode is left floating to reduce disturbance in the unselected memory cell transistor. If the selection transistor is provided between the memory cell transistor and the control gate electrode to provide two transistors, the problem of disturbance can be solved.
The cell area increases.

Next, reading will be described. Bit line 1
The potential of 1a is set to 0V, and a small potential is applied to the source region 2a so as not to affect the ferroelectric film 7a. By changing this potential, it is determined from the amount of current flowing through the transistor whether it is “0” or “1”, and a read operation is performed. When the source region 2a is shared by all the memory cell transistors, the potential of the bit line 11a is changed. At this time, in order to prevent a current from flowing from an unselected memory cell transistor, for example, the transistor is set to a p-type
It is necessary to fix the potential of the control gate electrode to 0 V as an SFET.

In the nonvolatile semiconductor memory device thus configured, first, as shown in FIG. 3, upper electrodes 8a and 108a are formed along corners 77a and 177a of ferroelectric films 7a and 107a. Never. Further, since control gate electrode 9a is also formed on upper electrodes 8a and 108a via contact holes 14a and 114a, 77a and 17a are formed at corners.
Control gate electrode 9a is not formed along 7a. Therefore, the corners 77a and 177a
No electric field concentration occurs and no leak current occurs. In addition, it is possible to prevent the withstand voltage of the corners 77a and 177a from being reduced.

Next, a method of manufacturing the nonvolatile semiconductor memory device shown in FIGS. 1 to 3 will be described. FIG. 4 to FIG.
FIG. 3 is a cross-sectional view showing a manufacturing process of one nonvolatile semiconductor memory device (memory cell transistor 60a) shown in FIG.
FIG. 11 is a diagram showing a cross section viewed along line XI-XI in FIG.

Referring to FIG. 4, a thermal oxide film is formed on p-type silicon substrate 1 by a thermal oxidation method. On the thermal oxide film, doped polysilicon is deposited by a CVD (Chemical Vapor Deposition) method. A floating gate electrode 4a and a gate oxide film 3a are formed by forming a resist pattern on the doped polysilicon and etching the doped polysilicon and the thermal oxide film according to the resist pattern. Using floating gate electrode 4a as a mask, source region 2a and drain region 2b are formed by performing a heat treatment after ion implantation of, for example, phosphorus into silicon substrate 1. A silicon oxide film is formed by a CVD method so as to cover the floating gate electrode 4a, and the silicon oxide film is entirely etched back to form a sidewall oxide film 49. In addition,
This sidewall oxide film 49 is shown in other figures (FIGS. 2, 3, and 5).
11 to 11) are not shown.

Referring to FIG. 5, a CV
An interlayer insulating film 13 made of a silicon oxide film is formed by the method D. After the formation of the interlayer insulating film 13, the surface of the interlayer insulating film 13 may be planarized. It is conceivable to use CMP (Chemical Mechanical Polishing) as a flattening method.

By forming a resist pattern on interlayer insulating film 13 and etching interlayer insulating film 13 in accordance with the resist pattern, floating gate electrode 4 is formed.
Is formed.

Referring to FIG. 6, contact hole 13a
And CV so as to cover the surface of the interlayer insulating film 13.
A doped polysilicon is deposited by the D method. By etching back this doped polysilicon,
The plug layer 12a is formed in the contact hole 13a. Referring to FIG. 7, a composite layer 31 made of titanium and titanium nitride is formed on interlayer insulating film 13 by a sputtering method. A platinum layer 32 is formed on the composite layer 31 by a sputtering method. A PZT layer 33 is formed on the platinum layer 32 by a sputtering method. The platinum layer 32 is formed on the PZT layer 33 by a sputtering method. Thereafter, RTA (Rapid Thermal) is used to crystallize the PZT layer 33.
Anneal).

Referring to FIG. 8, a resist pattern is formed on platinum layer 34, and platinum layer 34, PZT layer 33, platinum layer 32 and composite layer 31 are formed in accordance with the resist pattern.
Is etched to form an upper electrode 8a, a ferroelectric film 7a, a lower electrode 6a, and a barrier layer 5a.

Referring to FIG. 9, interlayer insulating film 1 made of a silicon oxide film is formed by CVD so as to cover upper electrode 8a.
4 is formed. Resist pattern 4 on interlayer insulating film 14
0 is formed, and the interlayer insulating film 14 is etched in accordance with the resist pattern 40 to form a contact hole 14a reaching the upper electrode 8a.

Referring to FIGS. 10 and 11, a tungsten layer is formed by a CVD method so as to fill contact hole 14a and cover the surface of interlayer insulating film 14. A resist pattern 41 is formed on the tungsten layer,
The control gate electrode 9a is formed by etching the tungsten layer according to the resist pattern 41.

Referring to FIG. 2, an interlayer insulating film 15 made of a silicon oxide film is formed by a CVD method so as to cover control gate electrode 9a. A resist pattern is formed on interlayer insulating film 15 and contact hole 16 is formed by etching interlayer insulating film 15 in accordance with the resist pattern. The barrier layer 10 made of titanium nitride is formed on the bottom surface of the contact hole 16 and the surface of the interlayer insulating film 15 by a sputtering method. A bit line 16 made of aluminum is formed by a sputtering method so as to cover the barrier layer 10 and fill the contact hole 16, thereby completing the memory cell transistor 60a.

In the non-volatile semiconductor memory device manufactured according to such a manufacturing process, first, a heat treatment is performed when forming source region 2a and drain region 2b in the process shown in FIG. No ferroelectric film is formed. Therefore, the ferroelectric film does not deteriorate due to the heat treatment.

In the step shown in FIG. 8, the PZT layer 33 is etched to form the ferroelectric film 7a. At this time, since the surface of the silicon substrate 1 is covered with the interlayer insulating film 13, even if lead or zirconium constituting the PZT layer 32 scatters, the lead or zirconium does not reach the surface of the silicon substrate 1. There is no. Therefore, contamination of the silicon substrate 1 can be prevented.

As shown in FIG. 8, the upper electrode 8a, the ferroelectric film 7a, the lower electrode 6a, and the barrier layer 5a having the same flat area are formed in one step.
There is no step at the interface between a and the upper electrode 8a. That is, the upper electrode 8a is not formed along the corner of the ferroelectric film 7a. In addition, the cell area of the memory cell transistor 60a can be reduced, and the upper electrode 8a, the ferroelectric film 7a, the lower electrode 6, and the barrier
Can be formed.

(Second Embodiment) FIG. 12 is a plan view of a nonvolatile semiconductor memory device according to a second embodiment of the present invention. Referring to FIG. 12, source regions 202a, 202c and 202e are formed on a silicon substrate so as to extend in one direction. A plurality of source regions 202a, 20
An isolation oxide film 222 is formed between 2c and 202e. Source regions 202a, 202c and 202e
Bit lines 211 in a direction orthogonal to the direction in which
a, 211b and 211c are formed. The bit lines 211a, 211b and 211c are connected to contact holes 213a, 213b, 313a and 313, respectively.
b, 413a and 413b are electrically connected to the silicon substrate.

Bit lines 211a, 211b and 211
a plurality of control gate electrodes (word lines) spaced apart from each other so as to extend in a direction perpendicular to the direction in which c extends
209a, 209b, 209c and 209d are formed. The floating gate electrode 204a is formed in a portion surrounded by oblique lines at the upper right end in FIG. The floating gate electrode 204a is electrically connected to a lower electrode (not shown in FIG. 12) through a contact hole 214a.

Note that the other floating gate electrode and lower electrode also have contact holes 214b and 214, respectively.
c, 214d, 314a, 314b, 314c, 314
d, 414a, 414b, 414c and 414d.

In the region where the control gate electrode 209b is provided, the barrier layer 205
b, a lower electrode 206b, a dielectric film 207b, and an upper electrode 208b. Barrier layer 205a, lower electrode 206b, ferroelectric film 207b, and upper electrode 208b
Have almost the same plane area. The other areas have the same plane area.

The control gate electrode 209b and the upper electrode 208b are electrically connected by a contact hole 215b. In other parts, control gate electrodes 209a, 209b, 209c and 209
d and the upper electrode are in contact holes 215a, 215
c, 215d, 315a, 315b, 315c, 315
d, 415a, 415b, 415c, and 415d. In the regions where these contact holes are formed, the nonvolatile memory cell transistors 260a, 260b, 260c, 260d, 360a,
360b, 360c, 360d, 460a, 460b,
460c and 460d are formed.

FIG. 13 is a sectional view taken along the line XIII-XIII in FIG.
It is sectional drawing seen along the line. Referring to FIG. 13, source regions 202a and 202, which are n-type impurity regions, are provided on a surface portion of a p-type silicon substrate 201 as a semiconductor substrate.
c and 202e and drain regions 202b and 202
d are formed at a distance from each other.

Floating gate electrodes 204a, 204b, 204a, 204b, 203c, and 203d are interposed on the surface of silicon substrate 201a.
204c and 204d are formed. Floating gate electrodes 204a, 204b, 204c and 2
An interlayer insulating film 213 is formed so as to cover 04d. Contact holes 213a and 213 reaching drain regions 202b and 202d are formed in interlayer insulating film 213.
13b is formed. Bit lines 211a and 211b as wiring layers made of polycide are formed on interlayer insulating film 213 so as to fill contact holes 213a and 213b and electrically connect to drain regions.

An interlayer insulating film 214 is formed on the interlayer insulating film 213. In the interlayer insulating films 214 and 213,
Floating gate electrodes 204a, 204b, 204
c and contact holes 214a reaching 204d,
214b, 214c and 214d are formed.
Plug layers 212a, 212b, 212c and 212 made of doped polysilicon to fill contact holes 214a, 214b, 214c and 214d.
d is formed.

The barrier layer 205 having a two-layer structure of titanium and titanium nitride is formed on the interlayer insulating film 214 so as to be in contact with the plug layers 212a, 212b, 212c and 212d.
a, 205b, 205c, and 205d are formed, and the lower electrodes 206a, 206b, 206c, and 206d made of platinum and the ferroelectric films 207a, 207b, 207c, and 20 made of PZT are stacked thereon.
7d and upper electrodes 208a, 208b, 2 made of platinum.
08c and 208d are formed.

Lower electrode layer 206a, ferroelectric film 207
a, the upper electrode 208a constitutes the capacitor 250a,
Similarly, the other lower electrodes 206b to 206d, the ferroelectric film 2
07b to 207d and upper electrodes 208b to 208d also form capacitors 250b, 250c and 250d.

Capacitors 250a, 250b, 250c
And an interlayer insulating film 215 made of a silicon oxide film so as to cover 250d. The upper electrodes 208a, 208b, 208c and 208 are provided on the interlayer insulating film 215.
d, contact holes 215a, 215b, 21
5c and 215d are formed.

Contact holes 215a, 215b, 2
A barrier layer 210 made of titanium nitride is formed on the bottom surfaces of the layers 15c and 215d and on the surface of the interlayer insulating film 215. Contact holes 215a, 215b, 21
5c and 215d to fill the interlayer insulating film 215
Control gate electrode 20 made of tungsten on top
9a, 209b, 209c and 209d are formed.

A pair of source region 202a and drain region 202b, floating gate 204a, plug layer 212a, barrier layer 205a, and capacitor 2
50a and control gate electrode 209a form memory cell transistor 260a.

A pair of source region 202c and drain region 202b and floating gate electrode 204b
, Plug layer 212b, barrier layer 205b, capacitor 250b, and control gate electrode 209b constitute memory cell transistor 260b.

A pair of source region 202c and drain region 202d and floating gate electrode 204c
, Plug layer 212c, barrier layer 205c, capacitor 250c, and control gate electrode 209c constitute memory cell transistor 260c.

A pair of source region 202e and drain region 202d and floating gate electrode 204d
, Plug layer 212d, barrier layer 205d, capacitor 250d, and control gate electrode 209d constitute memory cell transistor 260d.

FIG. 14 is a diagram showing a cross section viewed along line XIV-XIV in FIG. Referring to FIG. 14, isolation oxide films 222 are formed on the surface of silicon substrate 201 at a distance from each other. Floating gate electrodes 204a and 304a are formed between isolation oxide films 222 with gate oxide films 203 and 303 interposed. Floating gate electrodes 204a and 304
a interlayer insulating film 21 made of a silicon oxide film so as to cover
3 are formed.

The bit line 21 is formed on the surface of the interlayer insulating film 213.
1a and 211b are formed. Bit line 211
An interlayer insulating film 214 made of a silicon oxide film is formed on interlayer insulating film 213 so as to cover a and 211b. In the interlayer insulating films 214 and 213, contact holes 214a and 314a reaching the floating gate electrodes 204a and 304a are formed. Plug layers 212a and 312a made of doped polysilicon are formed to fill contact holes 214a and 314a.

Barrier layers 205a and 305a having a two-layer structure of titanium and titanium nitride are formed on interlayer insulating film 214 so as to be in contact with plug layers 212a and 312a. On the barrier layers 205a and 305a, upper electrodes 206a and 306a made of platinum and PZT
Ferroelectric films 207a and 307a made of and upper electrodes 208a and 308a made of platinum are laminated. The lower electrode 306a, the ferroelectric film 307a, and the upper electrode 308a form a capacitor 350a.

An interlayer insulating film 215 made of a silicon oxide film is formed on interlayer insulating film 214 so as to cover capacitors 250a and 350a. In the interlayer insulating film 215, contact holes 215a and 315a reaching the upper electrodes 208a and 308a are formed. A barrier layer 210 made of titanium nitride is formed on the bottom surfaces of the contact holes 215a and 315a and on the surface of the interlayer insulating film 215. Contact hole 215a
Control gate electrode 209a made of tungsten on interlayer insulating film 215 so as to fill
Are formed.

In the nonvolatile semiconductor memory device thus configured, upper electrodes 208a and 308a are formed along corners 277a and 377a of ferroelectric films 207a and 307a, as shown in FIG. It will not be done. Further, since control gate electrode 209a also contacts upper electrode 208a via contact holes 215a and 315a and barrier layer 210, control gate electrode 209a is not formed along corners 277a and 377a. Therefore, it is possible to prevent the occurrence of a leak current at the corners 277a and 377a. Further, it is possible to prevent the breakdown voltage at the corners 277a and 377a from being reduced.

Next, a method of manufacturing the nonvolatile semiconductor memory device shown in FIGS. 12 to 14 will be described. 15 to 1
FIG. 8 is a cross-sectional view showing a manufacturing step of one nonvolatile semiconductor memory device (memory cell transistor 260) shown in FIG. Referring to FIG. 15, a thermal oxide film is formed on a p-type silicon substrate 201, and doped polysilicon is formed on the thermal oxide film by a CVD method. A resist pattern is formed on the doped polysilicon, and the doped polysilicon and the thermal oxide film are etched according to the resist pattern to form a gate oxide film 203a and a floating gate electrode 204a.

Using the floating gate electrode 204a as a mask, an n
A source region 202a and a drain region 202b are formed by implanting impurity ions of a mold and performing a heat treatment. Thereafter, a silicon oxide film is formed by a CVD method so as to cover the floating gate electrode 204a, and the silicon oxide film is entirely etched back to form a sidewall oxide film (not shown) on the side wall of the floating gate electrode 204a.

An interlayer insulating film 213 made of a silicon oxide film is formed by a CVD method so as to cover floating gate electrode 204a. By forming a resist pattern on the interlayer insulating film 213 and etching the interlayer insulating film 213 according to the resist pattern, the drain region 2 is formed.
A contact hole 213a reaching 02b is formed.
A polycide 240 is formed by a CVD method and a sputtering method so as to fill the contact hole 213a.

Referring to FIG. 16, a resist pattern is formed on polycide 240, and bit line 211a is formed by etching polycide 240 in accordance with the resist pattern. An interlayer insulating film 214 made of a silicon oxide film is formed on the interlayer insulating film 213 by a CVD method so as to cover the bit line 211a. Interlayer insulating film 2
A resist pattern 340 is formed on 14. According to resist pattern 340, interlayer insulating films 214 and 213
Is etched to form a contact hole 214a reaching the floating gate electrode 204a.

Referring to FIG. 17, contact hole 21
4a and cover the interlayer insulating film 214 by CVD.
A doped polysilicon is formed by a method. By etching back the entire surface of the doped polysilicon, a plug layer 212a filling the contact hole 214a is formed.

Referring to FIG. 18, a composite layer made of titanium and titanium nitride is formed on interlayer insulating film 214 by a sputtering method. A platinum layer is formed on the composite layer by a sputtering method. A PZT layer is formed on the platinum layer by a sputtering method. A platinum layer is formed on the PZT layer by a sputtering method. RTA is performed to crystallize the PZT layer. A resist pattern is formed on the platinum layer, and the platinum layer, the PZT layer, the platinum layer, and the composite layer are etched according to the resist pattern to form the upper electrode 208a, the ferroelectric film 207a, the lower electrode 206a, and the barrier layer 205a. Form.

Referring to FIG. 13, an interlayer insulating film 215 made of a silicon oxide film is formed by CVD so as to cover upper electrode 208a. A resist pattern is formed on interlayer insulating film 215, and interlayer insulating film 215 is etched in accordance with the resist pattern to form upper electrode 20.
A contact hole 215a reaching 8a is formed. A barrier layer 210 made of titanium nitride is formed on the bottom surface of the contact hole 215a and the surface of the interlayer insulating film 215a by a sputtering method.

Tungsten is formed by the CVD method so as to fill the contact hole 215a, and a resist pattern is formed on the tungsten. The control gate electrode 209a is formed by etching tungsten according to the resist pattern, and the memory cell transistor 260a is completed.

In the memory cell transistor manufactured by such a process, first, in the process shown in FIG. 15, heat treatment is performed when forming source region 202a and drain region 202b. No body membrane is formed. Therefore, the ferroelectric film does not deteriorate due to heat during the heat treatment. FIG.
As shown in the figure, when the PZT film is etched to form a ferroelectric film, the silicon substrate 201 is
And 214. Therefore, contamination of the silicon substrate 201 can be prevented without lead and the like constituting the PZT film reaching the surface of the silicon substrate 201 during etching.

Further, as shown in FIG.
Since the lower electrode 5a, the lower electrode 206a, the ferroelectric film 207a, and the upper electrode 208a are manufactured in one process, no step is formed at the interface between the ferroelectric film 207a, the upper portion, and the electrode 208a. That is, the upper electrode 208a is
It is not formed along the corner of 07a. Further, the cell area of the memory cell transistor 260a can be reduced, and the upper electrode 208a, the ferroelectric film 207a, the lower electrode 206a, and the barrier layer 20 can be formed with one mask.
5a can be formed.

The method for manufacturing the nonvolatile semiconductor memory device shown in the first and second embodiments also has the following effects. That is, the step of forming the source region 2a, the drain region 2b, the gate oxide film 3a, and the floating gate electrode 4a shown in FIG. 4 of the first embodiment and the step of forming the source region 2a and the drain region 2b shown in FIG. And a gate oxide film 203a and a floating gate electrode 204a, a transistor including a source and drain region, a gate oxide film and a gate electrode may be formed in a peripheral circuit.

Here, the process of manufacturing a ferroelectric film is different from the process of manufacturing a transistor of a peripheral circuit. Therefore, as in the conventional case, a process of continuously manufacturing a floating gate electrode and a ferroelectric film is performed. When the process is adopted, the transistor manufacturing process of the peripheral circuit
The conditions of the manufacturing process of the ferroelectric film are restricted. However, in the present invention, the floating gate electrode 20
Since the gate electrode of the transistor 4a and the peripheral circuit can also be covered with the interlayer insulating film 213, the process for manufacturing the ferroelectric film is not restricted by the process conditions.

Although the process for manufacturing a ferroelectric film is different from the process for manufacturing a peripheral circuit, since the ferroelectric film is formed after the peripheral circuit is covered with the interlayer insulating film 213, the process is easy. A ferroelectric film can be manufactured. Therefore, the versatility of the process is improved.

Further, in a nonvolatile semiconductor memory device, a bit line may be divided into a main bit line and a sub bit line as a measure against disturbance. In such a case, the bit lines 11a, 11b, 211a, 211b and 211
It is also possible for c to be either a main bit line or a sub-bit line.

Although the embodiment of the present invention has been described above, the embodiment shown here can be variously modified. First, the material of the control gate electrode and the bit line can be changed as needed. Further, as a material forming the ferroelectric film, not only PZT but also PLZT can be used.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0137]

According to the first, second and fourth aspects of the present invention, it is possible to provide a nonvolatile semiconductor memory device in which the surface of the semiconductor substrate is not contaminated and the ferroelectric film is not deteriorated.

According to the third and fifth aspects of the present invention,
It is possible to provide a nonvolatile semiconductor memory device capable of suppressing generation of a leak current at a corner of a ferroelectric film.

According to the present invention, a nonvolatile semiconductor memory device having another wiring layer can be provided.

According to the ninth aspect of the present invention, it is possible to provide a nonvolatile semiconductor memory device capable of suppressing the diffusion of the material forming the floating gate electrode and the material forming the lower electrode.

According to the tenth aspect of the present invention, a nonvolatile semiconductor memory device having a small plane area can be provided.

[Brief description of the drawings]

FIG. 1 is a plan view of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a view showing a cross section viewed along the line II-II in FIG. 1;

FIG. 3 is a diagram showing a cross section viewed along line III-III in FIG. 1;

FIG. 4 is a cross-sectional view showing a first step of the method for manufacturing one memory cell transistor shown in FIG. 2;

FIG. 5 is a sectional view showing a second step of the method for manufacturing one memory cell transistor shown in FIG. 2;

FIG. 6 is a cross-sectional view showing a third step of the method for manufacturing one memory cell transistor shown in FIG. 2;

FIG. 7 is a sectional view showing a fourth step of the method for manufacturing one memory cell transistor shown in FIG. 2;

FIG. 8 is a sectional view showing a fifth step of the method for manufacturing one memory cell transistor shown in FIG. 2;

FIG. 9 is a cross-sectional view showing a sixth step of the method for manufacturing one memory cell transistor shown in FIG. 2;

FIG. 10 is a sectional view showing a seventh step of the method for manufacturing one memory cell transistor shown in FIG. 2;

FIG. 11 is a diagram showing a cross section viewed along line XI-XI in FIG. 10;

FIG. 12 is a plan view of a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

FIG. 13 is a view showing a cross section viewed along line XIII-XIII in FIG. 12;

FIG. 14 is a diagram showing a cross section viewed along line XIV-XIV in FIG. 12;

15 is a cross-sectional view showing a first step of the method for manufacturing one memory cell transistor shown in FIG.

16 is a cross-sectional view showing a second step of the method for manufacturing one memory cell transistor shown in FIG.

17 is a cross-sectional view showing a third step of the method for manufacturing one memory cell transistor shown in FIG.

18 is a cross-sectional view showing a fourth step of the method for manufacturing one memory cell transistor shown in FIG.

FIG. 19 is a plan view of a conventional nonvolatile semiconductor memory device.

20 is a diagram showing a cross-sectional view taken along line XX-XX in FIG.

[Explanation of symbols]

1,201 silicon substrate, 3a, 3b, 3c, 203
a, 203b, 203c, 203d Gate oxide film, 4
a, 4b, 4c, 104a, 204a, 204b, 20
4c, 204d, 304a Floating gate electrode, 6a, 6b, 6c, 106a, 206a, 206
b, 206c, 206d, 306a Lower electrode, 7a,
7b, 7c, 107a, 207a, 207b, 207
c, 207d, 307a Ferroelectric film, 8a, 8b, 8
c, 108a, 208a, 208b, 208c, 208
d, 308a Upper electrode, 9a, 9b, 9c, 109
a, 209a, 209b, 209c, 209d, 309
a Control gate electrode, 60a, 60b, 60
c, 160a, 260a, 260b, 260c, 260
d, 360a Memory cell transistor.

Claims (10)

[Claims] A step of forming a floating gate electrode on a semiconductor substrate with a gate insulating film interposed therebetween; and implanting impurity ions into the semiconductor substrate using the floating gate electrode as a mask, followed by a heat treatment to form the floating gate. Forming a pair of source and drain regions on a portion of the semiconductor substrate on both sides of an electrode at a distance from each other; and forming the floating gate electrode and the semiconductor substrate on which the pair of source and drain regions are formed. Forming a covering interlayer insulating film; forming a hole reaching the floating gate electrode in the interlayer insulating film; forming a first conductive film electrically connected to the floating gate electrode through the hole. Forming a ferroelectric film so as to be in contact with the first conductive film Forming a second conductive film so as to be in contact with the ferroelectric film; and masking the second conductive film, the ferroelectric film, and the first conductive film with a predetermined pattern. A lower electrode electrically connected to the floating gate electrode through the hole, the ferroelectric film remaining so as to be in contact with the lower electrode, and the remaining ferroelectric A method for manufacturing a nonvolatile semiconductor memory device, comprising: a step of forming an upper electrode in contact with a film; and a step of forming a control gate electrode electrically connected to the upper electrode. A step of forming a floating gate electrode on the semiconductor substrate with a gate insulating film interposed therebetween; a step of forming an interlayer insulating film covering the semiconductor substrate and the floating gate electrode; Forming a hole that reaches the interlayer insulating film, forming a first conductive film that is electrically connected to the floating gate electrode through the hole, and contacting the first conductive film. Forming a ferroelectric film, forming a second conductive film so as to be in contact with the ferroelectric film, forming the second conductive film, the ferroelectric film, and the first conductive film Contacting the lower electrode with the lower electrode electrically connected to the floating gate electrode through the hole by etching according to a mask having a predetermined pattern; Forming a remaining ferroelectric film and an upper electrode in contact with the remaining ferroelectric film, and forming a control gate electrode electrically connected to the upper electrode. A method for manufacturing a nonvolatile semiconductor memory device, comprising: Forming a floating gate electrode on a semiconductor substrate with a gate insulating film interposed therebetween; and implanting impurity ions into the semiconductor substrate using the floating gate electrode as a mask, followed by heat treatment to form the floating gate. Forming a pair of source and drain regions on a portion of the semiconductor substrate on both sides of an electrode at a distance from each other; and forming the floating gate electrode and the semiconductor substrate on which the pair of source and drain regions are formed. Forming a first interlayer insulating film to cover; forming a first hole reaching the floating gate electrode in the first interlayer insulating film; forming a first hole through the first hole in the floating gate electrode. Forming a first conductive film to be electrically connected; and contacting the first conductive film on the first conductive film. Forming a second conductive film so as to be in contact with the ferroelectric film; and forming the second conductive film, the ferroelectric film, and the first conductive film on the ferroelectric film. Is etched according to a mask having a predetermined pattern, thereby forming a lower electrode electrically connected to the floating gate electrode through the first hole, and the lower electrode remaining in contact with the lower electrode. Forming a dielectric film and an upper electrode in contact with the remaining ferroelectric film; forming a second interlayer insulating film covering the upper electrode; and a second reaching the upper electrode. Forming a hole in the second interlayer insulating film; and forming a control gate electrode electrically connected to the upper electrode through the second hole.
A method for manufacturing a nonvolatile semiconductor memory device. 4. A semiconductor substrate; a floating gate electrode formed on the semiconductor substrate with a gate insulating film interposed therebetween; A pair of source and drain regions, an interlayer insulating film covering the floating gate electrode and having a hole reaching the floating gate electrode, and the interlayer insulating film electrically connected to the floating gate electrode through the hole. A lower electrode formed on the film, a ferroelectric film formed to be in contact with the lower electrode, an upper electrode formed to be in contact with the ferroelectric film, and A nonvolatile semiconductor memory device comprising: a control gate electrode formed so as to be electrically connected. 5. A semiconductor substrate; a floating gate electrode formed on the semiconductor substrate with a gate insulating film interposed therebetween; A pair of source and drain regions, a first interlayer insulating film covering the floating gate electrode and having a first hole reaching the floating gate electrode, and electrically connecting to the floating gate electrode through the first hole. A lower electrode formed on the first interlayer insulating film so as to be connected to the first interlayer insulating film; a ferroelectric film formed to be in contact with the lower electrode; and a ferroelectric film in contact with the ferroelectric film. An upper electrode formed on the first electrode, a second interlayer insulating film covering the upper electrode and having a second hole reaching the upper electrode, and an upper electrode through the second hole. And a second control gate electrode formed on the interlayer insulating film so as to be electrically connected to the electrode, the non-volatile semiconductor memory device. 6. The nonvolatile semiconductor memory device according to claim 4, further comprising a wiring layer electrically connected to said drain region. 7. The nonvolatile semiconductor memory device according to claim 6, wherein said wiring layer is located above said control gate electrode. 8. The nonvolatile semiconductor memory device according to claim 6, wherein said wiring layer is located below said control gate electrode. 9. The nonvolatile semiconductor memory device according to claim 4, further comprising a barrier layer formed between said floating gate electrode and said lower electrode. 10. The floating gate electrode, the lower electrode, the ferroelectric film, and the upper electrode,
10. Any one of claims 4 to 9 having substantially the same plane area.
Item 14. The nonvolatile semiconductor memory device according to Item 1.