JPH11353890A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory in which a block not using a spare cell can be operated at a high speed. SOLUTION: A normal word-line driver 12 which raises the word line of a normal cell 20 and a spare word-line driver 10 which raises the word line of a spare cell 22 are installed in the block of a semiconductor memory device. By following a control signal which controls whether the normal cell 20 is to be replaced by the spare cell 22, which of the normal word-line driver 12 and the spare word-line driver 10 is to be activated is selected by a row fuse selector 6. The output start time of the driving signal of the normal word-line driver 12 or the spare word-line driver 10 is changed by a word-line driving- signal generation circuit 14. In addition, a block in which the normal cell 20 is replaced by the spare cell 22 is outputted by a spare-line usage block-number output circuit 16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a spare cell for replacing a normal cell when it is defective.

[0002]

2. Description of the Related Art A semiconductor device having a conventional spare cell will be described below with reference to the accompanying drawings. FIG. 5 is a block diagram showing a configuration of a conventional semiconductor memory device.

As shown in FIG. 5, a row address input via an address buffer 102 is input to a block fuse 104 and also to a row fuse selector 106 and a normal row decoder 108. The block selector 104 determines a block to be activated based on the input row address. Then, a block selection signal indicating a block to be activated is output from the block selector 104 to each of the low fuse selector 106 and the normal row decoder 108.

The normal row decoder 108 outputs a word line driver selection signal to the normal word line driver 112 based on the input row address.
The low fuse selector 106 compares the input row address with the address programmed by the fuse, and outputs a spare normal selection signal according to the comparison result from the low fuse selector 106. This spare / normal selection signal is supplied to spare word line driver 1
10 is input to each of the normal word line drivers 112, and activates either the spare word line driver 110 or the normal word line driver 112. More specifically, if the row address matches the address programmed by the fuse, the spare word line driver 110 is activated, and if not, the normal word line driver 112 is activated.

FIG. 6 is a circuit diagram showing a configuration of the low fuse selector 106 of the semiconductor memory device. For example,
If the normal cell is defective and a spare word line is used, the fuse in FIG. 6 is cut. Address A0-An
The fuses Fa0 to Fan corresponding to are disconnected when the bit of the defective address obtained by executing the normal cell test is "1", and the fuses Fba0 to Fban are disconnected when the bit of the defective address is "0". Is done.

The operation of the low fuse selector 106 is as follows. The node N1 is precharged to High (hereinafter, “H”) when the precharge state, that is, when the precharge signal PRCH = Low (hereinafter, “L”). First, after the PRCH becomes "H", addresses A0 to An are input.

Here, when the addresses A0 to An match the program address by the fuse, the node N1 holds the state of "H". As a result, the spare normal selection signal (/ SP0) output from the low fuse selector 106 becomes "L".

On the other hand, when the input addresses A0 to An do not match the program address by the fuse,
The electric charge of the node N1 is transferred to the ground level (“L”) through the fuse corresponding to the address that does not match,
The node N1 becomes "L". As a result, the spare normal selection signal (/ SP0) output from the low fuse selector 106 becomes "H".

In this circuit, when the addresses A0 to An do not match the program address of the fuse, it takes time to transfer the electric charge of the node N1 to "L". Therefore, the spare normal selection signal (/ SP) output from the low fuse selector 106 is output.
The time until 0) is determined becomes longer.

FIG. 7 is a circuit diagram showing a configuration of a normal word line driver 112 of the semiconductor memory device. A spare normal selection signal (/ SP0) output from the low fuse selector 106 is input as / RSP in this circuit. Address signals A0, bA
0, A1, and bA1 are connected to AND circuits AD1 to AD4 in FIG.
, And decoded into WDRV0-WDRV3 signals. This normal word line driver 112
In this case, one of the WDRV0 to WDRV3 signals changes from "L" to "H" at the timing when the WDRV signal changes from "L" to "H". The addresses bA0 and bA1 correspond to addresses A0 and AA, respectively.
1 shows an inverted signal.

FIG. 8 is a circuit diagram showing a configuration of a word line driver drive signal generating circuit 114 of the semiconductor memory device. When the WDRVA signal generated from the external clock changes from “L” to “H”, the resistance R21 and the capacitance C2
1. After the elapse of the delay time determined by C22, the WDRV signal transitions from "L" to "H". The delay time is determined from the time required for determining the output of the low fuse selector 106.

[0012]

In order to operate the normal word line driver 112, both the word line driver selection signal and the spare normal selection signal (/ SP0) need to be determined. However, in the conventional semiconductor memory device described above, the spare normal selection signal (/ SP
Since 0) is determined later, the operating speed of the low fuse selector 106 determines the operating speed of the entire circuit as described above.

The operating speed of the entire circuit is constant irrespective of whether a spare word line is used or not. Even in a block where a defective normal cell does not exist, the same timing and the same timing as a block in which a defective normal cell is replaced with a spare cell are used. It is currently operating at the operating speed.

The present invention has been made in view of the above problem, and has a circuit for causing an external controller to recognize a block that does not use a spare cell, and a word line that starts up when the spare cell is not used. It is an object of the present invention to provide a semiconductor memory device having a fuse selector for selecting at high speed, which can speed up the operation of a block that does not use a spare cell.

[0015]

In order to achieve the above object, a semiconductor memory device according to the present invention comprises a normal cell including a normally used memory cell and a defective cell when the normal cell is defective. A spare cell including a memory cell provided for replacing a normal cell, and a cell selection for selecting one of the normal cell and the spare cell according to a control signal for controlling whether to replace the normal cell with the spare cell And a block number output means for outputting the block in which the normal cell is replaced with the spare cell.

Further, a semiconductor memory device according to the present invention comprises:
A normal cell including a normally used memory cell, a spare cell including a memory cell provided to replace the defective normal cell when the normal cell is defective, and a word line connected to the normal cell. A normal word line driver to be activated, a spare word line driver to activate a word line connected to the spare cell, and the normal word line driver according to a control signal for controlling whether to replace the normal cell with the spare cell. And a word line driver selecting means for selecting which one of the spare word line drivers is to be activated, and an output start time of a signal for driving the normal word line driver or the spare word line driver according to the control signal. Word line driver drive signal generator to be changed Characterized by including and.

Further, according to the semiconductor memory device of the present invention,
A normal cell including a normally used memory cell, a spare cell including a memory cell provided to replace the defective normal cell when the normal cell is defective, and a word line connected to the normal cell. A normal word line driver to be activated, a spare word line driver to activate a word line connected to the spare cell, and the normal word line driver according to a control signal for controlling whether to replace the normal cell with the spare cell. And a word line driver selecting means for selecting which one of the spare word line drivers is to be activated, and an output start time of a drive signal for driving the normal word line driver or the spare word line driver according to the control signal Change the word line driver drive signal It has a plurality of blocks and means, further characterized by comprising the block number output means the normal cell to output the block is replaced with the spare cell.

Further, in the semiconductor memory device according to the present invention, when the control signal is a signal instructing activation of the spare word line driver, the word line driver drive signal generating means may be configured to output the drive signal of The output start time is delayed.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to an embodiment of the present invention.

As shown in FIG. 1, an address buffer 2 has a low fuse selector 6 for selecting a word line driver to be activated, and a normal row, via a block selector 4 for selecting a block to be activated. Each is connected to a decoder 8. Further, the address buffer 2 is directly connected to the low fuse selector 6 and the normal row decoder 8, respectively.

The low fuse selector 6 includes a spare word line driver 10 for raising a spare word line, and a normal word line driver 1 for raising a normal word line.
2 respectively. The normal row decoder 8
Are connected to the normal word line driver 12.

Further, a redundancy function control signal (RCTRL) for controlling whether to use the redundancy function, that is, whether to activate the spare word line driver 10, and W
The word line driver drive signal generation circuit 14 to which the DRVA signal is input is connected to the normal word line driver 12. The spare line use block number output circuit 16 to which the CTRL signal is input is connected to the DRAM controller 18.

Further, the memory cell section includes a normal cell 2
0, a spare cell 22, a sense amplifier 24, and a column decoder 26 provided to replace the normal cell 20 when it is defective. The spare word line driver 10 is connected to the spare cell 22 in the memory cell section, and the normal word line driver 12 is connected to the normal cell 20.

A DQ buffer 28 is connected to the sense amplifier 24. The DQ buffer 28
0 or a Dout signal read from the spare cell 22 is output. As described above, one block of the semiconductor memory device is configured. As shown in FIG. 1, the semiconductor memory device includes a plurality of blocks B1, B2,. have.

Next, the operation and the detailed configuration of the semiconductor memory device of this embodiment will be described. In FIG.
The row address input via the address buffer 2 is input to the block selector 4 and also to each of the row fuse selector 6 and the normal row decoder 8. The block selector 4 determines a block to be activated based on the input row address. Then, the block selector 4 outputs a block selection signal indicating a block to be activated to each of the low fuse selector 6 and the normal row decoder 8.

The normal row decoder 8 outputs a word line driver selection signal to the normal word line driver 12 based on the input row address. The low fuse selector 6 compares the input row address with the address programmed by the fuse, and outputs a spare normal selection signal according to the comparison result from the low fuse selector 6. The spare / normal selection signal is input to each of the spare word line driver 10 and the normal word line driver 12, and activates either the spare word line driver 10 or the normal word line driver 12.

More specifically, the low fuse selector 6
The spare / normal selection signal activates the spare word line driver 10 when the row address matches the address programmed by the fuse, and activates the normal word line driver 12 when they do not match.

At this time, when the redundant function control signal (RCTRL) indicating whether to use the spare word line of this block is "L", the spare normal selection signal is always at "H". Fixed.

As a result, the spare / normal selection signal is determined faster than the word line driver selection signal. The normal word line driver 12 operates at a timing determined by the word line driver selection signal. Therefore, the operation speed is controlled by the address buffer 2, the normal row decoder 8, the normal word line driver 12, and the like.
And the operation speed of the entire circuit can be increased as compared with the conventional example.

FIG. 2 is a circuit diagram showing a configuration of the low fuse selector 6 of the semiconductor memory device. As shown in FIG. 2, the drain of the transistor Tr1 whose gate receives the precharge signal PRCH is connected to the NAND circuit N
D1 is connected to a first terminal, and a redundancy function control signal (RCTRL) is input to a second terminal of the NAND circuit ND1. The drain of the transistor Tr1 and the NAND circuit N
Between the first terminal of D1 and the fuses Fa0, Fba
0,..., Fan, and Fban are respectively connected. The fuses Fa0, Fba0,..., Fan, Fban are:
The transistors T0L, T0R,..., TnL, T
It is connected to a reference potential point (GND) via nR.

The drain of the transistor Tr1 and N
The drain of the transistor Tr2 is connected to the first terminal of the AND circuit ND1. The output terminal of the NAND circuit ND1 is connected to the gate of the transistor Tr2, and a spare normal selection signal (/ SPO) is output from this output terminal.

The transistors T0L, T0R,..., T
The gates of nL and TnR have address signals A respectively.
0, bA0,..., An, bAn are input. The power supply voltage VDD is connected to the sources of the transistors Tr1 and Tr2. The address signals bA0 and bAn are:
These show inverted signals of addresses A0 and An, respectively.

The low fuse selector 6 configured as described above operates as follows. For example, when the normal cell 20 is defective and the spare word line is activated to use the spare cell 22, the fuse in FIG. 2 is cut. Fuse Fa0 corresponding to address A0-An
Fan is disconnected when the bit of the defective address obtained by executing the test of the normal cell 20 is “1”, and the fuses Fba0 to Fban are disconnected when the bit of the defective address is “0”.

The redundant function control signal (RCTRL) input to the NAND circuit ND1 is "L" when the spare word line of the block is not used, and "H" when the spare word line is used. Therefore, when RCTRL is "L", the spare normal selection signal (/ SPO) is always "H".

When the redundant function control signal (RCTRL) is "H", the following operation is performed. Node N1 is in a precharge state, that is, a precharge signal PRCH =
At the time of “L”, it is precharged to “H”. First, after the PRCH becomes "H", the addresses A0 to An
Is input, and if the addresses A0 to An match the program address of the fuse, the fuse Fa0
Since ~ Fan is disconnected, the node N1 maintains the state of "H". As a result, the spare normal selection signal (/ SP0) output from the low fuse selector 6 becomes "L".

On the other hand, if the input addresses A0 to An do not match the program address of the fuse,
The electric charge of the node N1 is transferred to the ground level (“L”) through the fuse corresponding to the address that does not match,
The node N1 becomes "L". As a result, a spare / normal selection signal (//) output from the low fuse selector 6 is output.
SP0) becomes “H”.

FIG. 3 is a circuit diagram showing a configuration of the word line driver drive signal generating circuit 14 of the semiconductor memory device. As shown in FIG. 3, the inverter IV1 to which the WDRVA signal is input is connected to the inverter IV1 via the resistor R1.
2 is connected. One end of a capacitor C1 is connected between the resistor R1 and the inverter IV2, and the other end of the capacitor C1 is connected to a reference potential point.

The drain of the transistor Tr3 is connected between the resistor R1 and the inverter IV2, and the source of the transistor Tr3 is connected to the reference potential via the capacitor C2. The inverter IV3 to which the redundant function control signal (RCTRL) is input is connected to the gate of the transistor Tr3. Then, a WDRV signal is output from the output terminal of the inverter IV2.

The word line driver drive signal generating circuit 14 configured as described above operates as follows. The redundant function control signal (RCTRL) for controlling whether to activate the spare word line driver 10 is “H” when the redundant function is used, and “L” when the redundant function is not used.
become. When the redundant function is not used, the n-channel transistor Tr3 is turned off. Therefore, when the WDRVA signal generated from the external clock changes from “L” to “H”, the WDRV signal elapses after a delay time determined by R1 × C1 has elapsed.
The signal changes from “L” to “H”. That is, WDR
The VA signal is output from the inverter IV2 as a WDRV signal after a delay time determined by R1 × C1 has elapsed.

When the redundant function is used, the n-channel transistor Tr3 is turned on.
When the VA signal changes from “L” to “H”, R1 × (C1 +
After the elapse of the delay time determined in C2), the WDRV signal transitions from “L” to “H”.

That is, the WDRVA signal is R1 × (C1
+ C2) After the elapse of the delay time, the inverter IV
2 is output as a WDRV signal. As described above, R1 × C1 determines the time for raising the word line when the redundant function is not used, and R1 × (C1 + C2) determines the time for raising the word line when the redundant function is used. .

FIG. 4 is a circuit diagram showing a configuration of the spare line use block number output circuit 16 of the semiconductor memory device. Here, the semiconductor memory device has four blocks B
The description will be made assuming that the number has 1 to B4.

As shown in FIG. 4, one end of the fuse F1 is connected to a power supply voltage VDD via a transistor Tr4, and the other end of the fuse F1 is connected to a reference potential point via a transistor Tr5.

Further, one end of the fuse F1 is connected to an inverter IV4 via an inverter IV3.
The output of the inverter IV3 is fed back to the input side of the inverter IV3 via the inverter IV5. Further, a CTRL signal is input to the gates of the transistors Tr4 and Tr5, and the inverter IV4
Outputs an Sout1 signal.

Similarly, one end of the fuse F2 is connected to the power supply voltage VDD via a transistor Tr6, and the other end of the fuse F2 is connected to a reference potential point via a transistor Tr7.

Further, one end of the fuse F2 is connected to an inverter IV7 via an inverter IV6.
The output of the inverter IV6 is fed back to the input side of the inverter IV6 via the inverter IV8. Further, a CTRL signal is input to the gates of the transistors Tr6 and Tr7, and the inverter IV7
Outputs an Sout2 signal.

One end of the fuse F3 is connected to the power supply voltage VDD via a transistor Tr8, and the other end of the fuse F3 is connected to a reference potential point via a transistor Tr9.

Further, one end of the fuse F3 is connected to an inverter IV10 via an inverter IV9. The output of the inverter IV9 is fed back to the input side of the inverter IV9 via the inverter IV11. Further, the transistors Tr8 and Tr9
The CTRL signal is input to the gate of, and the Sout3 signal is output from the output terminal of the inverter IV10.

One end of the fuse F4 is connected to the power supply voltage VDD via a transistor Tr10, and the other end of the fuse F4 is connected to a reference potential point via a transistor Tr11.

Further, one end of the fuse F4 is connected to an inverter IV13 via an inverter IV12. The output of the inverter IV12 is
Is fed back to the input side of this inverter IV12. Further, the transistor Tr10,
The CTRL signal is input to the gate of Tr11, and the Sout4 signal is output from the output terminal of the inverter IV13.

The spare line use block number output circuit 16 configured as described above operates as follows. The fuses F1 to F4 are disconnected when the spare word lines are used in the blocks B1 to B4, respectively, and are not disconnected when not used. The CTRL signal input from an external controller (not shown) is “L” in the standby state, and the receiver side outputs the external output signal Sout.
When ready to capture 1 to Sout4, CTRL
The signal becomes "H".

When the fuse is cut, that is, when a spare word line is used in the block, C
When the TRL signal changes from “L” to “H”, Sout1
ＳSout4 signal becomes “H”. When the fuse is not cut, that is, when the spare word line is not used in the block, Sout1 to Sout4
The signal becomes "L". The Sout1 to Sout4 signals are recognized by the DRAM controller 18.

In the semiconductor memory device of this embodiment, the redundancy function control signal (RCTR) for instructing the low fuse selector 6 whether or not to use the row spare line of this block is provided.
L) is input, and a spare line using block number output circuit 16 for outputting the number of the block using the spare word line is provided.

Thus, in the semiconductor memory device, if it is determined that the redundant function is not to be used for a block that does not use the spare word line, the redundant function control signal (RC
TRL), the operation of the word line driver drive signal generation circuit 14 is accelerated, and the fuse selector 6 can be operated at high speed. As a result, the access speed is higher than in the case where the redundant function is used, and a faster access cycle can be used for a block that does not use a spare word line.

As described above, according to this embodiment, in order to speed up the operation of the block not using the spare word line, the external controller can recognize the block not using the spare word line. Circuit that operates at high speed when a spare word line is not used, and has a fuse selector for selecting a word line to be activated, thereby speeding up the operation of a block that does not use a spare word line. be able to.

[0056]

As described above, according to the present invention, a circuit for causing an external controller to recognize a block that does not use a spare cell is provided, and a word line to be activated when a spare cell is not used is quickly selected. With the provision of the fuse selector described above, it is possible to provide a semiconductor memory device that can speed up the operation of a block that does not use a spare cell.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a low fuse selector in the semiconductor memory device according to the embodiment of the present invention;

FIG. 3 is a circuit diagram showing a configuration of a word line driver drive signal generation circuit in the semiconductor memory device according to the embodiment of the present invention;

FIG. 4 is a circuit diagram showing a configuration of a spare line use block number output circuit in the semiconductor memory device according to the embodiment of the present invention;

FIG. 5 is a block diagram showing a configuration of a conventional semiconductor memory device.

FIG. 6 is a circuit diagram showing a configuration of a low fuse selector in a conventional semiconductor memory device.

FIG. 7 is a circuit diagram showing a configuration of a normal word line driver in a conventional semiconductor memory device.

FIG. 8 is a circuit diagram showing a configuration of a word line driver drive signal generation circuit in a conventional semiconductor memory device.

[Explanation of symbols]

2 ... Address buffer 4 ... Block selector 6 ... Low fuse selector 8 ... Normal row decoder 10 ... Spare word line driver 12 ... Normal word line driver 14 ... Word line driver drive signal generation circuit 16 ... Spare line use block number output circuit 18 ... DRAM controller 20 Normal cell 22 Spare cell 24 Sense amplifier 26 Column decoder 28 DQ buffer B1, B2, ..., Bn Block C1, C2 Capacitor Fa0, Fba0, Fan, Fban Fuse F1, F2, F3, F4: Fuse IV1, IV2, IV3, IV4, IV5, IV6, I
V7, IV8, IV9, IV10, IV11, IV1
2, IV13, IV14 ... Inverter N1 ... Node ND1 ... NAND circuit R1 ... Resistance Tr1, Tr2, Tr3, Tr4, Tr5, Tr6, T
r7, Tr8, Tr9, Tr10, Tr11: transistors T0L, T0R,..., TnL, TnR: transistor 102: address buffer 104: block selector 106: low fuse selector 108: normal row decoder 110: spare word line driver 112: normal word Line driver 114 Word line driver drive signal generation circuit AD1, AD2, AD3, AD4 AND circuit C21, C22 Capacitor IV21, IV22, IV23 Inverter R21 Resistance Tr21, Tr22 Transistor

Claims (4)

[Claims] A normal cell including a normally used memory cell; a spare cell including a memory cell provided to replace the defective normal cell when the normal cell is defective; According to a control signal for controlling whether to replace the spare cell, according to a control signal, having a plurality of blocks including a cell selection means for selecting any of the normal cell and the spare cell, further replacing the normal cell with the spare cell And a block number output means for outputting the block. 2. A normal cell including a normally used memory cell, a spare cell including a memory cell provided to replace the defective normal cell when the normal cell is defective, and a connection to the normal cell. A normal word line driver for raising the word line, a spare word line driver for raising a word line connected to the spare cell, and a control signal for controlling whether to replace the normal cell with the spare cell. Word line driver selecting means for selecting which of the normal word line driver and the spare word line driver is to be activated; and a signal for driving the normal word line driver or the spare word line driver according to the control signal. To change the output start time of the word line The semiconductor memory device characterized by comprising: a drive signal generating means. 3. A normal cell including a normally used memory cell, a spare cell including a memory cell provided to replace the defective normal cell when the normal cell is defective, and a connection to the normal cell. A normal word line driver for raising the word line, a spare word line driver for raising a word line connected to the spare cell, and a control signal for controlling whether to replace the normal cell with the spare cell. Word line driver selecting means for selecting which of the normal word line driver and the spare word line driver is to be activated; and a drive for driving the normal word line driver or the spare word line driver according to the control signal. Word line to change the signal output start time It has a plurality of blocks including the driver drive signal generating means, further wherein the semiconductor memory device to the block number output means for outputting the block normal cells are replaced with the spare cell, characterized by comprising a. 4. The word line driver drive signal generation means delays the output start time of the drive signal when the control signal is a signal instructing activation of the spare word line driver. The semiconductor memory device according to claim 2.