JPH11353818A - Synchronous signal compensation function - Google Patents

Abstract

PROBLEM TO BE SOLVED: To effectively execute error correction with an error correction code of less redundancy by registering a portion or all of user data between two detection signals as a burst disappearance and using characteristics of an error correction code having a product code configuration with respect to this burst disappearance. SOLUTION: An error and disappearance correcting calculator 87 calculates an error position and an error value from non-zero syndrome, and corrects corresponding byte data of a data buffer. At this time, a syndrome calculator 86 receives a next sequence code word from an input data bus 82 to calculate syndrome. When receiving a non-zero value, the syndrome calculator 86 similarly transmits it to the error and disappearance correcting calculator 87, and continues the syndrome calculation of a next sequence code word. Thus, the syndrome calculator 86 and the error and disappearance correcting calculator 87 repeat the calculations in pipeline operations, thereby a correction operation can be performed at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and a device for detecting a synchronization signal, an error correction device, a reproducing device, a recording and reproducing device and a communication device. Synchronous signal detection method and apparatus suitable for a recording configuration having a synchronous signal, an error correction device, a reproducing device, a recording and reproducing device,
Related to a communication device.

[0002]

2. Description of the Related Art Techniques conventionally used will be described by taking a magnetic disk drive as an example.

FIG. 2 is a conceptual diagram of a data recording method on a recording medium 13 in a magnetic disk drive. Hereinafter, the sector recording method on the recording medium will be described with reference to FIG.

[0004] The disk-shaped recording medium 13 can be roughly divided into two areas. That is, one is the data recording area 11 (white area on the recording medium in FIG. 2), and the other is the servo area 1
0 (the gray portion on the recording medium in FIG. 2). The data recording area 11 is an area for recording user data and the like sent from the host, and the servo area 10 records servo information. The servo information is information for precisely controlling the operation of the recording / reproducing head 18 so that the recording / reproducing head 18 can obtain a desired data recording position during data recording.
In addition, by using the servo information, the operation of the recording / reproducing head 18 is controlled so that the recording / reproducing head 18 can take a desired data reproducing position during data reproduction. As can be seen from FIG. 2, when the disk-shaped recording medium rotates, the data recording area 11 and the servo area 10 pass under the recording / reproducing head 18 alternately. Data recording area 11
When the disk passes below the recording / reproducing head 18, the magnetic disk device performs a data recording / reproducing operation. When the servo area 10 passes below the recording / reproducing head 18, the magnetic disk device operates as follows. Recording / reproducing head 1
8 is controlled. By the way, the recording medium 13 records data from the host in blocks of a certain unit called a sector along a concentric data recording groove called a track. Sectors A14, B15 and C16 in FIG. 2 show an example of sector recording. Here, all of the sectors A14 and B15 can be recorded in a single data recording area. However, depending on the recording position, as in sector C16, the data is divided into a plurality of data recording areas across the servo area. May be recorded.

FIG. 3 shows a sector A14 and a sector B in FIG.
15 shows the configuration of the sector C16 in detail.
The sector configuration on the recording medium will be described with reference to FIG. 3, taking the above-described sector A14, sector B15, and sector C16 as an example.

In both sectors A14 and B15, all blocks of the sector are recorded in a single data recording area. First, there is an area called Preamble at the head of the sector. This area is for detecting the bit synchronization and the byte synchronization of the recording data at the time of reproducing the user data. next
There is an area called AM (Address Mark), which is for detecting synchronization at the start of the recording data portion. After detecting bit synchronization and byte synchronization by Preamble during playback,
, The synchronization of the start of data reading is detected, and the magnetic head reads the following user data.

By the way, with regard to sector C16, all blocks of the sector cannot be accommodated in a single data recording area.
It has straddled two data recording areas. That is, the servo area is inserted in the middle of the user data. In this servo area, data read is temporarily interrupted for servo control. Therefore, when the user data is read again from the middle after the servo area, there are a preamble area and an AM area as in the case of the sector head. According to the method, the bit synchronization, the byte synchronization, and the synchronization of the data reading start of the recording data are detected, and the remaining user data is read.

At the end of the sector, there is an area called ECC. In this area, ECC parity data calculated when the recording user data is encoded by the error correction code is recorded. This is added in order to correct the error to normal data using the parity data even if a read error occurs in a part of the data in the user data read.

With this error correction function, highly reliable data transfer to the host can be realized even if the data error rate during reading increases in a high-density recording environment.

[0010]

By the way, the error correction function described above is based on the premise that the synchronization detection at the start of data reading using the AM area has been successful. In other words, the error correction function does not function at all unless the above-described synchronization of the start of data reading is detected. That is, the error correction function does not have a function of compensating for a synchronization detection error at the start of data reading.

There are various factors in an error occurring at the time of data reading. Of course, the error may occur in the above-mentioned AM area, and the error may cause a failure in synchronous detection of the start of data reading. Conventionally, if the synchronization of the start of data reading by the AM is missed during reading, the subsequent reading of user data is impossible. When recognizing that the synchronization detection of the start of the data reading has failed, the reading operation is restarted from the beginning to try to detect the synchronization of the start of the data reading by the AM (hereinafter, this operation is referred to as a retry). So, again
If an error occurs in the AM area and synchronization detection of data read start fails, retry is further repeated. If the synchronization of the start of data reading cannot be detected even after repeated retries, it is finally determined that the data recorded following the AM cannot be read, and the data is lost.
Actually, in a magnetic disk or the like, a phenomenon in which an error occurs repeatedly at the same place (in this case, the AM area) occurs even when reading is repeated many times due to dust and the like adhering to the recording medium.

As described above, even if the detection of the start of data reading by the AM at the head of the sector becomes impossible due to a fixed occurrence error such as dust adhesion or the like, if the function of reading the user data following the AM is not realized, a high level is required. Reliable data recording and reproduction cannot be guaranteed. As a countermeasure against this AM read error, for example,
In 630, by writing a plurality of sets of AM information and a plurality of sets of distance information from the AM to the start point of the user data to the recording medium, at least one or more AMs of the plurality of AMs and A method has been reported that enables reading of user data if distance information from the AM to the start point of user data can be read. However, in this method, a plurality of pieces of AM information and distance information from the AM to the start point of the user data must be written to the recording medium, which degrades the recording efficiency of the user data on the medium. Furthermore, since such information is written continuously, if a long burst error occurs at the recording position of the information, all the AM information cannot be read, and the problem remains.

Therefore, it is necessary to realize a synchronization detection method that does not reduce the efficiency of recording user data on a recording medium and has a strong compensation capability even when a long burst error occurs.

[0014]

According to an aspect of the present invention, as a means for solving the problem, a head of a position where user data is stored in order to read a user data block stored on a recording medium. In a synchronization signal detecting apparatus for reading user data from a recording medium on which at least one user data head position identification synchronization signal pattern recorded before the error correction code is recorded, an error correction code is added in advance in a product code configuration. Not only the head position identification synchronization signal pattern that is recorded and indicates the head of the user data, but also at least one or more synchronization signal patterns n (n = 0, 1,
2. . . ) Is inserted, and when the user data in the format recorded is read, even if the detection of the head position identification synchronization signal pattern fails, another synchronization signal pattern n (n = n 0,1,
2. . . ), If at least one of them can be detected, the user data existing between the head position identification synchronization signal pattern and the synchronization signal pattern n detected for the first time can be corrected in two directions with different product error correction codes having different error correction codes. Provided is a synchronization signal detection device having an error correction function for compensating for the synchronization signal.

Further, the position (or required time) at which the detection of the start position identification synchronization signal and the detection of the synchronization signal pattern n, or the detection of either one of the synchronization signals, and the actual occurrence of the synchronization signal detection are performed. A comparison means for comparing the position (or required time), a means for estimating a synchronization signal detection error based on the result, and a means for identifying which synchronization signal pattern is detected may be provided.

Further, the above-mentioned head position identification synchronization signal pattern indicating the head and the above-mentioned synchronization signal pattern n (n = 0,
1,2. . . And a means for identifying these plural patterns may be provided, thereby having a function of identifying which synchronization signal pattern has been detected.

Further, the above-described head position identification synchronization signal pattern indicating the head and the synchronization signal pattern n (n = 0,
1,2. . . ) And the comparing means for comparing the position where synchronization signal detection is expected to occur with the position where synchronization signal detection is actually generated,
It is also possible to provide a means for estimating a synchronization signal detection error and to have a function of identifying which synchronization signal pattern has been detected.

Further, the above-mentioned head position identification synchronization signal pattern indicating the head and the above-mentioned synchronization signal pattern n (n = 0,
1,2. . . ), The number of user data that exists between
In the above product code, the code word length may be equal to the code word length of one of the series.

Further, the above-described head position identification synchronization signal pattern indicating the head and the synchronization signal pattern n (n = 0,
1,2. . . ), The number of user data that exists between
It may be characterized in that it is longer than an expected length of an error occurring at the time of reading.

Further, the above-described head position identification synchronization signal pattern indicating the head and the synchronization signal pattern n (n = 0,
1,2. . . ), The accuracy of synchronization signal detection may be improved by adopting user data that comes before or a pattern that cannot be taken in the preamble area.

Further, the above-described head position identification synchronization signal pattern indicating the head and the synchronization signal pattern n (n = 0,
1,2. . . ), At least one pattern may be recorded with fixed value data different from the pattern to improve the accuracy of detecting the synchronization signal.

The head position identification synchronization signal pattern indicating the head and the synchronization signal pattern n (n = 0,
1,2. . . ), The encoding of the product code may be performed including at least one pattern.

Further, the non-recordable area may be inserted in the middle of the user data block, and thereafter, a synchronization signal detecting means similar to the head of the user data block may be employed in order to synchronize again.

[0024]

Embodiments of the present invention will be described below with reference to the drawings.

First, a first embodiment of the present invention will be described. In the present embodiment, a description will be given of a magnetic disk device capable of executing a synchronization signal compensating function to which the present invention is applied when reproducing data from a magnetic disk as a recording medium.

First, the configuration of the magnetic disk drive will be described. The magnetic disk device has a mechanism for recording and reproducing signals using a magnetic disk as a recording medium, and an electronic circuit for processing signals recorded and reproduced by the mechanism.

Referring to FIG. 4, the mechanism of the magnetic disk drive will be described. In FIG. 4, a magnetic disk device 1680 includes a magnetic disk 810 as a recording medium for recording a signal describing data, and a spindle motor 1 for rotating the magnetic disk 810.
682, a head 811 for reading / writing signals from / on the magnetic disk 810, an arm 1683 for supporting the head 811, and a voice coil for driving the arm 1683 to move the head 811 The motor 1653 and the head 811
And a read / write control circuit 812 for amplifying a signal read out from the memory and driving the head 811 to record the signal.

Next, an electronic circuit section of the magnetic disk drive will be described with reference to FIG. In FIG. 5, a magnetic disk device electronic circuit section 1681 includes a host interface 826 for connecting to an information processing device such as a host computer, and a hard disk controller (hereinafter, referred to as HDC) for controlling data transfer and format. 817 and the head 811 (FIG. 4)
Servo control circuit unit 814 for controlling the relative positional relationship between the magnetic disk 810 (see FIG. 4) and the magnetic disk 810 (see FIG. 4).
A signal processing circuit 813 for processing signals from a read / write control circuit 812 (see FIG. 4); a data buffer 816 for temporarily storing data; and a CPU (central processing unit) for controlling these. ) 815. The CPU 815 mainly includes the HDC 817
And servo control of the magnetic disk 810 via the servo control circuit 814 is performed.

The servo control circuit section 814 includes a spindle control circuit 1685 for controlling the spindle motor 1682 (see FIG. 4) and a voice coil motor 1653.
(Refer to FIG. 4). The servo control circuit 814 is
A bidirectional signal is transmitted and received between the CPU 815 and the magnetic disk 81 using the spindle control circuit 1685.
0 rotation control and voice coil motor control circuit 1654
Is executed in accordance with the instruction of the CPU 815.

Next, with reference to FIG. 6, an outline of a recording operation and a reproducing operation of user data in the magnetic disk device will be described focusing on the HDC 817.

The HDC 817 has a magnetic disk 810.
This is a part for controlling the recording and reproduction of the user data to and from the user. This HDC 817 is a buffer control unit 81
8, the CPU input / output control unit 819, and the drive control unit 8
20 and a host interface control unit 825.

First, the operation of recording user data from the host will be described.

The user data sent via the host interface 826 is transmitted to the host interface controller 82
5, transmitted to the data buffer 816 via the data bus 833, the buffer control unit 818, and the data bus 827,
Stored temporarily.

The drive control unit 820 applies an EC to the user data temporarily stored in the data buffer 816.
An ECC parity part is added by the C circuit 830 so as to take the configuration of the product code as shown in FIG. Here, the product code will be briefly described. FIG. 7 shows a configuration example of the product code used in the present embodiment. A product code is a basic code created by combining two codes,
A q-element (n ₁ n ₂ , k ₁ k ₂ ) linear code formed by combining a q-element (n ₁ , k ₁ ) linear code C ₁ and a q-element (n ₂ , k ₂ ) linear code C ₂
When expressed the codeword sequence of n ₁ × n _2, each row (referred to as C1 direction or C1 sequence) becomes the codeword C _1, (referred to as C2 direction, or C2 sequence) each column C ₂ Is a code that becomes the code of In the configuration example of FIG. 7, C ₁ is
2 ^{8 element} (48,46) Reed-Solomon code, and C ₂ is 2
^{It is an 8-} ary (50,46) Reed-Solomon code.

In FIG. 7, D-000, D-001, D-002 ..., C
D-843 is 1-byte data, and in this example, a total of 2116 bytes are handled as one block (called a user data block). However, the xxx part of D-xxx is assumed to increase by one in hexadecimal notation. I for the ECC encoding on the user data blocks, first obtains the ECC parity part (region represented by Q-xxx) for C ₂ code. Next, this user data + C ₂ code ECC parity section 60 is provided with E ₁ for the C ₁ code.
A CC parity part (area represented by P-xxx) 61 is obtained.

[0036] In C ₁ code from the nature of the Reed-Solomon code is correctable random errors of up to 1 byte × 1 point, and in C ₂ code, correct the error and loss so as to satisfy the following formula It is possible.

[0037]

Where t is the number of random error bytes, and f is the number of random lost bytes.

Now, the configuration of the ECC circuit 830 used in the present embodiment and the operation of generating the product code ECC parity unit will be described with reference to FIG. ECC circuit 83
0 is roughly divided into a parity calculator & sequencer 84,
Syndrome calculator 86, error & erasure correction calculator 8
7, a product code correcting sequencer 85. Here, a parity calculator & sequencer 84 is used. The parity calculator & sequencer 84 is a block including a calculator for calculating ECC parity added to data when writing data to a recording medium, and a sequencer for controlling the same. As described above, the user data sent from the host (not shown) for recording on the medium is temporarily
The data is stored in the data buffer 816 (see FIG. 6).
The user data is stored in the buffer control unit 818, the data bus 828 (see FIG. 6, the drive control unit 820 (see FIG. 6)).
Through, while being read from the D-000 in the C ₂ direction, the selector 92, is transmitted to the parity calculator and the sequencer 84 via the input data bus 82. C When the user data bytes ("D-000" to "D-816") for one column in _two directions are read,
Parity calculator & sequencer 84 can calculate the C ₂ code ECC parity part of 4 bytes corresponding to the user data bytes ( "Q-000" ~ "Q-003"). Calculated the C ₂ code ECC parity part data bus 83 was, selector 80, and output through the output data bus 81, the C ₂ code ECC parity part which is output, the data bus 828, through the buffer controller 818 , Are stored in the data buffer 816. The same operation for 46 rows all C ₂ direction of the user data bytes, 4 bytes × 46 columns C ₂
The code ECC parity unit (60 in FIG. 7) is calculated and temporarily stored in the data buffer 816. The user data bytes from the data buffer 816 (see FIG. 6) to then C ₁ direction,
Data bus 827 (see FIG. 6), buffer controller 818
Read through (see FIG. 6), the data bus 828, a selector 92, the parity calculator and the sequencer 84 via the input data bus 82, 2 bytes × 50 columns of C ₁ code E
Calculate the CC parity part. Thus the data transmitted from the host C ₂ direction (column direction) and, twice C ₁ direction (row direction), by sending to the ECC circuit, can be constructed product code as shown in FIG.

The {user data + ECC parity section} encoded in the product code configuration is transmitted to the encoder / decoder 813 via the data bus 829 under the control of the drive control section 820, and recorded on the magnetic disk 810. You.

The {user data + ECC parity section} having the product code structure generated by the ECC circuit 830 is transmitted to the read / write control circuit 812 via the encoder / decoder 813 for recording on the magnetic disk 810. Here, operations of the encoder / decoder 813 and the read / write control circuit 812 will be described.
The encoder / decoder 813 divides the received {user data + ECC parity section} into units and encodes them into RLL (Run Length Limited) codes suitable for recording on a magnetic medium. For example, when an 8-9 RLL code is used, each 8 bits of the byte data of the {user data + ECC parity section} is encoded into 9-bit data mapped in advance. By this encoding, the number of consecutive bits having a value of 0 can be restricted with respect to the user data and the ECC parity portion which are originally arbitrary data strings. That is, if it is desired to restrict the data so that only four bits of value 0 continue continuously, the value 0 appears only up to 4 bits consecutively for all 8-bit data (that is, 256 kinds of data). It is sufficient to map 9-bit data that does not exist.

The 8-bit data "D-000" to "P" in FIG.
When “-311” comes from the upper left byte data (“D-000”) in the product code block to the right one byte at a time until the rightmost byte of the row, the encoder /
The encoder / decoder 813 transmits the 8-bit data to the 9-bit data “C000” to “C95F” corresponding to the mapping by 8-9.
Perform RLL encoding.

The data encoded as described above is transmitted from the encoder / decoder 813 to the read / write control circuit 812. In the read / write control circuit 812, the data is transmitted to the magnetic disk 810 via the magnetic head 811. The user data and the like are recorded in the upper target position in a format as shown in FIG. First, a preamble pattern for bit synchronization and byte synchronization is written, and the encoded {user data + EC
At the beginning of the C parity part (that is, "C000" to "C95F")} and at an appropriate position, two different 9
The bit pattern data synchronization detection signals AM1 and AM2 are inserted and recorded. Here, regarding the positional relationship between AM1 and AM2, in the present embodiment, in order to simplify the execution sequence of the data error compensation at the time of reading, the AM
The code word of the C1 sequence is positioned so as to be exactly one between 1 and AM2, but other configurations are also conceivable. For example, the length of the user data byte between AM1 and AM2 may be set to a value that exceeds the burst error length expected to actually occur.
This allows efficient use of the error correction capability. In this embodiment, two signals AM1 and AM2 are used as data synchronization detection signals. However, this number does not affect the essence of the present invention.
The present invention can be easily applied even when three or more data synchronization detection signals are used.

In the present embodiment, as the 9-bit patterns for detecting AM1 and AM2, two patterns that are not included in the 9-bit pattern mapped from the above-mentioned user data and the 8-bit data of the ECC parity part are selected. assign. This is to make AM1 and AM2 unique patterns so as to prevent other user data bytes from being erroneously detected as AM1 and AM2 when detecting synchronization for starting data reading. In the present embodiment, AM1 and AM2 are each set to a 9-bit pattern. However, the present invention can easily be applied to patterns of 10 bits or more. For example, as shown in FIG. 11, a 9-bit fixed pattern aa or the like is inserted into user data before AM2, and then AM2 is inserted to provide redundancy, thereby improving the reliability of synchronization detection pattern detection. Other methods are also conceivable.

Thus, the recording operation of the user data is realized.

Next, the operation of reading the recorded user data will be described.

The user data + EC recorded on the magnetic disk 810 under the control of the drive control unit 820
C parity section｝ is transmitted to drive control section 820 via magnetic head 811, read / write control circuit 812, encoder / decoder 813, and data bus 829.

Here, how to synchronize user data will be described.

The read / write control circuit 812 has the Preamb
In the le area (see FIG. 8), the bit synchronization and the byte synchronization of the reproduction data are performed, and the process waits for AM1 and AM2 to be read.

At this time, consider the following three cases. That is, (1) when AM1 is read normally, (2) when AM1 cannot be read normally, and when AM2 is read normally, and (3) when both AM1 and AM2 cannot be read normally. It is about.

First, when no error occurs when reading AM1 and AM1 is normally read, the read / write control circuit 812 (see FIG. 6) sets the synchronization detection signal line A850.
Via FIG. 6 (see FIG. 6), the drive controller 820 (see FIG. 6) is notified that AM1 has been detected. By this signal, the drive control circuit 820 (see FIG. 6)
Reading is started by synchronizing from the next data "C000" of 1 as user data. However, as described above, the 9-bit data “C000” to “C95F” are converted into the 8-9 RLL code when the data is recorded on the recording medium, and the data “D-000” to “P95” are recorded.
−311 ”is encoded, so that during this read processing, when the data passes through the encoder / decoder 813, the data is inversely decoded into the original 8-bit data“ D-000 ”to“ P-311 ”, and then drive control is performed. The signal is transmitted to the circuit 820. Further, when AM1 is read normally and the data is synchronized, AM1 and AM2 are unnecessary for data transfer to the host. Lead /
The write control circuit 812 (see FIG. 6) does not transmit the AM1 and AM2 to the encoder / decoder 813 (see FIG. 6).

Next, when an error occurs when reading AM1,
Was not read normally, but was successfully read for AM2, the read / write control circuit 812 (FIG. 6)
) Informs the drive control unit 820 (see FIG. 6) that AM2 has been detected via the synchronization detection signal line B851 (see FIG. 6). By this signal, the drive control circuit 820 (see FIG. 6) transmits the next data “C03” of AM2.
Reading is started in synchronization with “0” as user data. However, as described above, 9-bit data “C03”
0 ”to“ C95F ”are 8-9R when data is recorded on the recording medium.
Since the data "D-02e" to "P-311" are encoded in the LL code, during this read processing, when the data passes through the encoder / decoder 813 (see FIG. 6), the original 8-bit data " After being decoded to D-02e "to" P-311 ", it is transmitted to the drive control circuit 820 (see FIG. 6). When AM2 is read normally and data synchronization is established, since AM2 is no longer necessary for data transfer to the host, the read / write control circuit 812 (see FIG. 6) ) Prevents the AM2 from being transmitted to the encoder / decoder 813 (see FIG. 6).

Finally, when an error occurs during reading for both AM1 and AM2 and the data cannot be read normally, the read / write control circuit 812 (see FIG. 6) cannot detect the synchronization signal, and therefore, the drive control circuit 820 (See Fig. 6)
Cannot specify the start point of the current read data.
Therefore, since the data of the sector cannot be read in the current read sequence, the operation ends abnormally, and the process shifts to retry processing.

When data synchronization can be detected by AM1 or AM2, the drive control unit 820 (see FIG. 6)
Indicates that the read user data + ECC parity unit is a data bus 828 (see FIG. 6) and a buffer control unit 818 (FIG. 6).
) And a data buffer 816 (see FIG. 6) via a data bus 827 (see FIG. 6), and controls the ECC circuit 830 to control the {user data +
It is detected whether an error is included in the ECC parity unit #.

When an error is detected by the ECC circuit 830, error correction processing is continuously performed, and based on the calculated error position and error value, the data bus 834 (see FIG. 6) and the buffer control unit 818 (see FIG. 6). ) And a data buffer 816 via a data bus 827 (see FIG. 6).
The corresponding error data among the user data stored in (see FIG. 6) is corrected.

Here, the above error correction processing is performed by
The operation differs depending on the detection conditions of AM1 and AM2. FIG. 9 is a flowchart showing the error correction processing operation, and the operation of the ECC circuit 830 in each case will be described with reference to FIG.

As shown in FIG. 9, when AM1 is detected, the user data is the first byte "D-000".
From the last byte (the end of ECC parity data)
P-311 "are read in synchronization with each other.
Find the syndrome for one series (FIGS. 9 and 20)
0). 5 of the obtained C1 series (consisting of 50 lines of code words)
If any of the 0 syndrome sets takes a non-zero value, an error correction operation is performed on the codeword (FIG. 9,
201). Based on the error position and error value obtained by the error correction operation, the byte data at the corresponding position of the read {user data + ECC parity unit} stored in the data buffer 816 (see FIG. 6) is corrected. .
The error correction operation and the data buffer correction are similarly completed for all C1 sequence codewords whose syndromes have non-zero values. In the actual operation of the ECC circuit 830, when it is recognized that AM1 is detected by the synchronization detection signal line A850 in FIG.
9, a syndrome calculator 86 calculates a syndrome for each of the C1 sequence codewords received via the input data bus 82, and when a non-zero value is obtained, the syndrome value is transferred to the data bus 88. The error & erasure correction calculator 87 calculates the error position and error value from the received non-zero syndrome, and calculates the error position and the error position via the data bus 834. Data buffer 81 from error value
6 (see FIG. 6) corresponding byte data is corrected. At this time, the syndrome calculator 86 receives the next C1 sequence codeword from the input data bus 82 and calculates the syndrome. If the syndrome is calculated and a non-zero value is obtained, it is transmitted to the error & erasure correction calculator 87 in the same manner,
The syndrome calculator 86 continues calculating the syndrome of the next C1 sequence codeword. Thus, the syndrome calculator 8
6 and the error & erasure correction arithmetic unit 87, so to speak, repeat operations in a pipeline operation, so that a high-speed correction operation can be performed.

A syndrome is obtained for the C2 sequence from the {user data + ECC parity part} which has been corrected in the C1 sequence stored in the data buffer 816 (see FIG. 6) (202 in FIG. 9). In an actual circuit,
From the data buffer 816 (see FIG. 6) to the data bus 82
7 (see FIG. 6), buffer controller 818 (see FIG. 6),
The {user data + ECC parity section} is read from the input data bus 82 in the C2 sequence direction via the data bus 828 (see FIG. 6) and the selector 92 (see FIG. 6).
The syndrome calculator 86 calculates the syndrome.
The error & erasure correction arithmetic unit 87 may register the row that cannot be corrected in the correction of the C1 sequence as the erasure in the C2 sequence, and obtain the erasure position polynomial (FIGS. 9 and 203). If any of 46 syndrome sets of the obtained C2 sequence (consisting of 46 rows of codewords) takes a non-zero value, the error and erasure of that codeword is determined from the syndrome (and the erasure position polynomial). The correction operation is performed by the error & erasure correction operation unit 87, and based on the error position and error value obtained by the error & erasure correction operation, the read {user} stored in the data buffer 816 (see FIG. 6). The byte data at the corresponding position of the data + ECC parity section 訂正 is corrected.

All Cs whose syndromes have non-zero values
The error correction operation and the buffer memory correction are similarly completed for the two-sequence codeword (FIG. 9, 204). Also at this time, as described above, the syndrome calculator 86 and the error & erasure correction calculator 87 perform a pipeline operation to realize high-speed calculation.

Here, if the error & erasure operation is successful for all the C2 sequence codewords whose syndromes have non-zero values, it is determined that all the read data including the error has been compensated for as normal data, and the data buffer is determined. 816
The user data temporarily stored in the data bus 827 (see FIG. 6) and the buffer controller 818 (see FIG. 6).
(See FIG. 6) and the host interface control unit 825 (see FIG. 6) via the data bus 833 (see FIG. 6).
Sent to The host is a host interface control unit 82
5 (see FIG. 6) to the host interface 826 (see FIG. 6).
(See Reference). In this way, a user data reproducing operation is realized. However, if the error correction operation has failed for at least one C2 sequence codeword, it is determined that data compensation has failed, and the process proceeds to the retry processing of the read data.

In FIG. 9, if AM1 cannot be detected and AM2 can be detected, the user data is "D" which is the next byte of AM2.
-02e "to the last byte (the end of the ECC parity data)" P-311 "are read in synchronization with each other. First, from the {user data + ECC parity section}, data" D-000 "to A syndrome is obtained for a code C1 sequence other than the C1 code of “P-001” (FIGS. 9 and 21).
0). 4 of the obtained C1 sequence (consisting of 49 lines of code words)
If any of the nine syndrome sets takes a non-zero value, an error correction operation is performed on the codeword. Based on the error position and error value obtained by the error correction operation, the byte data at the corresponding position of the read {user data + ECC parity unit} stored in the data buffer 816 (see FIG. 6) is corrected. . The error correction operation and the data buffer correction are similarly completed for all the C1 sequence codewords whose syndromes have non-zero values (FIG. 9, 211). In the actual operation of the ECC circuit, when it is recognized that AM2 is detected by the synchronization detection signal line B851 in FIG. 1, the next byte of AM2 is transmitted via the data bus 829, the selector 92, and the input data bus 82. The syndrome calculator 86 calculates a syndrome for each of the C1 sequence codewords received from “D-02e” to “P-311” of the last byte (the end of ECC parity data), and a non-zero value is obtained. If so, the syndrome value is transmitted to the error & erasure correction calculator 87 via the data bus 88, and the error & erasure correction calculator 87 is transmitted.
Calculates the error position and error value from the received non-zero syndrome and corrects the corresponding byte data in the data buffer 816 (see FIG. 6) from the error position and error value calculated via the data bus 834.

Next, a syndrome is obtained for the C2 sequence from the {user data + ECC parity section} which has been corrected in the C1 sequence and stored in the data buffer 816 (212 in FIG. 9). Here, the first byte of the code word of each C2 sequence is obtained as a value 0. This is because the first byte of the code word of each C2 sequence corresponds to the code words of data “D-000” to “P-001” in the C1 sequence,
This is because the codeword could not be read out to the data buffer 816 (see FIG. 6) because AM1 could not be detected. In the actual ECC circuit 830, the syndrome operation is performed from the second byte of each codeword of the C2 sequence. As a result, the first byte is calculated as the value 0, and the syndrome can be easily calculated.

The error & erasure correction calculator 87 registers the first byte of the codeword of each C2 sequence as an erasure position, and obtains an erasure position polynomial (FIG. 9, 213). At this time, an erasure position polynomial may be obtained as an erasure in the C2 sequence even for a row that cannot be corrected in the C1 sequence correction (FIG. 9, 213). The obtained C2 series (46
The error & erasure correction calculator 87 performs an error & erasure correction operation for each codeword according to the 46 syndrome sets (consisting of the codewords of the row) and the erasure position polynomial. Error (loss) position found by error correction operation,
Based on the error (erasure) value, the byte data stored in the data buffer 816 at the corresponding position of the read {user data + ECC parity section} is corrected.
The error & erasure correction operation and the buffer memory correction are similarly completed for all the C2 sequence codewords (214 in FIG. 9). Here, if the error correction operation is successful for all the C2 sequence codewords, it is determined that all the read data including the error has been compensated for as normal data, and the data is temporarily stored in the data buffer 816 (see FIG. 6). The user data is sent to the host interface controller 825 (see FIG. 6) via the data bus 827 (see FIG. 6), the buffer controller 818 (see FIG. 6), and the data bus 833 (see FIG. 6). The host receives the user data from the host interface control unit 825 (see FIG. 6) via the host interface 826 (see FIG. 6). In this way, a user data reproducing operation is realized. However, when the error & erasure correction operation has failed for at least one C2 sequence codeword, it is determined that data compensation has failed, and the process proceeds to the retry processing of the read data.

As described above, in the first embodiment and the second embodiment to which the present invention is applied, the AM1
Even if it cannot be detected due to an error, if only AM2 can be detected, in many cases, the sector data can be compensated, and highly reliable data transfer to the host becomes possible.

In the present embodiment, after the ECC circuit 830 (see FIG. 6) adds an ECC parity part having a product code structure to the user data, the encoder / decoder 813 (see FIG. 6) outputs -9 RLL code, and then read / write control circuit 812
AM1 and AM2 are inserted (see FIG. 6), and into the disk type recording medium 810 (see FIG. 6), the {user data + ECC parity section} encoded into the 8-9 RLL code and the AM
1, AM2 etc. were recorded, but the following method is also conceivable.
That is, AM1 and AM2 are inserted into the user data previously encoded into the 8-9 RLL code by the encoder / decoder 813 (see FIG. 6), and this is inserted into the ECC circuit 830.
(See FIG. 6), an ECC parity part having a product code configuration is added. That is, an ECC parity part having a product code configuration is generated for a set of user data and AM1 and AM2. In this way, it is conceivable to enable the compensation function of the ECC parity unit having the product code configuration for AM1 and AM2.

In the present embodiment, the description has been made on the assumption that all the sector data is recorded in the single data recording area 11 (see FIG. 2). However, as a matter of course, as described in the description of the prior art, The present invention can be easily applied to a case where the sector data is divided by the servo area 10 (see FIG. 2) and divided into a plurality of data recording areas 11 (see FIG. 2). In such a case, after the sector data is divided into the servo area 10, a preamble area for performing bit synchronization and byte synchronization and an area corresponding to AM are conventionally used (see FIG. 3). ), The synchronization signal compensation function of the present invention can be easily applied here as well as the synchronization at the head of the sector data.

Next, a second embodiment of the present invention will be described. In the present embodiment, the operation of the compensation function relating to the detection of AM1 and AM2 performed by the HDC 817 in the magnetic disk device described in the first embodiment is different. Therefore, the description will focus on these different parts.

The feature of the compensation function relating to the detection of AM1 and AM2 in the present embodiment can be described with reference to FIG. 6 as follows. When the drive control unit 820 does not report the AM1 detection signal within a certain set time after starting the wait of the AM1 detection signal, the read / write control circuit 812
Reading of AM1 cannot be detected, and it is interpreted that reading of the user data section has already been started. Then, data reading is started from that point in time, and an AM2 detection signal is reported. From the time the AM2 detection signal is reported, A
Read data of {user data + ECC parity byte} after M2. By doing so, even if AM1 detection fails, data reading can be started without waiting for AM2 detection,
Loss of valid data can be minimized. Hereinafter, the operation of the HDC 817 of this embodiment will be described in detail.

First, the operation of recording user data from the host is the same as that of the first embodiment, and the same product code configuration is used. Since the read operation of the user data recorded on the recording medium is different from that of the first embodiment, the read operation will be described below with reference to FIGS.

The drive control unit 820 (see FIG. 6) includes a servo control circuit 814 (see FIG. 6) and a CPU 815 (see FIG. 6).
When it is determined that the magnetic head 811 (see FIG. 6) is positioned in front of the target sector to be read from the information given from the reference byte, the value of the increment byte counter (not shown) (denoted by C in FIG. 10) is set to 0. Reset (Fig. 10,
100). Here, the increment byte counter (hereinafter, referred to as a counter) is a read / write control circuit 8.
12 is incremented by 1 in synchronization with the user data bytes read from the medium transmitted to the drive control unit in byte units from the encoder 12 (see FIG. 6) via the encoder / decoder 813 (see FIG. 6). It is. Then, the read / write control circuit 812 sends a synchronization detection signal line A850
Monitor if AM1 is detected via (FIG. 6)
If is not detected, the value of the counter is checked, and if it is less than the set value R (the meaning will be described later), the counter is incremented. If AM1 is detected, the drive control unit 820 (see FIG. 6) determines that the user data starts from the next input user data byte,
Start reading data. The total sector size (user data + ECC parity part) of the present embodiment is 24.
The data of 00 bytes is read (FIGS. 10 and 101), and the read data is temporarily stored in the data buffer 816 (see FIG. 6) via the data bus 828 and the buffer control unit 818. Thereafter, error detection and correction are performed by the ECC circuit 830 (see FIG. 6) based on the detection of AM1 described in the first embodiment, and the compensated data is transferred to the host.

Here, the above set value R is a so-called timeout value for determining that the read / write control circuit 812 (see FIG. 6) has failed to detect AM1.
That is, the expected value that AM1 will be detected before the drive control unit 820 (see FIG. 6) resets the increment byte counter and counts up to the value R is set. For example, if it is expected that the counter value is separated by 20 (byte clock) from the time when the counter is reset to the time when AM1 is detected, R is set to 25 or the like. The difference 5 between the counter value 20 and the set value 25 of R has a meaning of a margin in consideration of errors such as variations in rotation speed during operation of the magnetic disk device and deformation of the medium. Well, while waiting for AM1 detection,
Although the counter is incremented, it is determined that the counter value C has exceeded the set value R in the drive control unit 820 (see FIG. 6) in a state where AM1 is not detected.
When the comparator (not shown) recognizes the counter value C and the setting R, the drive controller 820 (see FIG. 6) resets the counter value C (FIGS. 10 and 103), and
Reading is started with the data input from 29 as user data. That is, the drive control unit 820 (FIG. 6)
), AM1 was not detected, but the data bus 82
It is presumed that the input of the user data via 9 has already started, and the reading of the user data starts. Then, after that, it is monitored via the synchronization detection signal line B851 (see FIG. 6) whether or not AM2 has been detected. If AM2 has not been detected, the value of the counter is examined and the set value 48 (to be described later about the meaning of this value) If the value is less than (Description), the reading of the user data bytes via the data bus 829 is continued while the counter is incremented (105 in FIG. 10). If AM2 is detected, the drive control unit 82
0 (see FIG. 6) transmits the current counter value C to the ECC circuit 830 (see FIG. 6), and the ECC circuit 830 (see FIG. 6) stores the counter value C in an internal register (not shown). . Further, the drive control unit 820 (see FIG. 6) reads 2352 bytes (the number of bytes from the next data byte of AM2 to the last byte of the read sector) from that point (FIG. 10, 104), and the data buffer 816 (see FIG. 6). ) Is temporarily stored via the data bus 828 and the buffer control unit 818. Subsequent EC
The processing of the C circuit 830 (see FIG. 6) will be described later in detail. The set value 48 is the read / write control circuit 8
Reference numeral 12 (see FIG. 6) is a timeout value for detecting that AM2 has failed to be detected. That is, when the drive control unit 820 (see FIG. 6) starts reading data, the increment byte counter is reset (103 in FIG. 10), and AM2 is counted up to the value 48 which is the code word length of the C1 sequence. AM2 is not detected
The read / write control circuit 812 (see FIG. 6) detects AM2 and determines that it has failed. When the drive control unit 820 (see FIG. 6) detects AM2 and determines that it has failed, it determines that it has failed to synchronize the reading of the sector data to be currently read, and performs a data read retry operation. (Figure 1
0,106).

Now, AM2 is detected, and 2352
The processing of the ECC circuit 830 (see FIG. 6) after reading the bytes (FIGS. 10 and 104) will be described with reference to FIG. In this case, since a burst error occurred around AM1 and AM1 could not be detected, the position of AM1 was estimated by the internal counter of the drive control unit 820 (see FIG. 6), and the start point of data reading was determined. From the user data at that time, the data bus 829 (see FIG. 6), the selector 92 (see FIG. 6), the input data bus 82
Via the syndrome calculator 8 in the ECC circuit 830
6, the syndrome is calculated, and the codeword length of the first codeword of the C1 sequence is 48.
Syndrome calculation using all bytes may not be possible. The number of bytes used for calculating the syndrome among the 48 bytes of the code word is determined by the drive control unit 8 described above.
12 (see FIG. 6) can be determined by the counter value C transmitted and stored in an internal register (not shown) of the ECC circuit. If the value of the internal register is equal to 48, it can be determined that the position estimation of AM1 by the internal counter of the drive control unit 820 (see FIG. 6) was correct, and that the syndrome could be calculated using all the 48 bytes of the code word. If the value of the internal register is less than 48, it is considered that the syndrome is calculated from the position shifted from the beginning of the code word by the difference byte from 48, and the syndrome is calculated by the syndrome calculator 86 at this time. The syndrome calculation value is equal to the syndrome calculation value calculated using the data bytes from which the difference bytes from the beginning of the codeword are set to 0 and the remaining data bytes are actually read. Therefore, if the value of the difference byte is sufficiently smaller than the correction capability of the code word of the C1 series (for example, up to 1 byte in this embodiment), the difference byte from the beginning of the code word is registered as lost. The ECC circuit 830 may execute the error & erasure correction on the codeword by the error & erasure correction operation unit 87. Alternatively, the calculated syndrome value is ignored and not used.
The code word of the C1 sequence may be determined to be uncorrectable. When the value of the difference byte is larger than the correction capability of the code word of the C1 sequence, the calculated syndrome value is ignored and not used, and it is determined that the code word of the C1 sequence cannot be corrected. When it is determined that the correction is impossible, the code word row of the C1 sequence may be registered as an erasure for the correction operation of the C2 sequence. The following registration method is considered.

First, since the line of the code word of the C1 series cannot be corrected, a method of registering all bytes of the code word as erasure is considered (a method similar to the first embodiment). Alternatively, from the beginning of the codeword, register the erasure of the byte data corresponding to the difference byte,
It may be used for error & erasure correction of C2 sequence. Alternatively, the codeword of the C1 series has an appropriate set distance V bytes (where V> the appropriate distance) from the first byte of the codeword due to the fact that the detection of AM1 located before the first byte has failed. It is also possible to estimate that a burst error has occurred up to the difference byte), register the byte data at a distance of V bytes from the first byte as lost, and use it for C2 sequence error & lost correction. As the value of V, for example, it is conceivable to set an average value of byte lengths of burst errors that can occur when reading data from the recording medium. E
The error & erasure correction of the C2 sequence in the CC circuit 830 is executed by using the syndrome calculator 86 and the error correction & erasure correction calculator 87 in the same manner as described in the first embodiment. However, when the syndrome is calculated by the syndrome calculator 86, all the byte data at the erasure position set as described above are calculated with the value set to 0. If the error correction operation is successful for all the C2 sequence codewords, it is determined that all of the read error-containing data has been compensated for as normal data, and the user temporarily stored in the data buffer 816 (see FIG. 6). The data is transferred to the data bus 827 (see FIG. 6), the buffer controller 818 (see FIG. 6), and the data bus 833 (see FIG. 6).
) (See FIG. 6). The host sends the host interface 82 from the host interface control unit 825 (see FIG. 6).
6 (see FIG. 6). In this way, a user data reproducing operation is realized. However, when the error & erasure correction operation has failed for at least one C2 sequence codeword, it is determined that data compensation has failed, and the process proceeds to the retry processing of the read data. By the way, in the present embodiment, the drive control unit 820 (see FIG. 6) waits for AM2 detection after judging the detection error of AM1 using the above counter.
AM1 and AM1
The two write detection patterns may be the same. By adopting this method, a detection circuit having only a single pattern can be used without having a detection circuit having different AM1 and AM2, and cost can be reduced by reducing the circuit scale of the circuit to which the present invention is applied.

As described above, in the first embodiment and the second embodiment to which the present invention is applied, the AM1
Even if it cannot be detected due to an error, if only AM2 can be detected, in many cases, the sector data can be compensated, and highly reliable data transfer to the host becomes possible. In the first embodiment and the second embodiment,
Since AM1 and AM2 are recorded on the medium at a distance of 54 bytes, a long burst error of about 50 bytes occurs between AM1 and A2.
Even if it occurs around M2, due to the error, AM1, AM2
Both cannot be read out. In addition, this 50
Even if a byte length burst error occurs, the product code C2
By decomposing the error in the direction, the burst error can be corrected efficiently with a small error correction capability (in this case, only one erasure correction capability is used for each C2 sequence codeword). In addition, even if a plurality of errors occur on the sector data, the errors can be corrected by using the product code of the present embodiment. Further, in the second embodiment, even if AM1 detection fails, data reading can be started without waiting for AM2 detection, and the loss of valid data can be minimized. In addition, by estimating the burst error length considered to have occurred around AM1 to some extent and using it for registration of the erasure position, error & erasure correction can be executed effectively with an error correction capability using a limited error correction code,
Data transfer to a more reliable host becomes possible.

[0074]

As described above, according to the present invention, when data is read from the recording medium, even if the first detection signal pattern indicating the head of the data block is overlooked, after the appropriate amount of user data thereafter, If an additional detection signal is detected, a part or all of the user data between these two detection signals is registered as burst erasure. By utilizing the property of the error correction code having the product code configuration for the burst erasure, the error correction can be efficiently executed with the error correction code having a small redundancy. Since data is recorded on a recording medium using an error correction code with a small degree of redundancy, the recording density of user data can be relatively improved, and highly reliable data reading can be realized.

[Brief description of the drawings]

FIG. 1 is an ECC circuit.

FIG. 2 shows a sector recording method on a magnetic disk medium.

FIG. 3 is an example of a sector configuration on a magnetic disk medium.

FIG. 4 is a magnetic disk drive.

FIG. 5 is an electronic circuit unit of the magnetic disk drive.

FIG. 6 is a configuration example of a magnetic disk drive.

FIG. 7 shows the configuration of a product code.

FIG. 8 shows a format on a recording medium.

FIG. 9 is an error correction processing flow.

FIG. 10 is a data read control flow.

FIG. 11 shows a different example of a format on a recording medium.

[Explanation of symbols]

 830 ECC circuit 84 Parity calculator & sequencer 85 Product code correction sequencer 87 Error & erasure correction calculator 86 Syndrome calculator 850 Sync detection signal line A 851 Sync detection signal line B 810 Magnetic disk 1680 Magnetic disk unit 820 Drive control unit 819 CPU I / O controller 818 Buffer controller 825 Host interface controller 816 Data buffer 813 Encoder / decoder 812 Read / write control circuit 814 Servo control circuit

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Katsumi Yamamoto, Inventor 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Inside the Semiconductor Division, Hitachi, Ltd. Within Hitachi Storage Systems Division

Claims (10)

[Claims] At least one user data head position identification synchronization signal pattern recorded before a head of a position where user data is stored is read in order to read a user data block stored in a recording medium. In a synchronization signal detection device for reading user data from a recording medium, an error correction code is added and recorded in advance in a product code configuration,
At least one or more synchronization signal patterns n (n = 0, 1,...) Are included not only in the head position identification synchronization signal pattern indicating the head of the user data but also in user data separated by an appropriate distance therefrom. .) Is inserted, and when the user data in the format recorded is read, even if the detection of the head position identification synchronization signal pattern fails,
If at least one of the other synchronizing signal patterns n (n = 0, 1, 2,...) Inserted in the subsequent user data can be detected, the head position identification synchronizing signal pattern and the first detected synchronizing signal A synchronous signal detection device having an error correction function of compensating user data existing between a pattern n and a product code configuration using two different correction capabilities of the error correction code. 2. The method according to claim 1, wherein the start position identification synchronization signal is detected and
A comparison means for comparing a position (or required time) where the detection of the synchronization signal pattern n or one of the detections of the synchronization signal is expected with a position (or required time) at which the actual detection of the synchronization signal occurs; 2. The synchronization signal detecting apparatus according to claim 1, further comprising: means for estimating a synchronization signal detection error based on a result, and means for identifying which synchronization signal pattern has been detected. 3. A synchronizing signal pattern indicating a head position indicating the head and a synchronizing signal pattern n (n = 0, 1, 1)
2. . . 3. The synchronizing signal according to claim 1, further comprising means for identifying different patterns by adopting different patterns, and having a function of identifying which synchronizing signal pattern is detected. Detection device. 4. A head position identification synchronization signal pattern indicating a head and a synchronization signal pattern n (n = 0, 1, 1)
2. . . ), A comparison means for comparing a position where synchronization signal detection is expected to occur with an actual synchronization signal detection position, and a means for estimating a synchronization signal detection error based on the result. 2. The synchronization signal detecting device according to claim 1, further comprising a function of identifying which synchronization signal pattern is detected. 5. A head position identification synchronization signal pattern indicating a head and the synchronization signal pattern n (n = 0, 1, 1)
2. . . 5. The synchronization signal detection according to claim 1, wherein the number of user data existing between the first and second codes is made equal to the code word length of one of the series in the product code. apparatus. 6. A head position identification synchronization signal pattern indicating the head and a synchronization signal pattern n (n = 0, 1, 1)
2. . . 6. The synchronization signal detecting device according to claim 1, wherein the number of user data existing between the synchronous signal detecting device and the synchronous data detecting device is longer than an expected length of an error occurring at the time of reading. 7. A head position identification synchronization signal pattern indicating a head and a synchronization signal pattern n (n = 0, 1, 1)
2. . . ), The accuracy of synchronization signal detection is improved by adopting preceding user data or a pattern that cannot be taken in the preamble area in at least one of the patterns. 4,
7. The synchronization signal detecting device according to claim 5. 8. A head position identification synchronization signal pattern indicating a head and a synchronization signal pattern n (n = 0, 1, 1)
2. . . Wherein the fixed value data different from the pattern is recorded before at least one of the patterns to improve the accuracy of detecting the synchronization signal. 7. The synchronization signal detection device according to claim 6. 9. The synchronizing signal pattern indicating the head position indicating the head and the synchronizing signal pattern n (n = 0, 1, 1)
2. . . ), Including at least one of
The encoding of the product code is performed,
2. The synchronization signal detection device according to 2, 3, 4, 5, 6, 7, or 8. 10. A recording apparatus according to claim 1, wherein a non-recordable area is inserted in the middle of the user data block, and thereafter, a synchronizing signal detecting means similar to the head of the user data block is employed for synchronizing again. 1, 2, 3, 4,
5. The synchronization signal detection device according to 5, 6, 7, 8, 9.