JPH11345943A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the semiconductor device and the manufacturing method thereof, which can increase the capacitance of a capacitor more than in the conventional case when the dimensions of trench grooves are equal. SOLUTION: A trench groove 15 is formed so that one diameter of an inner bottom surface becomes larger than the opening part. Furthermore, between a diffused layer 17 as a lower electrode and a polycrystalline silicon film 20 as an upper electrode, conductive particles 18 and an insulating film covering the particles 19 covering the surface are present. Thus, the surface area between the electrodes is increased. Therefore, even if the dimension of the conventional trench-groove type capacitor and the dimension of an opening are equal, the capacitor having more larger capacitance can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a device having a trench capacitor and a method of manufacturing the same.

[0002]

2. Description of the Related Art DRAM (Dynamic Random Access Memory)
ry) has a configuration including a capacitor and a transistor for each cell. Then, it is becoming difficult to secure the capacity of the capacitor as the element becomes finer. Conventionally, such a problem has been dealt with by forming a three-dimensional structure such as a trench groove or a stack.

A DRA having a conventional grooved cell capacitor
The structure of M was as shown in FIG. On the surface of the semiconductor substrate 61, a silicon oxide film 62, a silicon nitride film 63, and a TEOS film 64 are sequentially deposited. A trench 65 is formed in the capacitor formation region by a reactive ion etching (hereinafter, referred to as RIE) method.

[0004] As shown in FIG. 15, an impurity diffusion layer 66 is formed at the bottom of the trench 65 by solid-phase diffusion of impurities. As shown in FIG. 16, a capacitor insulating film 67 is formed so as to cover the inner wall and bottom surface of the trench 65 and the entire surface of the TEOS film 64.

As shown in FIG. 17, a TEOS film 68 is formed on the inner wall of the trench 65 to insulate it from the upper layer.
Is formed, and a polycrystalline silicon film 69 is deposited so as to fill the inside of trench groove 65 and cover the surface of capacitor insulating film 67.

As shown in FIG. 18, first, an element isolation region is formed. A shallow trench (Shallow Trench) groove is formed by RIE, and the inside of the trench is filled with a TEOS film 70. A gate electrode 71 is formed by depositing a polycrystalline silicon film and patterning it into an electrode shape. Further, impurities are implanted using the gate electrode 71 as a mask, and the drain and source regions 7 are formed.
2 are formed.

Through the above-described steps, a transistor having a drain / source region 72 and a gate electrode 71, a polycrystalline silicon film 69 as an upper electrode and a diffusion layer 66 as a lower electrode, and a capacitor insulating between them. A semiconductor device provided with a capacitor having the film 67 for each memory cell is manufactured.

[0008]

However, in order to respond to the demand for further miniaturization in recent years, it has become difficult to secure the capacity of the capacitor by the above-mentioned conventional technology.

In view of the above circumstances, it is an object of the present invention to provide a semiconductor device capable of increasing the capacitance of a capacitor and a method of manufacturing the same.

[0010]

According to the present invention, there is provided a semiconductor device having a grooved cell capacitor, wherein the grooved cell capacitor is formed in a groove whose inner bottom surface is larger in diameter than the frontage.
A diffusion layer formed as one electrode inside the groove,
An insulating portion formed on the surface of the diffusion layer; and a first conductive film formed as the other electrode so as to fill the inside of the groove while being electrically insulated from the diffusion layer by the insulating portion. Wherein the insulating portion includes a second conductive film having an uneven surface, and an insulating film formed to cover the surface of the second conductive film.

Alternatively, in the semiconductor device according to the present invention, the groove type cell capacitor may be filled with a diffusion layer formed as one electrode inside the groove, and may be filled to a predetermined depth in a state where a gap exists inside the groove. The formed first conductive film, an insulating film formed to cover the surfaces of the first conductive film and the diffusion layer, and electrically insulated from the diffusion layer by the insulating film. And a second conductive film formed as the other electrode over the first conductive film.

Here, the groove type cell capacitor may be formed in a groove having a larger inner bottom surface diameter than the frontage.

According to the method of manufacturing a semiconductor device having a grooved cell capacitor of the present invention, a step of forming a trench having a diameter larger than the frontage on a surface of a semiconductor substrate; Forming a diffusion layer as an electrode; and forming a particulate first layer on an inner surface of the trench.
Forming an insulating film so as to cover the surfaces of the first conductive film and the diffusion layer; and forming a second conductive film as the other electrode so as to fill the inside of the trench groove. And a step of forming a film.

Alternatively, a method of manufacturing a semiconductor device according to the present invention comprises the steps of: forming a trench in a surface of a semiconductor substrate;
A step of forming a diffusion layer as one electrode inside the trench groove, and a step of forming a particulate first conductive film so as to fill the inside of the trench groove to a predetermined depth in the presence of a gap, Forming an insulating film so as to cover the surfaces of the first conductive film and the diffusion layer; and forming the first film in a state in which the insulating film is electrically insulated from the diffusion layer.
Forming a second conductive film as the other electrode on the conductive film.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. The method of manufacturing a semiconductor device according to the first embodiment of the present invention includes the steps shown in FIGS. 1 to 6 as the cross sections of the elements, respectively, and the semiconductor device according to the present embodiment is as shown in FIG. It has a simple cross-sectional structure.

First, as shown in FIG. 1, a silicon oxide film 12 having a thickness of 100 Å is formed on a surface of a semiconductor substrate 11 by a thermal oxidation method, and a CVD (Chemical Vapor Deposition) is formed on the surface. 25 by law
A silicon nitride film 13 is formed to a thickness of 00 Å, and a TEOS film 14 is deposited to a thickness of 7000 Å by CVD. A trench 15 is formed in the capacitor formation region by RIE.
In order to insulate the upper layer, the TEOS film 16 is formed as an interlayer insulating film only on the upper part of the inner wall of the trench groove 15, that is, only on the frontage.

Here, a method of forming the trench groove 15 so as to have a larger diameter at the bottom than the frontage as shown in FIG. 1 and further forming the TEOS film 16 only at the frontage of the trench groove 15 will be described.

First, a trench 15 having a depth smaller than that of a groove to be finally formed is formed by RIE. CVD
By the method, a TEOS film is deposited inside the trench 15. By RIE under conditions of high anisotropy, the trench 1
5 and a TEOS film on the semiconductor substrate 11
The film 14 is removed, and only the inner wall of the trench 15 becomes T
The EOS film 16 remains.

Next, the bottom and the inner wall of the trench 15 are etched by RIE under a highly isotropic condition. This etching is performed under such a condition that a region where silicon is exposed is removed and the TEOS film 16 is not removed. As a result, the bottom of the trench 15 and T
The inner wall excluding the frontage where the EOS film 16 is formed is removed. As a result, the diameter of the bottom portion of the trench groove 15 becomes larger than the frontage, and the TEOS is provided only at the frontage of the trench groove 15.
A film 16 will be formed.

As shown in FIG. 2, for example, arsenic (As) is diffused on the inner wall of the trench 15 by an air layer diffusion method to form an impurity diffusion layer 17. Further, conductive particles 18 made of polycrystalline silicon are formed on the bottom and inner walls of trench 15 and on the surfaces of TEOS films 14 and 16. As a method for forming such conductive particles 18, for example, arsenic (As) contained in polycrystalline silicon is used.
There is a method of increasing the concentration of impurities such as oxygen, oxygen (O), and carbon (C). If the impurity concentration is high, the fluidity of silicon becomes low, so that a particulate polycrystalline silicon film is formed. More specifically, the conductive particles 18 can be formed by using As-Doped polycrystalline silicon having a high arsenic concentration of 2 × 10 ²⁰ (1 / cm ³ ).

Next, as shown in FIG. 3, a capacitor insulating film 19 is formed so as to cover the inner wall of trench 15. The capacitor insulating film 19 may be formed by forming a silicon nitride (SiN) film to a thickness of 75 angstroms by, for example, a CVD method, and further forming a silicon oxide (SiO ₂ ) film to a thickness of 25 angstroms by a CVD method. .

As shown in FIG. 4, the TEO film 16 on the TEOS film 16 near the opening of the trench 15 and the TEO film
The conductive particles 18 and the capacitor insulating film 19 existing on the S film 14 are removed by etching.

As shown in FIG. 5, a polycrystalline silicon film 20 is deposited as a conductive film for an upper electrode to a thickness of 5000 angstroms by a CVD method.

The subsequent steps are the same as in the above-described conventional manufacturing method. As shown in FIG. 6, a shallow trench groove is formed by RIE, and the inside is filled with a TEOS film 21. A polycrystalline silicon film is deposited and patterned into an electrode shape to form a gate electrode 22. Using the gate electrode 22 as a mask, an impurity is implanted to form a drain and source region 23.

Through the above steps, the transistor having the drain and source regions 23 and the gate electrode 22 and the polycrystalline silicon film 2 as the upper electrode are formed.
A semiconductor device having a capacitor for each memory cell having 0, an impurity diffusion layer 17 as a lower electrode, and a capacitor insulating film 19 for insulating between them is manufactured.

In this embodiment, the trench 1
There is a conductive particle 18 covered by a capacitor insulating film 19 that insulates between the lower electrode and the upper electrode on the inner wall of the element 5. Here, the capacitance C is determined by [epsilon] * area between electrodes / distance between electrodes. Accordingly, the surface area between the lower electrode and the upper electrode is increased as compared with the case where the inner surface of the trench 65 is flat as in the conventional device shown in FIG. Further, since the diameter of the inner bottom surface of the trench groove 15 is formed larger than the frontage, the area of the inner side surface of the trench groove 15 is further increased as compared with the case where the cylindrical trench groove is formed as in the related art. The capacity of the capacitor increases. Therefore, according to the present embodiment, a capacitor having a larger capacitance can be formed even when a trench having the same width as that of the conventional trench is formed.

Next, a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS. 7 to 12, and a sectional structure of the device according to the present embodiment is shown in FIG.

As in the first embodiment, as shown in FIG. 7, a silicon oxide film 32 having a thickness of 100 Å is formed on the surface of a semiconductor substrate 31 by a thermal oxidation method.
Is formed, and a silicon nitride film 33 having a thickness of 2500 Å is formed by the CVD method.
The TEOS film 34 is deposited to a thickness of 7000 angstroms by the method. In the capacitor formation region, a trench groove 35 having a larger diameter at the bottom than the frontage is formed by RIE as in the first embodiment, and the trench groove 3 is formed.
The TEOS film 36 is formed as an interlayer insulating film only at the frontage of No. 5.

As shown in FIG. 8, for example, arsenic is diffused into the inner wall of the trench 35 by an air layer diffusion method to form an impurity diffusion layer 37.

As shown in FIG. 9, inside the trench 35,
Polycrystalline silicon is deposited as the particulate conductive film 38.
Here, the diameter of the particulate conductive film 38 is larger than the conductive particles 18 in the first embodiment. Such a particulate conductive film 38 can be formed by setting a longer time for depositing the conductive particles 18 according to the first embodiment. Alternatively, by setting the temperature higher than in the first embodiment, the diameter of the particles can be increased. Further, in the vicinity of the frontage of the trench groove 35 and on the surface of the TEOS film 34 on the semiconductor substrate 31, the polycrystalline silicon film 39 is not deposited in the form of particles but deposited like a normal film. Here, even when the conductive particles 18 having a small particle diameter are formed as in the first embodiment, the particulate conductive film 38 having a large particle diameter is formed as in the second embodiment. In this case, the controllability of the film thickness is easier.

Next, the polycrystalline silicon film 39 is etched to form a trench 35 as shown in FIG.
The surface of the internal particulate conductive film 38 is exposed. As a result, the inside of the trench groove 35 is filled with the particulate conductive film 38 in a state where a gap exists to a certain depth.

As shown in FIG. 11, the trench 35
, The surface of the TEOS film 36 formed at the opening of the trench 35, and the surface of the TEO film
Capacitor insulating film 40 is formed to cover the surface of S film 34. As in the first embodiment, the capacitor insulating film 40 is formed by forming a silicon nitride (SiN) film to a thickness of 75 Å by CVD, for example, and further forming a silicon oxide (SiO ₂ ) film by CVD. It may be formed with a thickness of 25 Å.

As shown in FIG. 12, a polycrystalline silicon film 41 as an upper electrode is formed in the trench groove 35 near the opening not filled with the particulate conductive film 38 and on the surface of the TEOS film 34 on the semiconductor substrate 31. Is deposited by a CVD method. Thereafter, as in the case of the first embodiment shown in FIG. 6, an element isolation region and a transistor are formed.

According to the present embodiment, a capacitor having a large surface area formed so as to cover the particulate conductive film 38 is provided between the polycrystalline silicon film 41 as the upper electrode and the impurity diffusion layer 37 as the lower electrode. Since it is insulated by the insulating film 40, the surface area between the upper electrode and the lower electrode increases. Therefore, when the dimensions of the trench grooves are the same, a capacitor having a larger capacity than the conventional one can be formed.

The above embodiment is merely an example, and does not limit the present invention. For example, in each of the first and second embodiments, a trench having a larger diameter at the bottom than at the frontage is formed. However, the present invention can be similarly applied to a case where a trench having a cylindrical shape is formed as usual. For example, as shown in FIG. 13, a cylindrical trench groove 52 is formed in a semiconductor substrate 51, and an impurity diffusion layer 53 is formed on an inner wall of the groove 52.
Even when the particulate conductive film 54 is deposited inside the capacitor 2, a capacitor having a larger capacity than before can be formed.

[0036]

As described above, according to the semiconductor device and the method of manufacturing the same of the present invention, a capacitance is formed in a trench having a larger inner bottom surface diameter than a frontage, and one electrode and the other electrode are connected to each other. The surface area of the insulating film is increased by using a particulate conductive film, so that a capacitor having a larger capacitance can be obtained even if the opening size is the same as that of the conventional trench.

Alternatively, according to the semiconductor device and the method of manufacturing the same of the present invention, the inside of the trench is filled with a particulate conductive film to a predetermined depth and the surface is covered with an insulating film, so that the trench is formed on the conductive film. Since the surface area between the one electrode and the other electrode formed inside the trench is increased, it is possible to obtain a capacitor having a large capacitance.

[Brief description of the drawings]

FIG. 1 is an element cross-sectional view showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention for each process.

FIG. 2 is an element cross-sectional view showing a method of manufacturing the semiconductor device according to the first embodiment for each step;

FIG. 3 is an element cross-sectional view showing a method of manufacturing the semiconductor device according to the first embodiment for each step;

FIG. 4 is an element cross-sectional view showing a method of manufacturing the semiconductor device according to the first embodiment for each step;

FIG. 5 is an element cross-sectional view showing a method of manufacturing the semiconductor device according to the first embodiment for each step;

FIG. 6 is an element cross-sectional view showing a method of manufacturing the semiconductor device according to the first embodiment for each step;

FIG. 7 is an element cross-sectional view illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention for each process.

FIG. 8 is an element cross-sectional view showing a method of manufacturing the semiconductor device according to the second embodiment for each step;

FIG. 9 is an element cross-sectional view showing a method of manufacturing the semiconductor device according to the second embodiment for each step;

FIG. 10 is an element cross-sectional view showing a method of manufacturing the semiconductor device according to the second embodiment for each step;

FIG. 11 is an element cross-sectional view showing a method of manufacturing the semiconductor device according to the second embodiment for each step;

FIG. 12 is an element cross-sectional view showing a method of manufacturing the semiconductor device according to the second embodiment for each step;

FIG. 13 is an element cross-sectional view showing a modified example of the second embodiment.

FIG. 14 is an element cross-sectional view showing a conventional method of manufacturing a semiconductor device for each process.

FIG. 15 is an element cross-sectional view showing a method of manufacturing the same semiconductor device for each process;

FIG. 16 is an element sectional view showing the method of manufacturing the same semiconductor device for each process;

FIG. 17 is an element cross-sectional view showing the manufacturing method of the semiconductor device for each process;

FIG. 18 is an element sectional view showing the method of manufacturing the same semiconductor device for each process;

[Explanation of symbols]

 11, 31, 51 Semiconductor substrate 12, 32 Silicon oxide film 13, 33 Silicon nitride film 14, 16, 21, 34, 36, 55 TEOS film 15, 35, 52 Trench groove 17, 37, 53 Impurity diffusion layer 18 Conductivity Particles 19, 40 Capacitor insulating film 20, 39, 41 Polycrystalline silicon film 22, 56 Gate electrode 23, 57 Drain, source region 38, 54 Particulate conductive film

Claims (5)

[Claims] 1. A semiconductor device having a grooved cell capacitor, wherein the grooved cell capacitor is formed in a groove having a larger inner bottom surface diameter than a frontage, and is formed as one electrode inside the groove. A diffusion layer, an insulating portion formed on the surface of the diffusion layer, and a second electrode formed as the other electrode so as to fill the inside of the groove while being electrically insulated from the diffusion layer by the insulating portion. A second conductive film having unevenness on its surface;
And an insulating film formed so as to cover the surface of the second conductive film. 2. A semiconductor device having a groove-type cell capacitor, wherein the groove-type cell capacitor is provided with a diffusion layer formed as one electrode inside a groove, and in a state where a gap exists inside the groove. A first conductive film in the form of particles formed so as to fill the depth, an insulating film formed so as to cover the surfaces of the first conductive film and the diffusion layer; And a second conductive film formed as the other electrode on the first conductive film while being electrically insulated. 3. The semiconductor device according to claim 2, wherein said groove type cell capacitor is formed in a groove having a larger diameter at an inner bottom surface than at a frontage. 4. A method for manufacturing a semiconductor device having a grooved cell capacitor, comprising: forming a trench having a larger inner diameter than a frontage on a surface of a semiconductor substrate; and forming one electrode in the trench. Forming a diffusion layer, forming a particulate first conductive film on the inner surface of the trench, and forming an insulating film to cover the surface of the first conductive film and the diffusion layer. Forming a second conductive film as the other electrode so as to bury the inside of the trench groove. 5. A method for manufacturing a semiconductor device having a grooved cell capacitor, comprising: forming a trench in a surface of a semiconductor substrate; and forming a diffusion layer as one electrode inside the trench. A step of forming a particulate first conductive film so as to fill the trench groove with a gap to a predetermined depth, and an insulating film covering the first conductive film and the surface of the diffusion layer Forming a second conductive film as the other electrode on the first conductive film while being electrically insulated from the diffusion layer by the insulating film. A method for manufacturing a semiconductor device.