JPH11345253A - Logic synthesizing device, logic synthesizing method and medium recording logic synthetic program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To remarkably reduce the time needed for logical synthesis by making a logic synthesizing means synthesize a logic circuit from description including the description of a block that is subjected to logical compression with a logical compressing means. SOLUTION: A syntax analyzing part 21 reads RTL description that becomes an object of syntax analysis from a file and analyzes the syntax of the description. A logic compressing part 22 before synthesis extracts a combinational circuit from the read RTL and performs logic compression. A logical structure deciding part 23 estimates and constructs a logic circuit structure while referring to an internal library to the RTL undergoing the logic compression. An implementation deciding part 24 decides implementation based on a design restriction condition. A technology mapping part 25 converts a logic circuit that is synthesized by using the internal library into a library designated by a user. A violation place correcting part 26 corrects design restriction violation place, etc. A logic compressing part 27 after synthesis compresses logic after logical synthesis.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to optimization of a logic circuit obtained by logically synthesizing a hardware description language.
In particular, the present invention relates to a logic synthesis device that performs optimization before logic synthesis, a logic synthesis method, and a medium that stores a logic synthesis program.

[0002]

2. Description of the Related Art In recent years, as semiconductor integrated circuits have become denser and more multifunctional, the circuit scale has tended to increase, and the time required for circuit design has also increased. As one of the methods for reducing the time required for the circuit design, there is a method of designing the circuit using a hardware description language (HDL).

FIG. 15 is a flowchart for explaining a processing procedure of logic synthesis in a conventional logic synthesis apparatus. First, the RTL (Register Tra
nsfer level) is read from the file, and the syntax of the description is analyzed (S101). In this syntax analysis, if there is a grammatically incorrect description or a description that cannot be handled by the logic synthesizer, an error message is displayed and the processing is stopped. If there is no description that cannot be handled by the logic synthesis device, the process proceeds to step S102.

FIG. 16 shows an RTL description in Verilog-HDL as an example of a hardware description language. In the first line, a macro cell comb_test is defined by a module statement. This comb_
test is the output signal h and the input signals a, b, c and d
And In the second row, the output signal h is defined. In the third to sixth rows, input signals a to d are defined.

In lines 7 and 8, wiring type variables (wire type) h and g are defined as intermediate variables. Also,
In line 9, the intermediate variable h is the input signal a and the intermediate variable g
Is defined as the logical product of In the tenth line, it is defined that the intermediate variable g is a logical sum of (logical product of input signals a and b) and (logical product of input signals c and d). In addition, in the last line,
Macro cell comb_te by endmodule statement
This indicates that the definition of st is over. Note that there is no grammatical error in the description shown in FIG.

Returning to the flowchart of FIG. 15, the description will be continued below. The logic circuit structure is estimated and constructed for the RTL read in step S101 with reference to the internal library. In other words, operators such as & (logical product), | (logical sum), and! (Negative) defined in RTL are simply mapped to AND, OR, and NOT cells by referring to the internal library. Is done.

FIG. 17 shows a logic circuit synthesized from the RTL description shown in FIG. In FIG. 17, FIG.
Corresponds to the logical structure deduced from the description of. 17 corresponds to the logical structure deduced from the description of FIG.

On the other hand, + (addition) and-other than logical operators
Arithmetic operators represented by (subtraction), * (multiplication), / (division) and the like are mapped to the operation unit cells of the internal library for which the implementation is not selected. In the edge trigger design method, a register (defined as a register type variable on the RTL and interpreted as a storage element in a syntax interpretation) is provided with a level-sensitive flip-flop (hereinafter, referred to as F / F) cell. In the method, the data is converted into a latch (hereinafter referred to as Latch) cell.

FIG. 18A shows an example of an RTL including a description of an arithmetic operator and a storage element, and FIG. 18B shows a logical structure synthesized from the description. FIG.
As shown in (a), a macro cell sample_datapath is defined by a module statement in the first line. An 8-bit output signal out_dat is defined in the second row, and 7-bit output signal out_dat is defined in the third row.
Bit input signals in1, in2 and add_val
Is defined. In the fourth and fifth rows, input signals sel_in and clk are defined, respectively.

In line 6, a register type (reg type)
An 8-bit output signal out_dat is defined as a variable. In the seventh row, a wiring type (wire type)
A 7-bit input signal in_dat is defined as a variable.

The eighth line describes that either the signal in1 or the signal in2 is selected by the signal sel_in and output as the wiring variable in_dat. Further, in the ninth row, a 7-bit wiring type variable in_dat and a 7-bit input signal add_val
Are described, the value is held at the positive edge of the input signal clk, and is output as the register type variable out_dat.

FIG. 18B shows the RT shown in FIG.
3 shows a logical structure synthesized from L. FIG. 18 (a)
The logical structure of the selector cell shown in FIG. 18B is changed from the description shown in FIG.
The logical structure of the storage element F / F shown in FIG.
The logic structure of the arithmetic operation cell (adder) shown in FIG. 18B is determined from the description shown in FIG. However, at the stage where the logical structure shown in FIG. 18B has been determined, the implementation for determining the implementation method of the adder estimated from the arithmetic operator has not yet been determined, so that it is treated as a black box. Will be

Returning again to the flowchart shown in FIG. 15, an implementation is selected based on design constraints (S103). In step S102, since the implementation of the arithmetic operation cell (adder) has not been selected yet, the internal logical structure of the arithmetic operation cell (adder) is set based on the externally applied design constraint (speed or area priority is set). Is determined.

For example, in the case of the adder shown in FIG.
ok The logic circuit structure corresponding to the Ahead type adder, and the logic circuit structure corresponding to the Ripple Carry type adder given the area-first design constraint condition are AND, OR,
It is configured using a simple operation cell such as NOT. Note that at the final stage of this implementation selection, the read RTL description is an
Simple operation cells such as D, OR, NOT, etc., and the sequential circuit portion are represented by F / F or Latch storage elements.

Next, the logical structure determined by using the internal library of the logic synthesizer by the above processing is converted into a library specified by a user (a library classified by process, technology, and design rule. For example,
CMOS (Complementary Metal Oxide Semiconductor)
0.8 μm three-layer Al corresponds to this. ) Is converted into a logic circuit (S104). At the time of the conversion of the logic circuit, the logic structure represented by an internal cell that does not exist in the user-specified library is replaced with an equivalent logic circuit using the user-specified library. This conversion to an equivalent logic circuit is called technology mapping.

FIGS. 19A and 19B are diagrams showing an example of this technology mapping. FIG.
When the logic circuit (8-input AND element) shown in (a) is not in the user-specified library, as shown in FIG. 19B, two 4-input AND elements and one 2-input AND are obtained by technology mapping. Converted to elements. Further, an output signal out1 is automatically generated between the four-input AND element and the two-input AND element, and an output signal out2 is automatically generated between the four-input AND element and the two-input AND element. Thus, with technology mapping,
An equivalent circuit is constructed so that the number of elements (the number of cells) is minimized, and the equivalent circuit is allocated to the logic circuit.

Returning to the flowchart shown in FIG. 15, the description will be continued. Next, the design constraint violation part and the design rule violation part are corrected (S105). As a specific design constraint violation given from the outside, for example, a case in which a constraint on an operating frequency of a circuit or a constraint on an area of a circuit is violated. Further, as a violation of the design rule, for example, a setup time, a hold time, or a shortage of cell driving capability in the storage element corresponds to this.

Finally, the logic circuit is compressed (S1).
06). Logical compression is performed by applying a Boolean axiom axiom or theorem within a range that does not violate the design constraints and design rules performed in step S105. For example, in the case of the logic circuit shown in FIG. 20A, the relationship between input signals A and B is determined by connecting two NOT cells in series (2 in a Boolean algebra).
Double negation). Here, signals A and B
(For example, if the signal B is connected to the input data of the sequential circuit at the next stage, it affects the setup time and the hold time) and the design rule conditions (for example, As long as it does not conflict with the delay time, the function expression is replaced by a single driver cell as shown in FIG. further,
As shown in FIG. 20C, the function is replaced with a functional expression by direct connection of wiring. All of these permutations are based on the Boolean algebra theorem.

From the logic circuit synthesized by the above processing, netlist data in the format specified by the user is generated and output, and the processing is terminated. If the logical compression cannot be performed within the range that does not violate the design constraint conditions and the design rule conditions in step S106, step S1
The netlist data is generated and output from the logic circuit synthesized up to 05, and the process ends.

[0020]

SUMMARY OF THE INVENTION Generally, Verilo
g-HDL (IEEE-1364) or VHDL
A logic circuit obtained by logically synthesizing a hardware description language such as (IEEE-1076) is more difficult to perform layout (placement and wiring) work than a logic circuit created by manual input using a logical connection diagram or the like. It is said to be. One of the reasons is that description is made so as to satisfy only functions without assuming a logic circuit after synthesis. That is, when synthesizing a logic circuit from the input hardware description language due to lack of processing capability of the logic synthesis device,
This is because the optimization of the logic circuit is not performed sufficiently.

As described above, a program described without considering the synthesized logic circuit includes a redundant logic description,
In a logic circuit synthesized by a conventional logic synthesis device having insufficient processing capability, a layout index represented by pin-pair / gate or the like does not extremely deteriorate. There was a problem. In addition, this pin-pair / g
“ate” means a value obtained by dividing the number of input terminals connected to the output terminal by the area of the gate, and indicates that if this value is large, the layout becomes difficult.

Further, in the conventional logic synthesizer, since the optimization processing of the logic structure is performed at the last stage after the logic synthesis, the logic compression is performed while the redundant cells and wiring due to the logic structure remain. The process up to step S106) is performed, and there is a problem that it takes a lot of time to optimize the logical structure.

The present invention has been made to solve the above problems, and a first object of the present invention is to provide a logic synthesizing apparatus capable of greatly reducing the time required for logic synthesis. .

A second object is to provide a logic synthesis method capable of greatly reducing the time required for logic synthesis.

A third object is to provide a medium recording a logic synthesis program capable of greatly reducing the time required for logic synthesis.

[0026]

According to a first aspect of the present invention, there is provided a logic synthesizing device for extracting a description of a block including only a combinational circuit from a description in a hardware description language, and an extraction unit. And a logic synthesizing unit for synthesizing a logic circuit from the description including the description of the block logically compressed by the logical compression unit.

The logic synthesis means synthesizes the logic circuit from the description including the description of the block logically compressed by the logic compression means, so that the time required for the logic synthesis can be reduced.

According to a second aspect of the present invention, there is provided a logic synthesis device comprising: a logic structure determining unit for determining a logic circuit structure based on a description in a hardware description language by referring to an internal library; Implementation changing means for changing the implementation of the description for which the logic circuit structure has not been determined in accordance with an instruction from the user, and changing the logic circuit structure and the implementation changing means determined by the logic structure determining means Logic synthesis means for synthesizing a logic circuit based on the implemented implementation.

Since the implementation changing means changes the implementation according to an instruction from the user, it becomes possible to obtain a desired logic circuit in a short time, and the processing efficiency of the logic synthesis device is improved.

According to a third aspect of the present invention, there is provided a logic synthesizing apparatus, comprising: extracting means for extracting a description of a block including only a combinational circuit from a description in a hardware description language; and combining only the combinational circuit extracted by the extracting means. Logical compression means for logically compressing the description of the block including the logical block, and a logical structure for determining the logical circuit structure based on the description including the description of the block logically compressed by the logical compression means by referring to the internal library Determining means, implementation changing means for changing an implementation of a description whose logical circuit structure has not been determined by the logical structure determining means in accordance with an instruction from a user, and a logic circuit determined by the logical structure determining means Implementation changed by structure and implementation change means Based on the emission, and a logic synthesizing means for synthesizing a logic circuit.

Since the implementation changing means changes the implementation in accordance with an instruction from the user, it is possible to obtain a desired logic circuit in a short time in addition to the effect of the first aspect. Processing efficiency is improved.

The logic synthesizing device according to claim 4 is the logic synthesizing device according to claim 1 or 3, wherein the extracting means is a variable extracting means for extracting a variable from a description in a hardware description language. Extracted by the variable extracting means until one of a variable declared as an input terminal, a variable interpreted as an output signal of the storage element, and a variable including the output signal of the arithmetic operation circuit on the right side. Combination circuit extracting means for extracting a combination circuit by sequentially developing variables.

Since the combinational circuit extracting means extracts the combinational circuit by expanding the variables until the combinational expansion becomes impossible, the combinational circuit can be extracted more appropriately.

According to a fifth aspect of the present invention, there is provided a logic synthesis method comprising the steps of extracting a description of a block including only a combinational circuit from a description in a hardware description language; Compressing, and synthesizing a logic circuit from the description including the description of the logically compressed block.

Since the logic circuit is synthesized from the description including the description of the logically compressed block, the time required for the logic synthesis can be reduced.

According to a sixth aspect of the present invention, in the logic synthesis method, a logic circuit structure is determined based on a description in a hardware description language by referring to an internal library, and a description of the description in which the logic circuit structure is not determined is provided. The method includes a step of changing an implementation according to an instruction from a user, and a step of synthesizing a logic circuit based on the determined logic circuit structure and the changed implementation.

Since the implementation is changed in accordance with an instruction from the user, a desired logic circuit can be obtained in a short time, and the processing efficiency of logic synthesis is improved.

The logic synthesizing program recorded on the medium according to claim 7 includes a step of extracting a description of a block including only a combinational circuit from a description in a hardware description language, and includes only the extracted combinational circuit. Logically compressing the description of the block; and synthesizing a logic circuit from the description including the description of the logically compressed block.

Since the logic circuit is synthesized from the description including the description of the logically compressed block, the time required for the logic synthesis can be reduced.

In the logic synthesizing program recorded on the medium according to the present invention, a logic circuit structure is determined based on a description in a hardware description language by referring to an internal library, and the logic circuit structure is determined. The method includes a step of changing the implementation of the description that has not been made in accordance with an instruction from a user, and a step of synthesizing a logic circuit based on the determined logic circuit structure and the changed implementation.

Since the implementation is changed according to an instruction from the user, a desired logic circuit can be obtained in a short time, and the processing efficiency of logic synthesis is improved.

[0042]

FIG. 1 is a diagram showing an example of the external appearance of a logic synthesis device according to the present invention. The logic synthesis device includes a computer main body 1, a graphic display device 2, a magnetic tape device 3 on which a magnetic tape 4 is mounted, a keyboard 5, a mouse 6, a CD-ROM (Compact Disc-Read Only Memory).
) 8 includes a CD-ROM device 7 to be mounted, and a communication modem 9. The logic synthesis program is supplied by a storage medium such as the magnetic tape 4 or the CD-ROM 8.
The logic synthesis program is executed by the computer main body 1, and the operator performs logic synthesis by operating the keyboard 5 or the mouse 6 while watching the graphic display device 2. The logic synthesis program may be supplied from another computer to the computer main body 1 via a communication line and a communication modem 9.

FIG. 2 is a block diagram showing a configuration example of the logic synthesizing device of the present invention. Computer body 1 shown in FIG.
Is a CPU (Central Processing Unit) 10 and ROM
(Read Only Memory) 11, RAM (Random Access Memo)
ry) 12 and the hard disk 13. CPU10
Performs processing while inputting and outputting data to and from the graphic display device 2, magnetic tape device 3, keyboard 5, mouse 6, CD-ROM device 7, communication modem 9, ROM 11, RAM 12, or hard disk 13.
The logical synthesis program recorded on the magnetic tape 4 or the CD-ROM 8 is temporarily transferred to the hard disk 1 by the CPU 10 via the magnetic tape device 3 or the CD-ROM device 7.
3 is stored. The CPU 10 performs logic synthesis by appropriately loading a logic synthesis program from the hard disk 13 into the RAM 12 and executing the program.

The logic synthesizer in each embodiment of the present invention will be described below. The appearance of the logic synthesizer shown in FIG. 1 and the configuration block diagram of the logic synthesizer shown in FIG. 2 are common to each embodiment. is there.

[First Embodiment] FIG. 3 is a block diagram showing a schematic configuration of a logic synthesizing apparatus according to a first embodiment of the present invention. The logic synthesizing apparatus includes a syntax analysis unit 21 for reading RTL and analyzing the syntax of the description, a pre-synthesis logic compression unit 22 for performing logic compression based on RTL before logic synthesis, and an internal library. A logical structure determining unit 23 for determining a logical circuit structure using the same, an implementation selecting unit 24 for selecting an implementation based on design constraints, and a logical structure determined using an internal library. A technology mapping unit 25 for replacing with a logical structure using a library specified by a user, a violating part correcting unit 26 for correcting violating parts of design constraints and design rules, and compression of a logic circuit after logic synthesis. And a post-synthesis logical compression unit 27.

FIG. 4 is a flowchart for explaining a processing procedure of the logic synthesizing apparatus according to the first embodiment of the present invention. First, the syntax analysis unit 21 reads a function description (RTL description) to be subjected to logic synthesis from a file and analyzes the syntax of the description (S11). In this syntax analysis, if there is a grammatically incorrect description or a description that cannot be handled by the logic synthesizer, an error message is displayed and the processing is stopped. If there is no description that cannot be handled by the logic synthesis device, the process proceeds to step S12. Note that this process
Since the process is the same as the process of step S101 in FIG. 15, detailed description will not be repeated.

Next, the pre-synthesis logical compression section 22 extracts a combinational circuit from the RTL read in step S11 and performs logical compression on the combinational circuit (S1).
2). Details of the logical compression before the logical synthesis will be described later.

Next, the logical structure determination unit 23 determines in step S
The logic circuit structure is estimated and constructed with reference to the internal library for the RTL subjected to the logic compression in S12 (S13). Note that this processing is the same as the processing in step S102 in FIG. 15, and thus detailed description will not be repeated.

Next, the implementation determining unit 24
Selects an implementation based on design constraints (S14). In step S13, the internal logical structure of an arithmetic operation cell whose implementation is not yet selected is determined based on externally applied design constraint conditions (speed priority or area priority is set). You. Note that this processing is the same as the processing in step S103 in FIG. 15, and thus detailed description will not be repeated.

Next, the techno lodge mapping unit 25
The logic circuit synthesized using the internal library of the logic synthesis device by the above processing is converted into a logic circuit using a library specified by the user (S15). At the time of the conversion of the logic circuit, the logic structure represented by an internal cell that does not exist in the user-specified library is replaced with an equivalent logic circuit using the user-specified library. Note that this process
Since the process is the same as that in step S104 in FIG. 15, detailed description will not be repeated.

Next, the violating part correcting unit 26 corrects the violating part of the design constraint and the violating part of the design rule (S1).
6). This process is the same as the process in step S105 in FIG. 15, and thus detailed description will not be repeated.

Finally, the post-synthesis logic compression section 27 performs compression of the logic after the logic synthesis (S17). Logic compression is performed by applying a Boolean axiom axiom or theorem within a range that does not violate the design constraints and design rules performed in step S16. This process is the same as the process in step S106 in FIG. 15, and thus detailed description will not be repeated.

From the logic circuit synthesized by the above processing, netlist data in the format specified by the user is generated and output, and the processing is terminated. If the logical compression cannot be performed within the range that does not violate the design constraint conditions and the design rule conditions in step S17, step S16
The netlist data is generated and output from the logic circuit synthesized up to and the processing is terminated.

FIG. 5 is a flowchart for explaining the processing procedure of step S12 in FIG. 4 in more detail.
First, only the combinational circuit tree is extracted from the RTL after the syntax analysis is performed (S21). Details of this processing will be described later.

Next, the extracted combinational circuit tree (RT
L) is converted into a Boolean expression (S22). For example,
In the case where the combinational circuit tree extracted in step S21 is the description shown in FIG. 6A, first, an expression is substituted into an expression in order to convert the description constituting the combinational circuit tree into a description using a single expression. The single equation shown in FIG. 6 (b) is obtained. The logical operator & in the description shown in FIG.
(Logical AND), | (logical OR) and! (Negative N
OT) are replaced by (•), (+) and (￣), which are operators of the Boolean equation, respectively. Thus, the combinational circuit tree shown in FIG.
It is replaced by the Boolean equation shown in FIG.

Next, it is determined whether or not there is a common term on the right side of the Boolean expression replaced in step S22 (S23). Prior to this determination, a table shown in FIG. 7 is created. This table is created from the Boolean equation shown in FIG. 6C, and shows the count numbers of the variables a to d on the right side. As shown in this table,
If there is a variable whose count number is 2 or more, since there is a common term on the right side of the Boolean expression (S23, Yes), it is determined that the combinational circuit tree can be optimized, and the process proceeds to step S24. If all the counts of the variables are less than 2 in step S23, there is no common term on the right side of the Boolean equation (S23, No). The conversion process ends. Note that the processing in this step is the same as the optimization processing for wiring with two or more pin-pairs described in the related art.

Next, optimization is performed on the Boolean algebraic expression determined to be optimizable in step S23 using the Boolean algebra theorem and axiom (S24). The process of optimizing the Boolean equation will be described with reference to FIG. The expression of FIG. 8A shows a Boolean expression obtained by substituting Expression ′ of FIG. An expression is obtained by using the Boolean algebra theorem (distribution rule) in the expression. Furthermore, an expression is obtained by using the Boolean algebra theorem (distribution rule) in the expression. In the right side of the expression,
By using the Boolean axiom (AND operation),
Since a · a and a are equivalent, an equation is obtained. Finally, an equation is obtained by using the Boolean algebra theorem (distribution rule) in the equation. Note that FIG.
8C shows the count number of each variable on the right side of the equation, and FIG. 8C shows the count number of each variable on the right side of the equation.
The optimization process is terminated when the count number of each variable becomes minimum.

Next, in step S24, a process of returning the logically compressed Boolean expression to RTL is performed, and the RTL before logical compression and the RTL after logical compression are displayed on the graphic display 2 and the like. To the effect that the description is to be optimized (S25).

Finally, the RTL before the logical compression is changed to the RTL after the logical compression in step S24, and the optimization processing of the combinational circuit is completed (S26). In other devices that implement logic synthesis, the function expression in the input original hardware description language and the function expression after the optimization processing are performed so that the optimum logic synthesis result can be obtained. May be output as a pair.

FIG. 9 is a flowchart for explaining details of the extraction of the combinational circuit tree shown in step S21 of FIG. First, all variables are extracted from the function description parsed in step S11 of FIG.
31).

One variable to be processed is selected from the group of variables extracted in step S31 (S3).
2). At this time, if there is no next candidate to select (S33, Y
es), the process ends (S35). If there is a next candidate to be selected (S33, No), it is determined whether or not the selected candidate is declared as an output terminal (S34).
As a method of this determination, for example, when the hardware description language is Verilog-HDL, the declaration is made using a special declarator (output) as shown in FIG. It is possible to determine whether or not the variable is an output terminal by collating the variable being set.

In step S34, if the selection candidate (trace target candidate variable) is declared as an output terminal (S34, Yes), the process proceeds to step S38. If the selection candidate is not declared as an output terminal (S3
4, No), it is determined whether or not the variable is one term of the right side of the condition determination expression (S36). As this determination method, for example, when the hardware description language is Verilog-HD
In the case of L, if sentence or assass as shown in FIG.
Since the variable is defined using a condition determination expression such as a ternary operation definition using an "ign" statement, if the variable is defined as a term on its right side, it is determined as a candidate for a variable constituting a combinational circuit tree. .

If it is determined in step S36 that the variable is a term on the right side of the conditional expression (S36, Ye
s), and proceed to step S38. On the other hand, if the variable is not determined to be a member of the right side of the condition determination expression (S36, N
o), it is determined whether or not the variable is one term on the right side of the expression using the arithmetic operator (S37). As the determination method, + (addition),-(subtraction), * (multiplication), / (division)
It is determined whether or not it is defined as one term on the right side of the expression including the arithmetic operator represented by.

In step S37, if the variable is defined as one term on the right side including the arithmetic operator (S3
7, Yes), and proceeds to step S38. If the variable is not defined as a term on the right side including the arithmetic operator (S37, No), the processing of the variable is stopped because the combinational circuit tree structure cannot be expanded, and the process returns to step S32 to return to the next candidate. Select a variable.

In step S38, it is determined whether the variable is not interpreted as a storage element in grammar. For example, if the hardware description language is Verilog-HDL
In the case of, it is determined whether the variable is defined as a register type (reg type) variable or a wiring type (wire type) variable. If the variable is defined as a wiring type variable, it is determined that the variable is an output of the combinational circuit and is not interpreted as a storage element, and the process proceeds to step S39.

If the variable is defined as a register type variable, an "always" statement in which the operation of the variable is defined is interpreted. For example, FIG.
As shown in the equation (a), when the variable out_dat does not change in any of the combinations of changes in the input signal, that is, when the value of the variable out_dat is sometimes held, the variable is stored. The variable is interpreted as the output of the element (S38, No), the processing of the variable is stopped because the combinational circuit tree cannot be expanded, and the process returns to step S32 to select the next candidate variable. If the variable always changes in all combinations of changes in the input signal, that is, if the value of the variable is not held, the variable is interpreted as the output of the combinational circuit (S38,
Yes), and proceed to step S39.

If it is determined in step S38 that the variable is not the output of the storage element, it can be interpreted as a variable defined for realizing the output of the combinational circuit. Here, in order to perform a backtrace of the combinational circuit tree structure, the variable is replaced with the right side (variable group and various operators) of the expression defining the function operation of the variable (S39). By sequentially repeating this processing, the expansion processing is performed until the logical tree structure cannot be expanded. The following cases can be cited as cases in which this expansion is impossible.

(1) It is defined as an input signal. (2) An output signal of the storage element.

(3) The output signal of the combinational circuit is the input signal to the macro element constituting the data path.

Next, backtrace processing of each variable constituting the logical expression developed in step S39 is performed (S40 to S46). First, one variable is selected from the variable group included in the developed logical expression, and preprocessing of the back trace processing is performed (S40).

At this time, if there is no next candidate to select (S4
1, Yes), returning to step S32 and repeating the following processing. If there is a next candidate to be selected (S41, N
o), it is determined whether the selection candidate is declared as an input terminal (S42). As this determination method, for example, the hardware description language is Verilog-HDL
In the case of (a), a special declarator (i
nput), the input
By collating the variable defined by the t statement, it can be determined whether the variable is an input terminal.

In step S42, if the selection candidate (trace target candidate variable) is declared as an input terminal (S42, Yes), the process proceeds to step S38. If the selection candidate is not declared as an input terminal (S4
2, No), it is determined whether or not the variable is grammatically interpreted as a storage element. This determination method is performed in step S3.
8, the detailed description will not be repeated.

If it is determined in step S43 that the variable is not the output of the storage element (S43, Ye
s), and proceed to step S45. If the variable is not interpreted as a storage element (S43, No), it is determined whether it is a data path circuit or a control circuit. The data path circuit refers to a circuit through which a normal data bus propagates, and a circuit including an arithmetic operation circuit is determined as a data path circuit. On the other hand, a circuit other than the data path circuit is set as a control circuit, and a circuit including only a logical operation circuit is determined as a control circuit. That is, when the right side of the function description expression for realizing the variable includes only logical operators (S44, Yes), it is determined that the variable is a control system circuit, and the process proceeds to step S46. If the right side of the function description expression for realizing the variable is not composed only of the logical operator (including the arithmetic operator) (S44, No), it is determined to be the data path circuit and the process proceeds to step S45. .

In step S45, the variable is regarded as the end point of the combinational circuit tree that cannot be expanded, the expansion processing ends, and the process returns to step S40 to select the next candidate.

Further, in step S46, a variable determined as a variable in the control system circuit is replaced with a logical expression for realizing the variable, thereby performing an intermediate variable expanding process. By repeating the above processing, expansion processing is performed until there are no more variables to be expanded, that is, expansion of intermediate variables becomes impossible, and a logical tree of the control system circuit is extracted from the RTL. In this way, by using the intermediate variables, the logic tree of the control circuit divided and described in a plurality of sentences can be replaced with a single expression. As described above, according to the logic synthesis apparatus of the present embodiment, it is possible to extract only the combinational circuit from the description in the hardware description language, and to logically compress the combinational circuit before performing the logic synthesis. By doing so, it has become possible to reduce the time required for logic synthesis.

[Second Embodiment] FIG. 10 is a block diagram showing a schematic configuration of a logic synthesizing apparatus according to a second embodiment of the present invention. The only difference from the logic synthesis apparatus according to the first embodiment shown in FIG. 3 is that the pre-synthesis logical compression unit 22 has been deleted and that an implementation selection change unit 28 has been added. Therefore, detailed description of the same configurations and functions will not be repeated.

As described in the logic synthesizing apparatus of the first embodiment, the implementation selecting unit 24 applies the design constraint condition (from the outside) to the arithmetic operation cell whose implementation has not been selected yet. (Speed-priority or area-priority is set). However, inadvertent design constraints may be given, or an inappropriate implementation that is not intended by the designer may be selected depending on the contents of the function description. Implementation selection change unit 2
Reference numeral 8 is for manually changing the implementation selection determined by the implementation selection unit 24.

FIG. 11 is a flowchart for explaining the processing procedure of the logic synthesizing apparatus according to the present embodiment. Compared to the processing procedure of the logic synthesis apparatus according to the first embodiment shown in FIG. 4, step S12 in FIG. 4 is deleted, and step S12 is inserted between steps S14 and S15.
The only difference is that 18 has been added. Therefore, detailed description of the overlapping processing procedure will not be repeated.

FIG. 12 is a flowchart for explaining the processing in step S18 shown in FIG. 11 in more detail. First, the implementation selection changing unit 28
The logical structure determined by the processing up to step S14 is displayed on the graphic display device 2 (S5).
1).

Then, the logical structure corresponding to the implementation selected in step S14 is highlighted on the graphic display device 2 (S5).
2). For example, in the case of the logical structure shown in FIG. 18B, the arithmetic operation cells and the like are highlighted on the graphic display device 2, indicating that the implementation of the arithmetic operation cells can be changed. Further, the implementation selection changing unit 28 displays that the logical structure (the part corresponding to the above-described control circuit) determined in step S13 cannot be changed. At this time, by displaying a portion (combination of AND, OR, NOT cells, etc.) corresponding to these control logic circuits as a black box, the display speed in the graphic display device 2 can be improved.

Next, the implementation selection changing section 28 displays a message to urge the operator to change the implementation (S53). The operator may determine the implementation selected by the implementation selecting unit 24 based on the function description and the design constraint without changing the implementation. Also, the operator
The design constraint may be selected from the options such as the speed-first design constraint and the area-first design constraint displayed on the graphic display device 2, and the implementation may be changed (S54).

Finally, the implementation selection changing unit 28 changes the function description and the contents of the design constraint conditions based on the instruction to change the implementation by the operator (S55). Then, in the case of the adder shown in FIG.
y The logic circuit structure equivalent to the Look Ahead type adder is
Also, given design constraints that prioritize area, Ripple Car
The logical circuit structure corresponding to the ry type adder is AND, O
It is configured using simple operation cells such as R and NOT.

As described above, according to the logic synthesis apparatus of the present embodiment, the operator can change the implementation while checking the logic circuit corresponding to the implementation displayed on the graphic display device. Therefore, a desired logic circuit can be obtained in a short time, and processing efficiency is improved.

[Embodiment 3] The logic synthesis device according to the third embodiment is different from the logic synthesis device according to the first embodiment shown in FIG. 3 in that the logic synthesis device according to the first embodiment shown in FIG. The only difference is that an implementation selection changing unit 28 of the logic synthesis device according to the second embodiment shown in FIG. 10 is added between the annotation selection unit 24 and the technology mapping unit 25. Therefore, detailed description of the same configurations and functions will not be repeated.

FIG. 13 is a flowchart for explaining a processing procedure of the logic synthesizing apparatus according to the third embodiment. Compared to the flowchart of the logic synthesis device according to the first embodiment shown in FIG. 4, between steps S14 and S15 in the flowchart of the logic synthesis device according to the first embodiment shown in FIG. 4, the embodiment shown in FIG. 2 only in that step S18 of the flowchart of the logic synthesis device in FIG. 2 is added. Therefore, detailed description of the overlapping processing procedure will not be repeated.

As described above, according to the logic synthesis device of the third embodiment, the effects of the logic synthesis devices of the first and second embodiments can be obtained. That is,
Only the combinational circuit can be extracted from the description in the hardware description language. Then, the combinational circuit is logically compressed before the logical synthesis, and the operator changes the implementation while checking the logical circuit corresponding to the implementation displayed on the graphic display device, thereby performing the logical synthesis. Time can be greatly reduced.

Fourth Embodiment In the first to third embodiments, the logic synthesizing apparatus has been described. Fourth Embodiment The fourth embodiment relates to a logic analyzer for analyzing a hardware description language.

The logic analyzer according to the fourth embodiment of the present invention removes the technology mapping unit 25, the violation correction unit 26, and the post-synthesis logical compression unit 27 of the logic synthesis device according to the first embodiment shown in FIG. After the implementation selection unit 24, the implementation selection change unit 2 of the logic synthesis apparatus according to the second embodiment shown in FIG.
The only difference is that 8 has been added. Therefore, detailed description of the same configurations and functions will not be repeated.

FIG. 14 is a flowchart for explaining the processing procedure of the logic analyzer according to the fourth embodiment. As compared with the flowchart of the logic synthesis device in the third embodiment shown in FIG. 13, the third embodiment shown in FIG.
Step S1 of the flowchart of the logic synthesis device in
The only difference is that 5 to S17 are deleted. Therefore, detailed description of the overlapping processing procedure will not be repeated.

As described above, according to the logic analyzer of the fourth embodiment, it is possible to extract only the combinational circuit from the description in the hardware description language. Then, the combinational circuit is logically compressed before the logical synthesis, and the operator changes the implementation while checking the logical circuit corresponding to the implementation displayed on the graphic display device, thereby realizing the hardware. Before logic synthesis of a description language, it became possible to analyze the effect on the logic circuit after logic synthesis.

[0091]

According to the logic synthesizing device of the first aspect,
Since the logic circuit is synthesized from the description including the description of the logically compressed block, the time required for the logic synthesis can be reduced.

According to the logic synthesizing device of the second aspect,
Since the implementation is changed according to an instruction from the user, a desired logic circuit can be obtained in a short time, and the processing efficiency of the logic synthesis device has been improved.

According to the logic synthesizing device of the third aspect,
Since the implementation is changed according to an instruction from the user, in addition to the effect of the first aspect, a desired logic circuit can be obtained in a short time, and the processing efficiency of the logic synthesis device has been improved.

According to the logic synthesizing device of the fourth aspect,
Since the combinational circuit is extracted by expanding the variables until the expansion becomes impossible, the combinational circuit can be extracted more appropriately.

According to the logic synthesis method of the fifth aspect,
Since the logic circuit is synthesized from the description including the description of the logically compressed block, the time required for the logic synthesis can be reduced.

According to the logic synthesis method of the sixth aspect,
Since the implementation is changed according to an instruction from the user, a desired logic circuit can be obtained in a short time, and the processing efficiency of logic synthesis has been improved.

According to the logic synthesizing program recorded on the medium according to the seventh aspect, since the logic circuit is synthesized from the description including the description of the logically compressed block, the time required for the logic synthesis can be reduced. It became.

According to the logical synthesizing program recorded on the medium according to the eighth aspect, since the implementation is changed according to the instruction from the user, it is possible to obtain a desired logical circuit in a short time. Processing efficiency was improved.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an appearance of a logic synthesis device according to the present invention.

FIG. 2 is a block diagram illustrating a configuration of a logic synthesis device according to the present invention.

FIG. 3 is a diagram for explaining a schematic configuration of a logic synthesis device according to the first embodiment of the present invention;

FIG. 4 is a flowchart illustrating a processing procedure of the logic synthesis device according to the first embodiment of the present invention.

FIG. 5 is a flowchart for explaining the processing procedure of step S12 in FIG. 4 in further detail;

FIG. 6 is a diagram illustrating an example of converting a description of a combinational circuit into a Boolean expression.

FIG. 7 is a diagram illustrating an example of a count number of a variable of a Boolean expression.

FIG. 8 is a diagram illustrating an example of logical compression of a Boolean expression and a change in the count number of a variable at that time.

FIG. 9 is a flowchart for explaining the processing procedure of step S21 in FIG. 5 in more detail;

FIG. 10 is a diagram illustrating a schematic configuration of a logic synthesis device according to a second embodiment of the present invention.

FIG. 11 is a flowchart illustrating a processing procedure of the logic synthesis device according to the second embodiment of the present invention.

FIG. 12 is a flowchart for explaining the processing procedure of step S18 in FIG. 11 in further detail;

FIG. 13 is a flowchart illustrating a processing procedure of the logic synthesis device according to the third embodiment of the present invention.

FIG. 14 is a flowchart illustrating a processing procedure of the logic analysis device according to the fourth embodiment of the present invention.

FIG. 15 is a flowchart illustrating a processing procedure of a conventional logic synthesis device.

FIG. 16 is a diagram illustrating an example of a hardware description language.

FIG. 17 is a diagram showing a logic circuit synthesized from the function description shown in FIG. 16;

FIG. 18 is a diagram illustrating an example of a description including an arithmetic operator and the like and a logic circuit synthesized from the description.

FIG. 19 is a diagram illustrating an example of a technology mapping process.

FIG. 20 is a diagram illustrating an example of conventional logical compression.

[Explanation of symbols]

1 Computer main body, 2 Graphic display device, 3 Magnetic tape device, 4 Magnetic tape, 5 Keyboard, 6 Mouse, 7 CD-ROM device, 8 CD
-ROM, 9 communication modem, 10 CPU, 11 RO
M, 12 RAM, 13 hard disk, 21 syntax analysis unit, 22 pre-synthesis logical compression unit, 23 logical structure determination unit, 24 implementation selection unit, 25 technology mapping unit, 26 violation part correction unit, 27 post-synthesis logical compression unit , 28 Implementation selection changer.

Claims (8)

[Claims] An extraction unit for extracting a description of a block including only a combinational circuit from a description in a hardware description language; and a logical description of a block description including only the combinational circuit extracted by the extraction unit. And a logic synthesizing means for synthesizing a logic circuit from a description including a description of a block logically compressed by the logical compression means. 2. By referring to an internal library,
A logical structure determining means for determining a logical circuit structure based on a description in a hardware description language, and an implementation of a description whose logical circuit structure is not determined by the logical structure determining means is changed by an instruction from a user And logic synthesis means for synthesizing a logic circuit based on the logic circuit structure determined by the logic structure determination means and the implementation changed by the implementation change means. And a logic synthesizer including: 3. Extraction means for extracting a description of a block including only a combinational circuit from descriptions in a hardware description language, and logically compresses a description of a block including only the combinational circuit extracted by the extraction means. Logic determining means for determining a logical circuit structure based on a description including a description of a block logically compressed by the logical compressing means by referring to an internal library; and Implementation changing means for changing an implementation of a description whose logic circuit structure is not determined by the determining means in accordance with an instruction from a user; and a logic circuit structure determined by the logical structure determining means and the implementation. Based on the implementation changed by the There, the logic synthesis device including a logic synthesis means for synthesizing a logic circuit. 4. The variable extracting means for extracting a variable from a description in a hardware description language; a variable declared as an input terminal; a variable interpreted as an output signal of a storage element; And a combinational circuit extracting means for extracting a combinational circuit by sequentially expanding the variables extracted by the variable extracting means until the output signal of the arithmetic operation circuit is included on the right side. The logic synthesis device according to claim 1. 5. A step of extracting a description of a block including only a combinational circuit from a description in a hardware description language; a step of logically compressing the description of the block including only the extracted combinational circuit; Synthesizing a logic circuit from the description including the described description of the block. 6. Referring to an internal library,
Determining a logic circuit structure based on a description in a hardware description language; changing an implementation of the description for which the logic circuit structure has not been determined according to a user instruction; and determining the determined logic circuit structure. And synthesizing a logic circuit based on the modified implementation. 7. A step of extracting a description of a block including only a combinational circuit from a description in a hardware description language; a step of logically compressing the description of the block including only the extracted combinational circuit; Synthesizing a logic circuit from the description including the described description of the block. 8. Referring to the internal library,
Determining a logic circuit structure based on a description in a hardware description language; changing an implementation of the description for which the logic circuit structure has not been determined according to a user instruction; and determining the determined logic circuit structure. And synthesizing a logic circuit based on the modified implementation.