JPH11345142A - Method for compressing static test sequence using two-stage restoration and segment processing - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain sufficient compressing performance, even when this system is used for the detection of the failure of large-scaled industrial design and to realize the shortening of the executing time by recognizing the segments of a vector in a restoring stage, detecting each segment as object failure, and including the rearrangement, removal, and merger of the segments. SOLUTION: The set of text vectors and the list of failures to be detected are inputted together with each detecting time (2.01). Then, the object failure set is selected (2.02), and whether or not any object is present is checked (2.03), and then a restoring procedure constituted of an inspection step (2.05) and an improvement step (2.06) is executed. Then, whether or not the restored vector sequence includes the segments is confirmed (2.07). When the segments are present, the removal and rearrangement of the found segments is operated (2.08). As long as such an object failure is present, the new set of the object failures is selected (2.02), and this operation is continued.

Description

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to a method for statically compressing a sequence of test vectors used to detect faults in a large industrial design. Especially,
The present invention is a method for static compression comprising a decompression stage and a segment processing stage. The present invention is embodied in a method for compressing a static test sequence that appears to be practical for improving the performance and efficiency of fault diagnosis for large-scale designs.

2. Description of the Related Art Static Compression Considerations One vector is a set of inputs to the system. The test set is a set of vectors for recognizing a system failure.
The failure target is a failure recognized by a predetermined set. Since test costs are directly proportional to the number of test vectors in the test set, short test sequences are desirable. The test set size can be reduced using static or dynamic test set compression algorithms. A dynamic technique that performs compression at the same time as the test generation stage. See below. * I. Pomeranz,
S. M. "Dynamic Te by Reddy
st Compaction for Syncro
nousual Circuits
using Static Compaction T
echniques "(Dynamic Test Compression for Synchronous Sequential Circuits Using Static Compression Techniques) Fault Tolerant Computer Symposium Presentation, pp. 53-61,
June 1996, * S. T. Chakradha
r, A. "Bot by Raghunathan
leanck removalalgorithm f
or dynamic compaction ins
"Equivalent Circuits" (Bottle Movement Algorithm for Dynamic Compression in Sequential Circuits) IEEE Bulletin on Computer-Aided Design (Published) 1
997, * E. M. Rudnick, Jana
kH. "Simulation- by Patel
based techniques for dyna
mic test sequence compact
ion "(a simulation-based technique for dynamic test sequence compression), presented at the International Conference on Computer Aided Design, pp. 67-73, November 1996, *
T. J. Lambert, K .; K. Salu
“Methods for Dynamic by Ja
Test Vector Compaction i
n Sequential Test Generator
ion "(Method for Dynamic Test Vector Compression in Sequential Test Generation) VLSI Design International Conference Presentation, p.
p. 166-169, January 1996. Dynamic techniques often require modification of the test generator. On the other hand, static compression techniques are used after the test generation stage.
Thus, this technique is independent of the test generation algorithm and does not require any modifications to the test generator. In addition, static compression techniques can further reduce the size of test sets obtained after dynamic compression. Several static compression methods for sequential circuits are proposed in the following references. * T. M. Nierm
anna, R .; K. Roy, I .; H. Pat
el, J.M. A. “Tes by Abraham
t compaction for sequenti
al circuits "(test compression for sequential circuits), IEEE Bulletin, Computer Aided Design Vo
l. 11, No. 2, pp. 260-267, 1
February 992, * B. "Time-eff by So
client automatic test pat
turn generation system ”
(Time-efficient automatic test pattern generator), Faculty of Electronics, Doctoral Dissertation, Madison, University of Wisconsin, 1994, * I. Pomeranz,
S. M. "On static" by Reddy
compaction of test sequence
ces for synchronous sequence
neutral circuits "(for test sequence static compression for synchronous sequential circuits), Automatic Design Conference, pp. 215-220, June 1996.
Month, * M. S. Hsiao, E. et al. M. Rudn
ick, J.C. H. "Fast" by Patel
algorithms for static com
action of sequential cir
"quit test vectors" (a fast algorithm for static compression of test vectors for sequential circuits), IEEE VLSI Test Symposium, p.
p. 188-195, April 1995 However, some of these methods do not reduce the test set generated by any test generator or simulation based test generator. See below. * T. M.
Niermann, R .; K. Roy, I .;
H. Patel, J.M. A. "Test compaction for seq" by Abraham
Universal Circuits "(Test Compression for Sequential Circuits), IEEE Bulletin Computer Aided Design, vol. 11, no. 2, pp. 260-2.
67, February 1992, * B. "Time by So
-Efficient automatic test
pattern generation system
m "(Time-Efficient Automatic Test Pattern Generator), Ph.D. in Physics, School of Electronics, University of Wisconsin, Madison, 1994. For static compression techniques based on vector insertion, omission, and selection, see I. Pommer.
anz and S.M. M. "On st" by Reddy
attic compaction oftest se
quences for synchronous s
elementary circuits "(for test sequence static compression for synchronous sequential circuits),
(Automatic Design Conference announcement, pp. 215-220, 1
June 996). Such techniques require many failure simulation passes. When saving or replacing one vector, call the fault simulator and make sure that the fault coverage is not affected. While these techniques can compress well, they are too computationally intensive and impractical. Vector restoration techniques aim at restoring the vectors needed to detect all faults starting from the more difficult faults. In this regard, R.A. Guo, I .; Pomer
anz, S.M. M. "Proce by Reddy
durations for static compacti
on of test sequences for
synchronous sequential ci
rcuits based on vector re
station ”(Procedure for static compression of test sequence for synchronous sequential circuit based on vector restoration)
(University of Iowa, Faculty of Electrical and Computer Engineering, Technical Report 8-3-1997, 1997). For the compression of fast static test sets based on removing recursive sequences that start and end in the same state, see also S. Hsiao,
E. FIG. M. Rudnick, J .; H. Pate
"Fast algorithms fors
static compaction of sequence
neutral circuit test vector
s "(High-speed algorithm for static compression of test vectors for sequential circuits) (IEEE VLSI Test Symposium, pp. 188-195, April 1995)
Mon) recently reported. However, such test sets are not as compact as those achieved by algorithms using multiple fault simulation passes. Recently, compression based on vector rearrangement has also been proposed. In this regard, S.M. T.
Chakradhar, M .; S. "Partitioning and Reorder by Hsiao
ering Techniquesfor Stati
c Test Sequence Compaction
nof Sequential Circuits "
See (Division and Rearrangement Techniques for Static Test Sequence Compression of Sequential Circuits) (NEC USA Inc., Computer and Communications Laboratories, 1997 Technical Report). Among known static compression methods, the compression technique based on vector restoration was able to perform the largest compression. In this regard, I.I. Po
meranz, S.M. M. "Vec by Reddy
tor Restoration BasedStat
ic Compaction of Test Seq
uencesfor Synchronous Seq
universal Circuits "(Vector Restoration Based on Static Compression of Test Sequences for Synchronous Sequential Circuits) (University of Iowa, International Conference on Computer Design, pp. 360-365, August 1997);
R. Guo, I .; Pomeranz, S.M.
M. "Procedures fo by Reddy
r static compaction of te
st sequences for syncron
ous sequential circuits b
used on vector restoratio
n "(Procedure for Static Compression of Test Sequence for Synchronous Sequential Circuit Based on Vector Restoration) (Technical Report 8-3-199, University of Iowa, Faculty of Electrical and Computer Engineering)
7, 1997). "Study of compression based on vector recovery" test set V is a vector V _i, ..., that the sequence of the order of V _n, fault f ₁ forming the fault set F This test _set, ..., a f _z To detect. The goal of the compression algorithm is to reduce the test set upon detecting all faults at F. If a vector V _i of the test set to detect the failure, detection time D of the fault
(F) is i. This information can be easily obtained by a preprocessing step including a fault simulation of the test set T (with fault dropping).
For example, the test set in FIG. 1 has 20 vectors, ie, V ₁ ,..., V ₂₀ . This test set detects _five faults, f ₁ ,..., F ₅ .
Fault _{f 5} is detected by the vector _{V 20.} For this reason,
D (f ₅ ) = 20. The other failure detection times are as shown in the figure. The static compression method based on vector restoration is based on the following framework.
Given a test set, a fault set, and a detection time for each fault, the static compression method can generate a shorter test set and detect at least as many faults as the original test set. The fault set is initially selected as a fault target. Such faults can have the same or different detection times. Assuming that the latest detection time of any fault in the target list is t, (1) a subsequence V _i ,..., V _t (1 ≦ i ≦ t) that detects all faults in the fault target list in the restoration stage.
And (2) if the subsequence is derived from a subsequence recovered for the earlier failure target, then all the initial target failures are also detected. The next set of faults is selected from faults left undetected by the restored vector set. This step is continued until there are no more failure targets. In a technique that relies on a failure simulation to satisfy Step 2 described above, the calculation becomes large-scale and impractical in a large-scale industrial design. Among the well-known vector-based compression methods, there is a restoration labor saving synchronization prefix (restoration omitting).
Synchronizing prefix (RSP) is the only method that does not require simulation to satisfy step 2. In this regard, I.I. Pomeranz,
S. M. "Vector Re by Reddy
station Based Static Co
impact of TestSequences
for Synchronous Sequenti
al circuits "(Static compression based on vector restoration of test sequences for synchronous sequential circuits) (University of Iowa, International Conference on Computer Design, pp. 147-64)
360-365, August 1997). R
In the SP way, enough vectors are restored,
Fault targets are detected starting from all unknown initial states. As a result, independently of the addition to the reconstructed vector set, the faults once selected for reconstruction remain detected for the remainder of the compression phase. Line segment vector reconstruction method (linear vector restoration method) determines a sub-sequence by first considering only the vector V _t. If all of the failure target is not necessarily be detected, subsequence V _t-1, V _t is proposed. If this sequence also does not detect all failure subjects, additional vector _{V t-2, ..., V} 1 (in that order) all faults subject is considered to be detected.
Details of this technique will be described below. Among known compression methods based on vector restoration, the RSP method uses C
Little PU processing time is required. However, this R
Even the SP method is too slow to be practical for large-scale industrial design (see Table 2 in FIG. 7). Conventional static compression techniques, including RSP techniques, have at least significant problems that limit their practical use. These techniques, when used to test large industrial designs, require a significant amount of execution time.

As described above, the conventional static compression method of a test vector sequence has insufficient compression performance when used for fault detection in a large-scale industrial design, and is not suitable for compression processing. There was a disadvantage that it required a huge amount of execution time. The present invention solves the above-mentioned conventional disadvantages,
It is an object of the present invention to provide a method for statically compressing a test vector sequence that can obtain sufficient compression performance even when used for fault detection in a large-scale industrial design and realizes a reduced execution time. It is another object of the present invention to provide a method of compressing a test vector sequence in order to test a system having a fault set detectable by the test vector sequence.

To achieve the object of the present invention, a method is provided for compressing a sequence of test vectors for testing a system, the system being detectable by the sequence of test vectors. And a subset of the failure set is selected as a failure target, and the method includes a restoration stage and a segment processing stage. In that method, the reconstructing step recognizes the segments of the vector, detecting each of the segments as faulty, and the segment processing step further includes reordering, removing, and merging the segments. A further improvement is a method for compressing a sequence of test vectors. In the method, the restoration step comprises a verification step and an improvement step, the verification step recognizing a first sub-sequence of test vectors for detecting a failure target and a second sub-sequence not detecting a failure target, and the improvement step comprises: The shortest subsequence between the first subsequence and the second subsequence for detecting a failure target is recognized.
Another aspect of the invention is a method of compressing a sequence of test vectors to test a system,
The system has a fault set that can be detected by a sequence of test vectors to form a compact vector set. In that way, the compressed vector set is decompressed by merging vector segments. A further improvement is that in a way of compressing the sequence of test vectors, the segments are removed and redundant synchronization sequences are eliminated. Yet another aspect of the invention is a method for compressing test vector sequences in which segments are merged into a compact set if found. In the compression method, a test vector, a fault list including faults that can be detected using the test vector, and a fault detection time are recognized. If a fault target exists, the fault target is selected. When the vector restoration is performed and the failure target selected in the restoration stage is found,
Increasing the partial segment set, removing the acquired segment if the partial segment set is a complete segment, merging the acquired segment if the partial segment set is a complete segment,
This step is repeated as long as there is a failure target. In a further refinement, in a method of compressing a sequence of test vectors, the merge stage simulates a new segment from a known initial state obtained after simulating the vectors in the currently compressed vector set. , Adding a new segment to the end of the compressed vector set. A further improvement is that in the method of compressing the sequence of test vectors, the two-stage vector restoration merges the two faults as one fault target if the two faults have a restored sequence that overlaps. In this case, redundant verification is performed as described above, and if there is a segment for detecting a failure target, redundant improvement is performed. According to yet another aspect of the invention, a method for compressing a sequence of test vectors includes assigning j = i in a removal step, having a j-th element of an input segment as a first element, and a last element of the input segment. From the known initial state obtained after the simulation of the vector in the compact set, and run a simulation to simulate the fault detected by the input segment, and j = j + 1 Iterates until no more subsets of the assignments and input faults are detected, outputting the segments starting at the j-1 element of the input segment and ending with the last element of the input segment. Yet another aspect of the present invention is a compression method that includes the use of segments. The improvement is the use of the removal segment and the use of the rearrangement segment.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described.
This will be described with reference to the drawings. For static compression according to the invention
The algorithm can be functional or any vector
Tools or automatic test generators
Used to compress the turtle set. The invention is partly
Based on the concept of vector restoration. The present invention is different from the prior art
The main features are: (1) New two-stage vector restoration technique
And (2) the concept of a new segment. Two steps
Vector restoration is more computationally inefficient than other vector restoration methods.
Always advantageous. The segment of the present invention, which is the concept of a segment
Segment removal and segment reordering provide further compression.
For this purpose, it can be applied to existing compression methods. Two-step vector
The method for restoring torque is described in US patent application N.
o. 09 / 112,945, which is described and embodied in detail.
ing. Segment removal, segment merge, segment
The reorganization procedure is described in detail below.
You. "New static compression algorithm"
FIG. 2 shows a flowchart of the algorithm embodiment. This pressure
In the reduction algorithm, a set of test vectors and
The list of faults to be detected is added to step 2.01.
Input along with each detection time. Steps
Select a target set in 2.02
2.03 whether such an object exists
After checking, the verification step 2.05 and the improvement step
A two-step vector restoration procedure consisting of
You. In step 2.07, the restored vector sequence
Check if the sense includes a segment. If included
Is found in segment operation step 2.08
Remove and rearrange segments that have been lost. Such a pair
Step 2.02 as long as there is an elephant failure
To select a new set of failure targets and continue these operations.
You. This algorithm uses vector restoration like RSP
Based on However, the following two prominent
This is different from the RSP method in the point. 1. If the line vector restoration stage is a large-scale circuit,
It is always replaced by an advantageous two-stage restoration stage. 2. Unlike RSP, the two-step restoration phase is based on the failure set
One monolithic service that detects all faults
Multiple segments rather than subsequences.
Understand. Segments removed for further compression
Subsequences that can be rearranged and rearranged. The main feature of the compression algorithm of the present invention is that
And two-step vector restoration. Segment operation
The two-stage vector restoration technique will be described below. "Segment rearrangement" RS explained in the section of the conventional technology
In the P method, the compressed vector set restored so far
During the recovery phase for all future objects
It will be considered as a target for the simulation. Previous target
Vector set restored for current and future
If you simulate repeatedly during the original stage, RS
It is easy to experiment that the execution time of the P method becomes enormous
I understand. According to the invention, the vector sequence is seg
Is restored in the comment. Segment is a subsequence
SUV_i, ..., V_j(1 ≦ i ≦ j ≦ n), so
The detection time is D (f) <i
It is. In the example of FIG.₅The restoration phase for
Bus sequence V₁₇, ..., V₂₀become. at this point,
Failure f₁, F₂, F₃Depends on the restored sequence
Is not detected. The detection time for all such faults is
Faster than 17. Therefore, the sub-sequence V₁₇,
…, V₂₀Is a segment. f₄Is f₃Detect more than
Time is slow and f₄Is detected by the restored sequence.
Is issued, f₄Cannot be targeted for future failure.
Segments result from the restoration phase of multiple fault targets.
Every failure target corresponds to its own segment.
You. Once a segment is recognized,
During the restoration of any future failure targets,
Not be considered. During the restoration phase of the failure target f, the security of f
Only the vectors that would be present in the
Will be considered for compilation. In the example of FIG.
Object f₅Restored sequence V for₁₇, ..., V
_{2 0}Is a segment. f₃Future failure target like
Only can be multiple new segments. Therefore, f
₃The restoration phase for segment V₁₇, ..., V_{2 0}To
Not considered for failure simulation. The compression stage
If it continues, failure f₃Restored vector sequence for
Is V₅, ..., V₁₂Becomes This sequence is
It is not an event. This is the fault f₂Is not detected and D
(F₂) ≧ 5. Failure f₂Is
is there. f₂In the restoration phase for the subsequence
V₅, ..., V₁₂Target for failure simulation
consider. f₂The vector restoration for
V₂, ..., V₁₂become. Again, this sequence
Not a segment. This is the fault f₁Is not detected and D
(F₁) ≧ 2. Failure f₁Is
is there. f₁The restoration stage for sequence V₁, ..., V
₁₂become. Because there are no undetected faults, this sequence
Is a segment. In short, two segments
There is. (1) Failure f₄And f₅Subsequence to detect
SUV₁₇, ..., V₂₀And (2) fault f₁, F₂, F₃
Subsequence V for detecting₁, ..., V₁₂It is. Book
An embodiment of the compression algorithm of the invention is shown in FIG.
This is explained by the pseudo-code given. Line 6 (segment
Line removal) and the seventh line (segment merge)
Corresponds to the work. About segment removal and segment merging
Will be described below. According to the compression algorithm,
The failure simulation is based on the initial failure list F and the original vector.
Determine failure detection time D at F for set V
Done for During compression, when a segment is found
Vector set called CompactSet as it is
Will be merged. All failures in the early failure list
When the sequence CompactSet detects
Is completed. Recognized by CompactSet so far
Contains vectors in all segments
I have. The vector segments that make up the current subsegment
The set is stored in ParSeg. CompactSe
Both sets, t and ParSeg, are initially empty.
First, all faults in F are set F_uIn addition to
It is. Set F during compression_uHas a CompactSe
Detected by vector at t or ParSeg
Not included failures. Procedure Choose_Next_
Target () selects failure target in vector restoration stage
I do. According to the present invention, the vector-recovered fault is detected
Considered in order of decreasing time. For example, in FIG.
Obstacle f₅Is V₂₀And the fault f₄Is V₁₆Detected by
It is. Failure f₄In a subsequence for detecting₅Also detected
I can't. This is f₅But more detection time
Because it is. But f₅Subsequence to detect
If f₄(That is, f₅Is the detection time slower than
) Can be detected. Because of this, detection
Faults that are slower in time are initially targeted for vector restoration.
Will be considered. Two or more faults have the same detection time
So that, in contrast to one fault, F_uLate in
Failure sets can be selected for the restoration phase. versus
After selecting the elephant, the two-step restoration procedure described below
Segs are expanded to detect the subject. Procedure New_
Subsequence ParSe by Segment ()
Check if g is a segment (FIG. 3)
(Fifth line of the algorithm). New segment found
If so, the segment is included in the CompactSet.
It is rare. The restored vector is a new
ParSeg is reset because a new segment is formed.
Is The segment merging phase has several steps
Consists of According to the present invention, the fault simulator comprises:
Simulating vectors in CompactSet
Circuit is in good condition and incomplete due to undetected fault after installation
Memorize the state. As the first step of the merge phase,
New segment is subject to failure simulation
Will be verified. The initial state of the failure simulator is Comp
simulated vector in actSet
It is the same as the state obtained later. Therefore, the simulation
Not only see the vector due to the fault
The boundary between CompactSet and the new segment
You can also see new sequences formed beyond
(See FIG. 4). The merging step of the present invention uses Co in the example of FIG.
mpactSet = V₁₇, ..., V_{2 0}, And ParSe
g = V₁, ..., V₁₂By considering merging
Can be explained. CompactSeg stains
Failure f after simulation₁, F ₂, F₃Imperfect state of
Is known. During failure simulation,
Failure f₁, F₂, F₃By ParSeg subsea
Not only can you see Kens, but also Compact
Watching subsequences beyond Set and ParSeg
Will be. For example, the sequence V₂₀, V₁, V₂
Is f₃If you want to detect
By performing a failure simulation from the state,
Failure f ₃Is V₁₂V instead of₂become. This is the
The compression characteristics of the method should not be reversed as in the RSP method.
Because it is. The segment method is based on the observation of compression characteristics.
From a point of view, it can do better than the RSP method.
RSP method is expensive and iterative simulation
By performing the sequence ParSeg and Co
Consider subsequences beyond the boundaries of mpactSet
Will do. In contrast, the segment method
Is Compact in a single failure simulation
Everything beyond the boundaries of Set and ParSeg sequences
Consider a subsequence of. As a result, the entire compression hand
The order speeded up considerably. Figure 4 shows segment processing
Schematically illustrates the difference between RSP and the above method in
Things. After segment failure simulation,
The new segment ends the CompactSet sequence.
Added to the end. This completes the merge phase.
You. The target fault is determined next, and the compression phase is repeated.
It is. Compression is complete when the fault of interest is gone
You. The last compressed vector set is Compact
Available in Set. "Two-step vector restoration" Two-step vector restoration algorithm
No. 6,078,045, filed in Co-pending U.S. Pat. 09
/ 112,945. Reversion of the present invention
The original process consists of two phases, verification and improvement. Verification
Phase quickly identifies enough subsequences of the vector.
You. A subsequence that detects all failure targets is
Guaranteed to include even shorter substrings of
You. This subsequence is unnecessarily large and
Called. Remediation phase is a validated segment
Shortest to find all failure targets by pruning
Find substring. According to the restoration process according to the present invention,
Observe that failures can be detected by non-overlapping subsequences
You. In the example of FIG._ThreeAnd f_FiveCan be restored
It represents the case as follows. The entire test set
Obstacle f_ThreeAnd f_FiveProposed as a subsequence necessary to detect
can do. But failure f_ThreeAnd f_FiveDetect
Subsequences do not share vectors. As shown above
And the subsequence V₁₇,…, V₂₀Is f_FiveAnd the subsequence V₁,…,
V₁₂Is f_ThreeIs detected. These subsequences have a common vector
Do not have. The restoration technique of the present invention replaces one subsequence
Generate two subsequences. These subsequences are obviously late
Obstacle f_ThreeAnd f_FiveTo be specified in any way that detects
Can be. Such an independent subsequence is called a segment.
U. With the restoration technology of the present invention, all failure targets can be detected.
Recover non-overlapping segments that can be arbitrarily specified to be
Let The basic concept of the two-step restoration process is the two-step
This will be described with reference to FIG. 2 showing a specific example of the restoration method. Present
The current failure target is f. The detection time is D [f]
Is represented. Labels low, opt, high, base, last are 1
n (the original test set is the vector V₁,
…, V_nConsists of) Sequence ResSeq (V_base,…, V
_last) Was restored to an earlier object and the current
Failure target f is not detected. The restoration process for f is the vector V
_baseStarts with The verification phase is the part that detects the failure target
Row V_low,…, V_lastIdentify. Subsequence V is also in restoration phase
_high,…, V_{las t}Proves that no failure target is detected
You. The important thing is that the shortest subsequence
V_lowAnd V_highStarting with any vector between
is there. The improvement phase consists of the restored subsequence ResSeq
The sub-sequence V is the shortest sub-sequence_opt,…, V_base
Recognize. Here, low ≦ opt <high. Two stages
An example of the restoration algorithm is shown in FIG.
Will be explained by The restoration algorithm was restored
Input fault list F by sequence ResSeq_uAll of
Verification and improvement are repeated until a failure is detected. Each iteration
During this time, it is detected by the currently restored sequence ResSeq.
Only faults that are not issued are considered. Among the undetected faults,
The fault with the longest detection time is selected as the fault target.
These failures are listed in the failure target list F_TCan be put in. Next 2
Two chapters describe the verification and improvement phases.
You. "Verification" Failure target list F_TThen the validation phase
Variables low and hig to delimit the validated segment
Determine the value of h. This phase is the previous restore phase
Inherits or restores the sequence ResSeq from
Can start a new sequence. The variable base is
F_TMinimum failure detection time and already restored sequences
Is initialized to the exponent of the first vector of the sequence ResSeq. Restoration
The algorithm extends ResSeq to F_TDetect failure in
I do. Failure simulation with a while loop (6th line in Fig. 3)
(8th line in FIG. 3) several times. If ResSeq is
If you have a vector, the failure simulator is F_TIs ResSeq
Verify that it has already been detected by. F_TFailure
If no is detected, additional vector is added to ResSeq
(Lines 10 and 11 in FIG. 3). Enough vectors
F_TThis step continues until it is added to detect. k
Vector is F_TWhen added to ResSeq to detect
Indicates that there is no call to the failure simulator in the verification phase.
(log k). In the worst case, the verification
Only 2^{[log2k] +1}Simulate only vector
Does not work. This is the vector simulation in ResSeq.
Not subject to rationale. Fault f in the example of FIG._Five
Consider how the sequence for is restored
Can explain the behavior of the verification phase.
it can. f_FiveIs the first vector to be restored, so ResSeq
Has no vector. For this reason, base and low
D [f_Five] = 20 is assigned. while loop (6 in Figure 3)
During the first iteration (line 2), the fault simulator
Le V₂₀By a sequence consisting of one of_FiveIs detected
Confirm that there is not. f_FiveIs not detected, so the variable low
Is 20−2⁰Is updated to = 19. In the next iteration, the failure simulation
Lator is f_FiveIs sequence V₁₉, V₂₀Not detected by
Confirm that Therefore, the variable high is updated to 19.
Variable low is also 20-2¹= 18 is updated. If this process continues,
low = 20−2^TwoF = 16_FiveIs detected. This is a sequence
V₁₆,…, V₂₀Detects failure from unknown initial state
That's why. Vector v₁₆Fault detection capability
Cannot be changed. At this point, high = 18
You. This marks the end of the verification phase. while le
Four iterations of the loop were required. Validated segments are
Vector v₁₆,…, V₂₀Consists of This segment
f_FiveContains more vectors than necessary to detect. After the “Improvement phase” verification phase, the failure target set F_T
All the faults in are marked as undetected (see FIG. 3).
Line 13). In the improvement phase, F_TVerified to detect
Recognize the shortest subsequence in a segment. Improvement Fe
Failure while loop (line 14 in Figure 3) is also a fault simulator
(Line 17 in FIG. 3). Simple 2 minutes
Using search, F_TShortest part that detects all failures
Close up the sequence. The improvement phase is a failure simulation
The call to the lator is 0 (log (high-low)). k is restored
In the worst case, if the length of the original sequence
The call to the fault simulator is 0 (log k). Also,
In the worst case, the improvement phase is a simulation of the 2k * log k vector.
Request. This is also in ResSeq
Not subject to vector simulation. f_Five(Figure
In the improvement phase for 1), f_FiveShortest to detect
Perform a binary search between low = 16 and high = 18 to find a subsequence
Do. The first sequence considered is the vector V₁₇so
Begin. This is because (low + high) / 2 = 17. C
Kens V₁₇,…, V₂₀Is f_FiveIs detected. For this reason, low is 1
Updated to 7. Because low = high + 1, the while loop on line 14
And the improvement phase ends. Found 1
The shortest substring is V₁₇,…, V₂₀It is. "Accelerated two-step vector restoration"
Co-pending U.S.
Patent application No. 09 / 112,945
Have been. "Segment removal" The technology of the present invention described above is mainly
The aim is to speed up the order. In addition, another of the present invention
As an aspect, eliminating redundant use of synchronization sequences
Therefore, by avoiding it, with the aim of improving the compression characteristics
I have. Assume initial state with unknown failure during segment restoration
Is simulated. For this reason, two segment
Will have a common initialization sequence. Follow
To keep the synchronization sequence of the first segment,
The synchronization sequence of all other segments from the
By doing so, further compression is performed. Segment
FIG. 5 shows a pseudo-code
Explained by The procedure is vector V₁, ..., V
_kStarts with a segment Seg consisting of Set F
_segFailed to generate the segment Seg in the restoration stage
Is included. F_segAlso starts from an unknown initial state
Considered as the set of faults detected by g.
As described above, CompactSet contains the previous segment
Event is included. According to the present invention, CompactSe
good and incomplete after fault simulation of t
The state is stored. Sequence V_{i + 1}, ..., V_j
Is F_{se g}(Starting from an unknown initial state, Compact
(Available after simulation of Set)
If all faults are not detected, there is no segment removal
Is also possible. Otherwise, sequence V_{i + 2},
…, V_jHave been considered and failure simulation
This is done using a sequence. At this stage, no further
Sequence V that cannot be left_k, ..., V_j (I ≦ k
≦ j) until it is found. In the example of FIG.
Segment found is V₁₇, ..., V₂₀It is.
Since this is the first segment, it is not removed. Find next
The segment was V₁, ..., V₁₂It is. 1st seg
Failure f after simulation of the₁, F₂, F₃
Good and imperfect states are available. 2nd
The removal of the fragment proceeds as follows. First, the sequence
V₂, ..., V₁₂And failure f₁, F₂, F₃Is a failure stain
Will be considered for simulation. f₁Is not detected
This is possible even without segment removal. "Experimental results" Static compression technology according to the present invention is called SECO.
It is embodied in a C program. Examples are described above.
All the techniques of the present invention are included. Reveal the difference
For this purpose, an improved version of the RSP system is also implemented. About this
I. Pomeranz, S.M. M. Red
"Vector Restoration B" by dy
ased Static Compaction of
 Test Sequences for Synch
ronous Sequential circuit
s "(Static compression of test sequence for synchronous sequential circuit
-Based vector restoration) (University of Iowa, Computer
International Conference on Design, pp. 360-365, 1
Aug. 997). The RSP method is the same
As stated in the literature, the vector
A simulation is performed for one failure. RSP
Equation is enhanced to account for a large number of faults during vector reconstruction
Have been. In this run of the RSP algorithm, the same
Faults with detection time are considered simultaneously for recovery.
Thus, the procedure includes the concurrent fault simulation used for execution.
Using a lator. How to do this in RSP
It is called an improved RSP. ISCAS benchmark circuit and
Experimental results of several industrial designs have been reported. F.
 Brglez, D.A. Bryan, K .; Koz
"Combinational p by minski
rofiles of sequential ben
chmark circuits "(sequential benchmer
Circuit combination profile) (for circuits and systems)
International Symposium on pp. 1929-1934,
 May 1989). Improved SECO R
Compare with SP. Table 1 in FIG. 6 shows the result of the ISCAS circuit.
Is shown. Table 2 in Figure 7 shows the results of some industrial designs.
Is shown. Each table has the original vector set and compression vector
It shows the number of vectors in the dataset. Compression characteristics
Reports percentage reduction of original vector set
doing. CPU is Sun UltraSPARC
Reported for the workstation. Reported CP
U seconds are specified by the platform. For this reason,
To provide information about the complexity of the algorithm,
Fault simulation of all faults using the original vector set
The time taken for the translation is also reported. At such time
The interval is written below the "Initial simulation time" column
I have. In the column of "improved RSP", I.P. Pomera
nz, S.M. M. "Vector by Reddy
 Restoration Based Static
 Compaction of Test Seque
nces for Synchronous Sequ
initial circuits "(synchronous sequential circuit
Restoration based on Static Compression of Test Sequence
(University of Iowa, International Conference on Computer Design
Record, pp. 360-365, August 1997).
Speed-up version of the fast algorithm was introduced
ing. The result of the above embodiment of the present invention is "SEC
O ”column. The industrial design used for the experiment
The number of gates and the number of flip-flops are shown in Table 2 in FIG.
It is shown. Due to the nature of the method based on vector restoration,
Fault coverage of the vector set is always a compressed vector
Protected by reset. For this reason, the fault coverage
No figures were reported. Table 2 uses the above acceleration technology
The results obtained are also shown. US co-pending above
Patent application no. 09 / 112,945
Such a two-stage restoration and an accelerated two-stage restoration method
The results obtained using 2-φ and 2-φ respectively^*Column
Has been reported to. Initial vector used in ISCAS circuit
The torque set uses the test set generator HITEC.
Was obtained. T. M. Niermann, I .;
 H. "HITEC: A tes by Patel
t generation package for
sequential circuits ”(design
European Automation Conference (EDA)
C), pp. 214-218, March 1991)
See also. See the table below for the compression results of the ISCAS circuit.
It is shown in FIG. Both SECO and RSP technologies are flat
It shows an average compression ratio of 40%, but SECO is much faster
No. It is a small ISCAS circuit (s344, s444)
And the RSP method has better compression. Other ISCAS
For the design, the difference in compression characteristics between the two methods is almost
Absent. Clearly, from a CPU second perspective, SECO
Better than the improved RSP. s1494, s148
In a circuit like FIG. 8, the technology of the present invention is 30 times
Speed and little difference in compression efficiency. ISCAS design
So, on average, SECO uses the original vector set
Of the time it takes to simulate
Compress by about 2 times. Industrial design, three-state buffer, both
Some non-Boolean functions like directional buffers and buses
Have. In addition, set-reset flip-flops
With multiple clocks. The original test cell of such a circuit
The unit was obtained using a commercial test generator. Compression
The results are shown in Table 2. Generally, the time taken at SECO
Is about 2 to 10 times the initial failure simulation time
You. As shown in the table, the execution speed of SECO is
20 to 50 times faster and better compression. example
For industrial design p7B, SECO is 2 in 179 seconds.
7% compression, but with the improved RSP, 25% compression
It takes 10200 seconds to shrink. SECO is about 200,
Large scale design of 5000 flip-flops with 000 gates
Can be finished, but with RSP 2 days in CPU days
Even if it takes, it is not completed. Duplicate verification and improvement technologies
It has been executed. The result of these techniques is^*With SEC
It is shown in the column of O. 2-φ^*The edition has many segments
It is especially effective for circuits that use For example, p306
In total, there are 2666 vector segments and 2-φ
^*The usage result is more than doubled in CPU seconds. In FIG.
Table 3 shows the results of SECO with segment removal.
You. The segment elimination technique of the present invention uses the synchronization prefix redundancy.
Improved compression characteristics by avoiding long-term use.
You. Table 3 shows the results of SECO after segment removal.
Circuit whose compression characteristics have been significantly improved by removing segments
There is. For example, for the ISCAS circuit s526,
Without segment removal, only 32% compression
I didn't come. However, the compression characteristics due to segment removal
Has doubled to 63%. For this reason, segment removal
Therefore, it can be seen that the improvement is remarkable. Depending on the experimental results
Segment removal technology was used to test industrial designs
It can be seen that in some cases, it can be a significant improvement. Experimental result
Is the static pressure of the present invention in terms of performance and compression efficiency.
This shows that the compression algorithm is superior. The present invention
SECO is a further modification of the known static compression technique.
Have been good. Other changes and modifications of the present invention
It will be apparent to those skilled in the art from the foregoing description. here
Has described in detail only some embodiments of the present invention.
Will not depart from the spirit and scope of the invention.
Obviously, changes can be made.

As described above, the static compression method according to the present invention is based on the concept of vector restoration. However, by using segments and two-stage restoration, the compression performance is improved and the time required for the compression processing is reduced. There is an effect that it can be shortened.
Also, the above-described two-stage restoration and segment processing technique according to the present invention can be used in existing static compression methods to further improve CPU time and compression characteristics.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of a failure set in which test vector sets and respective detection times are described.

FIG. 2 is a block diagram illustrating compression using a two-stage decompression algorithm.

FIG. 3 shows an embodiment of a two-stage restoration algorithm, S
It is a figure showing the case where pseudo code is executed to ECO.

FIG. 4 is a diagram showing the difference between the RSP method in segment processing and the method of the present invention because it relates to compression characteristics.

FIG. 5 shows pseudo code for a segment removal algorithm.

FIG. 6 is a diagram showing simulation measurement results.

FIG. 7 illustrates a compression result for a production circuit.

FIG. 8 is a diagram showing a compression result of SECO from which a segment has been removed;

Continuing on the front page (72) Inventor Srimat Chakradad United States, New Jersey 08540, Princeton, 4 Independence Way NESA Research Laboratories (72) Inventor Kiran Dreswamy USA , New Jersey 08540, Princeton, 4 Independence Way NCE USA Research Laboratories

Claims (11)

[Claims] 1. A method for compressing a test vector sequence for testing a system having a failure set detectable by a test vector sequence and selecting a subset of the failure set as a failure target, the compression method comprising: A restoration step and a segment processing step. In the restoration step, the segments of the vector are recognized, and each of the segments detects one of the failure targets. A method for compressing test vector sequences, comprising pruning) and merging. 2. The restoration step includes a verification step and an improvement step. In the verification step, a first subsequence of a test vector for detecting a failure target and a second subsequence not detecting the failure target are recognized. The method according to claim 1, wherein the improving step recognizes a shortest subsequence for detecting the failure target among subsequences between the first subsequence and the second subsequence. Test vector sequence compression method. 3. A method for compressing a test vector sequence for testing a system, the system comprising: forming a compact vector set having a set of faults detectable by the test vector sequence; A method for compressing a test vector sequence, wherein the set is restored by merging segments of the vector. 4. The method according to claim 3, wherein the segments are removed to eliminate redundant synchronization sequences. 5. A method for compressing a test vector sequence, wherein segments are merged into a compact set if found, comprising: (a) a test vector; a fault list including faults detected using the test vector; Recognizing the detection time of the fault, (b) selecting the fault target if it exists, (c) performing two-step vector restoration, and performing the restoration to select the fault target selected in step (b). (D) if the partial segment set is a segment, remove the segment obtained in step (c); (e) if the partial segment set is a segment Merging the segment obtained in the step (c) into a compact set, and (f) the failure target exists in the step (b). A method for compressing a test vector sequence, comprising repeating steps (b) to (e) as far as possible. 6. The step of merging segments of step (e) includes simulating a new segment from a known initial state obtained after simulating a vector in the compact set, and terminating the new segment with an end of the compact set. 6. The method according to claim 5, further comprising: 7. The method according to claim 6, wherein the step (c) comprises:
6. The test vector sequence compression according to claim 5, wherein overlapping verification is performed so that one fault is merged as one fault target, and overlapping improvement is performed when there is a segment for detecting the fault target. Method. 8. A method for removing segments to increase the speed of compression, comprising: (a) assigning j = 1; (b) setting the j-th element of the input segment as the first element and ending the input segment. (C) simulate the faults detected by the input segment from the known initial state obtained after simulating the vector in a previously existing compact set (D) assign j = j + 1; (e) generate the sequence list of step (b) until no further subset of input faults are detected; (f) Starting with the j-1 element of the input segment Outputting a segment ending with the last element of the input segment. 9. A compression method using segments. 10. The compression method according to claim 9, further comprising using segment elimination. 11. The compression method according to claim 9, further comprising using segment rearrangement.