JPH11340817A - Counter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately count clock signals at a high speed. SOLUTION: A counter circuit 11 is constituted of a 7-stage shift register circuit, consisting of 7 flip-flop circuits 121 -127 that receive clock signals CL of count objects in parallel and an EXOR circuit 13 that feeds back an exclusive OR of 6th stage and 7th stage data of the shift register circuit to the 1st stage, a latch circuit 14 latches the output data of the counter circuit 11, and a data conversion circuit 15 converts the latched data into data which denote the number of times of stepping of output data of the counter circuit 11 and provides an output.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a counting device for counting the number of occurrences of an event.

[0002]

2. Description of the Related Art In a measurement system which counts the number of occurrences of various events per predetermined time and processes the counted result by a computer, a clock signal to be counted by a binary counter has conventionally been used for performing the counting process. Was counted.

[0003]

However, in such a counting device using a binary counter, the counting speed of the binary counter is limited, and the counting of the high-speed clock signal cannot be performed accurately. There was a problem.

For example, if the counting of a clock signal having a cycle of 20 nanoseconds is to be performed for 1 second, the maximum count value is approximately 5 × 10 ⁷ , a 26-digit binary counter is required, and each digit is shifted. A delay of 26 times the time occurs.

That is, the speed of the clock signal that can be counted is limited by the number of digits, and it is extremely difficult at present to realize a counting speed of several nanoseconds or less. An object of the present invention is to provide a counting device that solves this problem.

[0006]

In order to achieve the above object, according to a first aspect of the present invention, there is provided a counting apparatus comprising: an n-stage shift register circuit for receiving a clock signal to be counted; An exclusive-OR circuit for feeding an exclusive-OR of a plurality of data out of the bit output data to the n-stage shift register circuit. Each time the clock signal is received, the n-bit output data is incremented. A linear feedback type counting circuit, a latch circuit for latching output data of the counting circuit, and data conversion means for converting the data latched by the latch circuit into data representing the number of steps of the output data of the counting circuit And

Further, the counting device according to claim 2 of the present invention provides
Multiple values result obtained by subtracting the power from the first (2 ⁿⁱ -1) is relatively prime _{(n 1, n 2, ...} n r) respectively provided for each, n _i-stage shift receiving the clock signal of the counting target a register circuit, configured to exclusive-OR of a plurality of data among the output data of n _i bits of the n _i-stage shift register circuit by an exclusive OR circuit is fed back to the n _i-stage shift register circuit, A plurality of linear feedback type counting circuits for incrementing n ₁ , n ₂ ,... N _r bits of output data each time the clock signal is received, and a latch circuit for latching each output data of the plurality of counting circuits. Data conversion means for converting the data latched by the latch circuit into data representing the number of times each output data of the plurality of counting circuits has advanced, and each conversion data output from the data conversion means. Based on, and a count value calculating means for calculating the number of inputs of the input clock signal to said plurality of counter circuits.

According to a third aspect of the present invention, there is provided the counting apparatus according to the first or second aspect, wherein the latch circuit outputs the latched output data of the counting circuit serially. It is constituted by a shift register circuit of the number of stages corresponding to the number of bits of the output data of the counting circuit, and converts serial data output from the latch circuit into parallel data and inputs the parallel data to the data conversion circuit. I have.

According to a fourth aspect of the present invention, in the counting device of the third aspect, the shift register circuit of the counting circuit has at least one data terminal of each of a plurality of flip-flops constituting the shift register. A plurality of input changeover switches for selectively inputting either the output of the flip-flop or the output of the preceding flip-flop are provided, and the shift register circuit of the latch circuit includes a plurality of flip-flops constituting a shift register. Each data terminal of the flip-flop is provided with a plurality of input changeover switches for selectively inputting any of the output of the flip-flop, the output of the preceding flip-flop and the output of the flip-flop of the counting circuit.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a configuration of a counting device 10 according to a first embodiment for performing counting with a relatively small number of bits at high speed.

The counting device 10 comprises a linear feedback type counting circuit 11, a latch circuit 14, and a data conversion circuit 15.

The linear feedback type counting circuit is configured to correspond to a generator polynomial of a predetermined order, and the counting circuit 11 shown in FIG. 1 corresponds to a 7th-order primitive polynomial (1 + x + x ⁷ ). The counting circuit 11 has a Finabocci type connection M
It is constituted by a series of linear feedback shift register circuits.

That is, seven D-type flip-flops 12
_{1-12 7} 7-stage shift register is configured, the feedback of the exclusive OR of the output of the sixth stage and the seventh stage flip flop 12 _6, 12 ₇ to the first stage of flip-flop 12 ₁ from the EXOR circuit 13, the counting target clock signal CL to all the flip-flops 12 ₁ to 12 ₇ and inputs in parallel.
In addition, the set terminal of the flip-flops 12 ₁ to 12 _7, the set signal S to set the output of the flip-flops 12 ₁ to 12 ₇ in the initial data of all 1s are input.

In the counting circuit 11 configured as described above,
As shown in FIG. 2, if (in this example all bits 1) the initial data other than all bits zero for flip flops 12 ₁ to 12 ₇ by setting in advance, the output data d ₀ of the 7-bit ~d ₆ indicates that the input number F of the clock signal CL is 0 to 1
In the range up to 26, any one of the values 1 to 127 is taken without duplication. However, although the input number F of the clock signal CL does not match the output data, this is converted into the clock signal input number F by the data conversion circuit 15 described later.

The 7-bit output data of the counting circuit 11 is
The data is latched by the latch circuit 14 receiving the latch signal L and output to the data conversion circuit 15.

The data conversion circuit 15 is composed of a memory in which the number of inputs F shown in FIG. 2 is stored in advance at an address designated by output data corresponding to the number of inputs F, and the output latched by the latch circuit 14 The input number F corresponding to the data is output.

The set signal S to the counting circuit 11 and the latch signal L to the latch circuit 14 are input from a control circuit (not shown).

In the counting device configured as described above, the input number F of the clock signal CL between the time immediately after the set signal S is input to the counting circuit 11 and the time when the latch signal L is input to the latch circuit 14 is represented by the data F. Output from the conversion circuit 15.

The counting device 10 of the first embodiment receives a clock signal to be counted by a linear feedback type counting circuit that feeds back the output of the shift register circuit, increments output data, and converts the output data. Since it is configured to convert the data into the data indicating the number of input clock signals, high-speed counting of clock signals can be performed without being limited by the number of digits.

Although the case of counting seven digits has been described here, if the configuration of the counting circuit 11 is configured to correspond to a higher-order generator polynomial, counting of seven digits or more can be performed. A counting device that performs high-speed counting up to about ten and several digits can be realized with a simple configuration.

(Second Embodiment) The first embodiment is for a case where the number of digits is relatively small, and can be applied up to about ten and several digits. If a 26-bit count is to be realized by a counting circuit corresponding to the (1 + x + x ² + x ⁶ + x ²⁶ ) 26th-order generator polynomial, the memory capacity of the data conversion circuit 15 is about 210 M
It becomes more than bytes, and it is difficult to configure with a normal memory.

Next, a description will be given of a counting apparatus according to a second embodiment capable of performing high-speed counting of many digits with a small memory capacity for data conversion.

In this counter, a value (2 ⁿⁱ -1) obtained by subtracting 1 from a power of 2 is relatively prime, and the sum (n ₁₎
The number of clock signals is counted by a plurality of counting circuits respectively corresponding to a plurality of primitive polynomials of order such that + n ₂ +... + N _r ) is equal to 26, thereby reducing the memory capacity for data conversion.

In this case, the number of input clock signals cannot be directly obtained from the data converted by the data conversion circuit. However, as described above, the number of bits of each divided data is a power of two. Since the value obtained by subtracting 1 from is relatively prime, the number of clock inputs can be obtained by a method called the remainder number system or the Chinese remainder theorem.

FIG. 3 shows the configuration of the counting device 20 according to the second embodiment. The counting device 20 has a seventh order (n ₁ = 7) and a ninth order (n
₂ = 9), linear feedback type counting circuits 21a to 21c respectively corresponding to the 10th order (n ₃ = 10) primitive polynomials, and 3 provided respectively for the counting circuits 21a to 21c.
It is composed of one latch circuit 31a to 31c, a control circuit 40, a serial / parallel conversion circuit 41, a data conversion circuit 42, and a count value calculation circuit 43.

FIG. 4 shows a counting circuit 21a and a latch circuit 31a.
Shows the internal configuration of the device. Counting circuit 21a, corresponding to the 7-order primitive polynomial ^{(1 + x + x 7)} , a flip-flop 22 _{1-22 7} seven D-type to constitute a shift register circuit of the seven stages, input switch 23 ₁ to 23
₇ and an EXOR circuit 24.

[0028] Each clock terminals of the flip-flops 22 ₁ to 22 _7, and the clock signal CL of the counter object is input in parallel, each data terminal is connected the input switch 23 ₁ to 23 ₇ I have.

[0029] each input selector switch 23 ₁ to 23 _7, 3
It has two input terminals ac. The first input terminal a is a reset terminal to which data for initial setting (here, all 1s) are inputted, and the second input terminal b is a counting terminal to which the output of the preceding flip-flop is inputted. . The third input terminal c is a terminal for hold, and receives the output of the connected flip-flop itself.

The input switch 23 ₁ to 23 _7, the mode signal S ₀ of the 2-bit output from the control circuit 40

The first input terminal a at [00], the second input terminal b at [10], and the third input terminal c at [11].
To the data terminal of the flip-flop.

6th and 7th stage flip-flop 2
Output of 2 _6, 22 _7, are inputted to the EXOR circuit 25,
The exclusive OR of the two is input to the second input terminal b of the input switch 23 ₁ .

On the other hand, the latch circuit 31a is
seven D-type flip-flop for latching the output of each flip-flop 22 _{1-22 7} of a 32 ₁ to 32
_7, and an input changeover switch 33 _to 333 _7.

A clock signal CL is inputted in parallel to each clock terminal of each of the flip-flops 32 _{1 to} 32 _{7 as} a transfer clock signal, and each of the data terminals is provided with an input switch 33 _{1 to} 33 _7. It is connected.

[0034] each input selector switch 33 _to 333 _7, 3
It has two input terminals ac. The first input terminal a output of the flip-flops 22 ₁ to 22 ₇ of the counter circuit 21a at the terminal for the load is input, a second input terminal b is output of the preceding flip-flop in the terminal for transfer input Is done. The third input terminal c is a terminal for hold, and receives the output of the connected flip-flop itself.

The input changeover switches 33 _{1 to} 33 ₇ receive the 2-bit mode signal S ₁ output from the control circuit 40.

At [00], the first input terminal a is connected, at [10], the second input terminal b, and at [11], the third input terminal c is connected to the data terminal of the flip-flop.

As shown in FIG. 5, a counting circuit 21b corresponding to a ninth-order primitive polynomial (1 + x ⁴ + x ⁹ )
Is an input switch 26 ₁ having _nine flip-flops 25 _{1 to} 25 ₉ and three input terminals a to c, respectively.
Is constituted by -26 ₉ and EXOR circuit 27, the latch circuit 31b is nine flip-flops 35 ₁ to 3
Is constituted by 5 _9, input switch 36 ₁ to 36 ₉ having three input terminals a to c.

[0037] In the counter circuit 21b, 9-order output primitive polynomial ^{(1 + x 4 + x 9} ) flip-flop 25 of the fifth stage and ninth stage corresponding to _5, 25 _9, EXOR circuit 2
7 and the exclusive OR of the two is input to the second input terminal b of the input switch 26 ₁ .

Similarly, as shown in FIG. 6, a counting circuit 21c corresponding to a tenth-order primitive polynomial (1 + x ³ + x ¹⁰ )
Is an input changeover switch 29 having _ten flip-flops 28 _{1 to} 28 ₁₀ and three input terminals a to c, respectively.
Is constituted by ₁ to 29 ₁₀ and the EXOR circuit 30,
The latch circuit 31c has ten flip-flops 38 ₁
To 38 ₁₀ , and input changeover switches 39 _{1 to} 39 ₁₀ having three input terminals a to c, respectively.

In the counting circuit 21c, the outputs of the seventh and tenth flip-flops 28 ₇ and 28 ₁₀ are input to the EXOR circuit 30 corresponding to the tenth-order primitive polynomial (1 + x ³ + x ¹⁰ ). The exclusive OR of the two is input to the second input terminal b of the input switch 29 ₁ .

The serial output S of the latch circuit 31a is
Oa (output of the flip-flop 32 _7), serial input SIb of the latch circuit 31b (input switch 36 ₁
To the second input terminal 36b) of the latch circuit 32
a serial output SOb (output of the flip-flop 35 ₇₎ are inputted to the serial input SIb of the latch circuit 31c (second input terminal 39b of the input switch 39 _1).

When the control circuit 40 receives the count instruction signal for instructing the start of the counting, the control circuit 40 changes the mode signal S ₀ as shown in FIG.

Set to [00] and count circuit 21a
[1] is input to all the flip-flops to 21c,
All bits are initialized to 1 data by the clock signal CL. After this initialization, the mode signal S ₀ is set to [10] for a predetermined measurement time T, and the counting circuits 21 a to 21
c to count the clock signal CL. After the measurement time has elapsed, the mode signal S ₀ is set to [11] and the counting circuit 2
The counting results Da to Dc of 1a to 21c are held.

Immediately after the count result is held, the mode signal S ₁ is output as shown in FIG.

[00]
, The count results of the counting circuits 21a to 21c are input to all flip-flops of the latch circuits 31a to 31c, and the latch circuits 31a to 31c are input by a clock signal CL (in this case, 26 clock signals need to be input).
To memorize. Then, the mode signals S ₁ [10] to set counts stored in the latch circuit 31a~31c with results Da, Db, is output Dc serially. When performing continuous measurement, the mode signal S ₀ is output during this time.

Set to [00] to initialize the counting circuits 21a to 21c and start counting.

The counting circuits 21a to 21c and the latch circuits 31a to 31c hold the data by inputting the output of the flip-flop to the data terminal of each flip-flop by the input changeover switch. The clock signal can be always input.

Since the latch circuits 31a to 31c are connected so as to circulate as a whole, each count result can be transferred any number of times until the next count result is latched.

The data output from the latch circuits 31a to 31c is returned to parallel data Da, Db, and Dc by the serial / parallel conversion circuit 41 and input to the data conversion circuit 42.

The data conversion circuit 42 includes the counting circuits 21
The first to third memories 42 respectively corresponding to a to 21c
a, 42b, and 42c are provided.

The first memory 42a stores, in advance, data Ka (0 to 126) indicating the number of steps performed from the initial data to the count result Da at an address designated by the count result Da of the count circuit 21a. The stored data Ka outputs data Ka corresponding to the data Da from the serial / parallel conversion circuit 41.

The second memory 42b stores, in advance, data Kb (0 to 510) representing the number of steps from the initial data to the count result Db at an address designated by the count result Db of the count circuit 21b. The data Kb stored therein and corresponding to the data Db from the serial / parallel conversion circuit 41 is output.

The third memory 42c stores in advance the data Kc (0 to 1022) representing the number of steps from the initial data to the count result Dc at the address specified by the count result Dc of the count circuit 21c. The data Kc stored therein and corresponding to the data Dc from the serial / parallel conversion circuit 41 is output.

Here, the input number F of the clock signal CL to each of the counting circuits 21a to 21c and each of the memories 42a to 42c
FIG. 8 shows the relationship between the output values Ka, Kb, and Kc of 2c.

As shown in FIG.
(= 2 ⁷ -1), 511 (= 2 ⁹ -1), and 1023 (=
Since 2 ¹⁰ -1) is relatively prime, the values Ka, Kb, and Kc output from the memories 41a to 41c are all equal in the range from 0 to 126. Therefore, if Ka = Kb = Kc is satisfied in this range, the value indicates the actual input number F of the clock signal.

However, if the number of inputs F exceeds 126, the values Ka, K output from the memories 42a to 42c
The true input number F cannot be directly obtained from b and Kc.

Therefore, in this embodiment, each memory 42
The values Ka, Kb, and Kc output from a to 42c are input to the count value calculating means 43, and the actual input number F is obtained by using a method called a remainder number system or a Chinese remainder theorem.

In the following, one operation procedure of the above method, Gar
The ner method is shown. That is, the count value calculating means 43 determines in advance m
₁ = 2 ⁷ -1, m ₂ = 2 ⁹ -1, m ₃ = 2 ¹⁰ -1 values, m ₁ · m ₂ values, m ₁ · m ₂ · m ₃ values, and the following congruence: (1) Three coefficients U _ij satisfying U _ij · m _i ≡ 1 (mod m _j ) (1) (where (mod y) indicates the remainder when the operation result is divided by y) (I <j).

Then, according to the following recurrence formula, Ka, K
Va, Vb, and Vc are calculated from b and Kc. Va = Ka Vb = (Kb−Va) U ₁₂ mod m ₂ Vc = [(Kc−Va) U ₁₃ −Vb] U ₂₃ mod m
_Three

[0056] Then, obtained by calculating the following equation input number F (2) F = (Va + m 1 Vb + m 1 m 2 Vc) mod m 1 m 2 m 3 ...... (2).

The count value calculation means 43 performs the above calculation on the values Ka, Kb, Kc output from the memories 42a to 42c, and obtains the actual input number F of the clock signal CL.

[0058] Incidentally, the above-mentioned, 2 ⁷ -1 (= 127),
Since 2 ⁹ -1 (= 511) and 2 ¹⁰ -1 (= 1023) are relatively prime integers, (2 ⁷ -1). (2 ⁹ -1). (2 ¹⁰ -1) can output data of the street (66,389,631 combinations), which is greater than the maximum count 5 × 10 ⁷ when the counted one second clock signal having a period 20 nanoseconds as described above.

Moreover, each memory 42 of the data conversion circuit 42
The memory capacity of a to 42c is (7 × 127) + (9 × 511) + (10 × 1023)
= 15718, which is only about 16 kbits.

As described above, in the counting device of the second embodiment, the value (2 ⁿⁱ −1) obtained by subtracting 1 from the power of 2 is relatively prime, and the sum (n ₁ + n ₂ +... + N _r ) is obtained. The clock signals are counted in parallel by a plurality of linear feedback type counting circuits respectively corresponding to a plurality of primitive polynomials of the order equal to 26, and the counting results are converted into data, respectively.
Since the actual input number of the clock signal is obtained from the value obtained by the data conversion, the clock signal can be counted at a high speed without being limited by the number of digits, as in the above-described embodiment. Many digits can be counted by capacity.

Each of the counting circuits 21a to 21c described above
Are both because of the use of minimum number of terms of the primitive polynomial expressed by ^{(1 + x P + x Q} ), simplification of the actual circuit arrangement (E
The number of XOR circuits is small).

In this embodiment, the case where the counting of 26 bits is performed has been described, but the number of bits can be further increased.

[0063] When performing the example 30 bits of counting, 9-order primitive polynomial ^{(1 + x 4 + x 9} ), 10 -order primitive polynomial ^{(1 + x 3 + x 10} ) and 11-order primitive polynomial (1+
x ² + x ¹¹ ) may be used.

The latch circuit 3 of the second embodiment
Since 1a to 31c constitute the shift register circuit so that the latched counting result can be serially output, it is easy to extend the counting to a plurality of series of clock signals in parallel.

That is, as shown in FIG. 9, the counting circuits 21a to 21c and the latch circuits 31a to 31c are arranged so that the counting for the plural series of clock signals CL _{1 to} CL _N can be performed in parallel.
31c, N sets of latch circuits 3c are provided.
If connected in a series as a whole 1a~31c is, one set of the latch circuit 31c in (set to count the clock signal CL _N 9), the counting result for each clock signal one signal line only can be output, the counting result is output to the serial-parallel conversion circuit 41, the performs the same data conversion may be calculated the number of inputs of each clock signal CL ₁ -CL _N.

In this case, as shown in FIG. 9, if the latch circuits 31a to 31c of each set are connected so as to circulate as a whole, each count result can be transferred any number of times.

When the clock signal to be counted is limited to one series, the latch circuits 31a to 31c
May be configured by a parallel input / parallel output latch circuit as in the first embodiment, and the latch output may be directly input to the data conversion circuit 42. If you do this,
Since time is not required for serial transfer of the counting result, continuous measurement is possible even when the measurement time is short.

In the second embodiment, the data latched in the latch circuit is serially output in synchronization with the clock signal to be counted. However, a clock signal for transfer is input from the control circuit to count the data. The latch data may be output asynchronously with the target clock signal.

In the second embodiment, the initial data is set to the flip-flop of the counting circuit via the input switch. However, the initial data is set without passing through the input switch. As in the first embodiment, the initial data may be set by directly inputting the set signal to the flip-flop.

In the above-described embodiment, the linear feedback shift register circuit of the Fibonacci type is used as the counting circuit. However, the counting circuit 21 shown in FIGS.
As in a ', 21b', and 21c ', a linear feedback shift register circuit of Galois connection may be used. In this Galois-type connection, the order of tap positions (outputs to be input to the EXOR circuit) is reverse to that of the Fibonacci type, and the output of the final stage is input to the first stage and one input terminal of each of the EXOR circuits 24, 27, 30. And the outputs of predetermined stages other than the last stage are input to the other input terminals of the EXOR circuits 24, 27, and 30, and the outputs are input to the next stage after the predetermined stage. This Galois-type connected counting circuit is also of the M-sequence having the longest code cycle, similarly to the Fibonacci type, and has the same operation as in the above embodiment.

In the above embodiment, the linear feedback type counting circuit uses the M sequence (maximum length sequence). However, other sequences such as the H sequence (Hall sequence) and the TP sequence (twin prime number) are used. Series) or the like may be used.

[0072]

As described above, the counting device of the present invention receives a clock signal to be counted by a linear feedback type counting circuit that feeds back the outputs of a plurality of stages of shift registers via an exclusive OR circuit. The output data is incremented by one step, and the output data is converted into data indicating the number of times the increment has been made, so that a high-speed clock signal can be counted without being limited by the number of digits. .

A value obtained by subtracting 1 from a power of 2 (2 ⁿⁱ
-1) The clock signals are counted in parallel by a plurality of linear feedback type counting circuits respectively corresponding to a plurality of generator polynomials of orders which are relatively prime, and the output data is converted into data indicating the number of steps performed. Then, in the counting device that obtains the actual number of inputs of the clock signal from the converted value,
The memory capacity for data conversion can be reduced, and high-speed counting of many digits can be easily realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of the first embodiment;

FIG. 3 is a diagram showing a configuration of a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a main part of the second embodiment.

FIG. 5 is a block diagram showing a configuration of a main part of the second embodiment.

FIG. 6 is a block diagram showing a configuration of a main part of the second embodiment.

FIG. 7 is a view for explaining the operation of the second embodiment;

FIG. 8 is a diagram for explaining the operation of the second embodiment;

FIG. 9 is a block diagram showing a configuration in which counting of a plurality of events is performed in parallel;

FIG. 10 is a block diagram showing a modification of the counting circuit.

FIG. 11 is a block diagram showing a modification of the counting circuit.

FIG. 12 is a block diagram showing a modification of the counting circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 10 counting device 11 counting circuit 12 flip-flop 13 EXOR circuit 14 latch circuit 15 data conversion circuit 20 counting device 21 a to 21 c counting circuit 22, 25, 28 flip-flop 23, 26, 29 input selector switch 24, 27, 30 EXOR circuit 31 a 31c Latch circuit 32, 35, 38 Flip-flop 33, 36, 39 Input changeover switch 40 Control circuit 41 Serial / parallel conversion circuit 42 Data conversion circuit 43 Count value calculation circuit

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[Procedure amendment]

[Submission date] April 23, 1999

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction contents]

[0006]

In order to achieve the above object, according to a first aspect of the present invention, there is provided a counting apparatus comprising: an n-stage shift register circuit for receiving a clock signal to be counted; An exclusive-OR circuit for feeding an exclusive-OR of a plurality of data out of the bit output data to the n-stage shift register circuit. Each time the clock signal is received, the n-bit output data is incremented. A linear feedback type counting circuit (11, 21a to 21c); and a latch circuit (14, 31) for latching output data of the counting circuit.
a to 31c) and a memory in which data indicating the number of times a clock signal has been received is stored in an address corresponding to the value of the output data to be incremented by the counting circuit, and the data latched by the latch circuit is Data conversion means (15, 42) for converting the output data of the counting circuit into data representing the number of steps performed.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0007

[Correction method] Change

[Correction contents]

Further, the counting device according to claim 2 of the present invention provides
The result (2 ⁿⁱ -1) obtained by subtracting 1 from the power of is provided for each of a plurality of mutually prime values (n ₁ , n ₂ ,..., N _r ), and n _i commonly receives the clock signal to be counted. Stage shift register circuit, and n of the _ni stage shift register circuit.
an exclusive-OR circuit that feeds back an exclusive-OR of a plurality of data of the _i- bit output data to the n _i- stage shift register circuit, and receives n ₁ , n ₂ , ... A plurality of linear feedback type counting circuits (21a to 21a) for respectively increasing the _nr- bit output data
1c), a plurality of latch circuits (31a to 31c) for latching each output data of the plurality of counting circuits, and the number of times a clock signal is received at an address corresponding to the value of the output data to be incremented by each of the counting circuits. And a plurality of data converting means for converting the data latched by the latch circuit into data representing the number of times each output data of the plurality of counting circuits has stepped up. 42a to 42c); and a count value calculating means (43) for calculating the number of clock signals input commonly to the plurality of counting circuits based on each converted data output from the plurality of data converting means. It has.

[Procedure amendment 4]

[Document name to be amended] Drawing

[Correction target item name] Figure 3

[Correction method] Change

[Correction contents]

FIG. 3

Claims (4)

[Claims] 1. An n-stage shift register circuit for receiving a clock signal to be counted, and an exclusive-OR of a plurality of data among n-bit output data of the n-stage shift register circuit is sent to the n-stage shift register circuit. A linear feedback type counting circuit that comprises an exclusive OR circuit that feeds back and increments n-bit output data each time the clock signal is received; a latch circuit that latches output data of the counting circuit; A data conversion means for converting data latched by the circuit into data representing the number of times output data of the counting circuit has advanced. 2. The result of subtracting 1 from a power of 2 (2 ⁿⁱ −
A plurality of values (n ₁ , n ₂ ,..., N _r ) in which 1) is relatively prime
Respectively provided for each, and n _i-stage shift register circuit for receiving a clock signal of the counting target, the n _i-stage shift register circuit of n _i the exclusive OR of the plurality of data among the output data of the bit the n _i is constituted by an exclusive OR circuit is fed back to stage shift register circuit, said n ₁ for each receive a clock signal, n _2, ... n _r linear feedback of a plurality of counting circuits for each increment of output data bits A latch circuit for latching each output data of the plurality of counting circuits; and a data conversion for converting the data latched by the latch circuits into data representing the number of times each output data of the plurality of counting circuits has stepped. Means for calculating the number of clock signals input to the plurality of counting circuits based on each conversion data output from the data conversion means. And a counting device comprising: 3. The latch circuit includes a shift register circuit having a number of stages corresponding to the number of bits of the output data of the counting circuit so as to serially output the latched output data of the counting circuit. 3. The counting device according to claim 1, wherein the serial data output from the circuit is converted into parallel data and input to the data conversion circuit. 4. A shift register circuit of the counting circuit, wherein at least one of an output of the flip-flop or an output of a preceding flip-flop is selectively input to each data terminal of a plurality of flip-flops constituting the shift register. The shift register circuit of the latch circuit includes an output of the flip-flop, an output of the preceding flip-flop, and a data terminal of each flip-flop constituting the shift register. 4. The counting device according to claim 3, further comprising a plurality of input changeover switches for selectively inputting any one of the outputs of the flip-flop of the counting circuit.