JPH11340809A - Input circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an input circuit to that has a function of amplifying an input signal whose voltage level is lower than a power supply voltage, where a difference of voltage between an H level and an L level is very small, surely receives the input signal with the characteristics as above, even when a frequency of the input signal is high, and stably supplies the amplified signal to other circuits. SOLUTION: This input circuit 1 consists of 1st, 2nd, 3rd sense amplifiers 11, 21, 231 and inverters 241, 243. The 1st sense amplifier is provided with a P-channel transistor (TR) 12 and the 2nd sense amplifier is provided with a P-channel TR 22. Since the on-state of the P-channel TRs 12, 22 is strengthened when a voltage at nodes N3, N4 is decreased, the voltage at the nodes N3, N4 is higher than the case without the P-channel TRs 12, 22.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input circuit of a semiconductor integrated circuit device, and more particularly, to an input signal having a high frequency and a voltage level lower than a power supply voltage, and amplifying the input signal to a predetermined internal circuit connected thereto. The present invention relates to an input circuit having a function of supplying an amplified signal.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor integrated circuit device, input signals IN and INN having a high frequency and a voltage level lower than a power supply voltage (the input signal IN and the input signal INN are complementary signals) are received. For this purpose, the input circuit 201 shown in FIG. 9 has been used.

The input circuit 201 includes a first sense amplifier 211 serving as a first differential amplifier, a second sense amplifier 221 serving as a second differential amplifier, and a third sense amplifier 221 serving as a third differential amplifier. It comprises a third sense amplifier 231 and inverters 241, 243.

[0004] The first sense amplifier 211 is a P-channel transistor (hereinafter, referred to as a "P transistor").
212, 213, 214, and N-channel type transistors (hereinafter, referred to as “N transistors”) 215, 2
16. The first sense amplifier 211 uses P transistors 213 and 214 to receive the input signal IN as the first input signal and the input signal INN as the second input signal, respectively. It is generally called a P-type sense amplifier.

The second sense amplifier 221 comprises P transistors 222, 223, 224 and N transistor 2
25, 226. Similarly to the first sense amplifier 211, the second sense amplifier 221 uses P-transistors 224 and 223 to receive the input signals IN and INN, respectively. It is said.

The third sense amplifier 231 includes N transistors 232, 233, 234 and P transistor 2
35, 236. Then, the third sense amplifier 231 receives the first amplified signal from the first sense amplifier 211 and the second amplified signal from the second sense amplifier 221 to receive the N transistors 233 and 234, respectively. And is generally called an N-type sense amplifier.

Next, the connection of each component of the conventional input circuit 201 will be described. The node N1, which is the input point of the input signal IN from outside the input circuit 201,
The gate of the P transistor 213 belonging to the sense amplifier 211 and the gate of the P transistor 224 belonging to the second sense amplifier 221 are connected. On the other hand, the gate of a P transistor 214 belonging to the first sense amplifier 211 and the gate of a P transistor 223 belonging to the second sense amplifier 221 are connected to a node N2 which is an input point of an input signal INN from outside the input circuit 201. Is connected.

Here, the connection inside the first sense amplifier 211 will be described. The source of the P transistor 212 is connected to the power supply, the drain is connected to the node N211 and the gate is connected to the ground. The source of the P transistor 213 and the source of the P transistor 214 are commonly connected to the node N211. The drain of the P transistor 213, the drain and gate of the N transistor 215, and the gate of the N transistor 216 are commonly connected to a node N212. The source of the N transistor 215 and the source of the N transistor 216 are commonly connected to the ground. The drain of the P transistor 214 and the drain of the N transistor 216 are commonly connected to a node N3.

Next, the connection inside the second sense amplifier 221 will be described. The source of the P transistor 222 is connected to the power supply, the drain is connected to the node N221, and the gate is connected to the ground. The source of the P transistor 223 and the source of the P transistor 224 are commonly connected to the node N221. The drain of the P transistor 223, the drain and gate of the N transistor 225, and the gate of the N transistor 226 are commonly connected to a node N222. The source of the N transistor 225 and the source of the N transistor 226 are commonly connected to the ground. The drain of the P transistor 224 and the drain of the N transistor 226 are commonly connected to a node N4.

Next, the connection contents inside the third sense amplifier 231 will be described. The source of the N transistor 232 is connected to the ground, and the drain is connected to the node N231.
, And the gate is connected to the power supply. The source of the N-transistor 233 and the source of the N-transistor 234 are commonly connected to the node N231. The drain of the N transistor 233, the drain and gate of the P transistor 235, and the gate of the P transistor 236 are commonly connected to a node N232. The source of the P transistor 235 and the source of the P transistor 236 are commonly connected to a power supply.
The drain of the N transistor 234 and the drain of the P transistor 236 are connected to the node N5.

Further, an inverter 24 is connected to the node N5.
1, and the inverter 243 are sequentially connected. A predetermined circuit (not shown) is connected to the output of the inverter 243, and an output signal OU is supplied to the circuit.
T will be supplied.

The conventional input circuit 201 having the above configuration
Will be described with reference to FIG. FIG.
0 indicates that there is no change in the voltage of the input signals IN and INN;
This indicates a so-called static state and a state in which the voltage of the input signals IN and INN fluctuates and the fluctuation periodically repeats, that is, a so-called dynamic state. And the static state in FIG. 10 corresponds to the time domain [1],
The dynamic state corresponds to the time domain [2]. Also,
FIG. 10A shows a case where the voltage of the input signal IN is lower than the voltage of the input signal INN in the time domain [1], and FIG. 10B is the reverse of FIG. In the time domain [1], the voltage of the input signal IN
The case where the voltage is higher than the voltage of N is shown.

First, in the time domain [1], the first sense amplifier 211 outputs the voltage difference (Vi) between the voltage (Vi1) of the input signal IN and the voltage (Vi2) of the input signal INN.
1-Vi2) and amplify the node N as a first amplified signal.
Output to 3. Conversely, the second sense amplifier 22
1 amplifies the voltage difference (Vi2-Vi1) between the voltage (Vi1) of the input signal IN and the voltage (Vi2) of the input signal INN and outputs the amplified signal to the node N4 as a second amplified signal.
Then, the third sense amplifier 231 amplifies the voltage difference (Va1−Va2) between the voltage (Va2) of the node N4 and the voltage (Va2) of the node N3 and outputs the amplified signal to the node N5 as a third amplified signal. , And the inverter 24
1, 243 amplify the voltage (Va3) of the node N5,
Output signal O of a predetermined voltage (here, 0 V / 3.3 V)
Output UT.

Next, when the voltage (Vi1) of the input signal IN and the voltage (Vi2) of the input signal INN are reversed, that is, when the time domain [1] shifts to the time domain [2], the input signals IN, The voltages (Va1, Va1) of the nodes N3, N4 are changed according to the fluctuations of the voltages (Vi1, Vi2) of INN.
2) starts to fluctuate. Here, the voltage fluctuations of the nodes N3 and N4 are slower than the voltage fluctuations of the input signals IN and INN due to operation delays of a plurality of transistors forming the first sense amplifier 211 and the second sense amplifier 221. Becomes

Thereafter, the voltages of the input signals IN and INN (V
i1, Vi2) repeatedly fluctuates at a predetermined cycle, and the voltage (Va1) of the node N3 and the voltage (Va2) of the node N4 fluctuate according to the voltage fluctuation. Further, with the voltage fluctuations of the nodes N3 and N4, the node N5
Of the output signal (Va3), the inverter 243 outputs an output signal OUT having the same frequency as the input signals IN and INN and having a peak voltage of 0 V / 3.3 V.
Is output. That is, the conventional input circuit 2
According to No. 01, the voltage is lower than the power supply voltage (here, 3.3 V), and is a logical high level (hereinafter, referred to as “H level”) voltage and a logical low level (hereinafter, referred to as “L level”). ) Are received (here, several tens of mV), the input signals IN, INN are received, and the amplitude of the power supply voltage / ground voltage is applied to a predetermined circuit (not shown) connected thereto. It has been possible to supply the amplified output signal OUT.

[0016]

However, FIG.
As shown in FIG. 7, when the frequency of the input signals IN and INN is high (here, about 500 MHz), the voltage fluctuation of the first input signals IN and INN in the time domain [2] is
The fluctuations of the voltages (Va1, Va2) of the nodes N3, N4 cannot follow up, and the difference between the peak voltage value pN3 of the node N3 and the peak voltage value pN4 of the node N4 becomes insufficient. For this reason, the peak voltage value pN3 and the peak voltage value pN
Although the difference from N4 is amplified by the third sense amplifier 231, the voltage (Va3) at the node N5 is
41, the input signals IN, IN
There is a possibility that the voltage fluctuation of N does not appear as the voltage fluctuation of the output signal OUT. For example, input signals IN, INN
If the input signal indicates serial data, the input circuit 20
The predetermined circuit connected to 1 will fail to take in the first data. In today's world where high-speed data processing is required, there is an increasing need for an input circuit capable of stably supplying a higher frequency signal to a subsequent circuit.

The present invention has been made in view of the above-mentioned problems of the conventional input circuit, and an object of the present invention is to reduce the voltage level of the power supply voltage and to reduce the voltage at the H level. It has the function of amplifying an input signal whose voltage difference at the L level is very small. Even if the frequency of the input signal is high, it reliably receives the input signal and stabilizes the amplified signal to other circuits. An object of the present invention is to provide an input circuit that can be supplied in a controlled manner.

[0018]

According to a first aspect of the present invention, a difference between a voltage of a first input signal and a voltage of a second input signal is amplified, and the first amplification is performed. A first differential amplifier circuit for outputting a signal, a second differential amplifier circuit for amplifying a difference between a voltage of the first input signal and a voltage of the second input signal, and outputting a second amplified signal; , An input circuit configured to amplify a difference between the voltage of the first amplified signal and the voltage of the second amplified signal and output a third amplified signal. The input circuit includes first voltage adjusting means for adjusting the voltage of the first amplified signal, and second voltage adjusting means for adjusting the voltage of the second amplified signal. .

According to this configuration, the voltage of the first amplified signal is adjusted to a predetermined value by the first voltage adjusting means, and the voltage value of the second amplified signal is adjusted to the predetermined value by the second voltage adjusting means. Therefore, the voltage of the third amplified signal output from the third differential amplifier circuit that amplifies the voltage difference between the voltage of the first amplified signal and the voltage of the second amplified signal is also adjusted to the value of the third amplified signal. The voltage can be adjusted by the first voltage adjusting means and the second voltage adjusting means. Therefore, for example, when a third amplified signal is supplied to a predetermined circuit via an inverter gate, the voltage of the third amplified signal may be adjusted according to the threshold voltage of the transistor forming the inverter gate. It is possible, and the reliability of the operation of the inverter gate is improved, and as a result, the operation of a predetermined circuit connected to the input circuit is stabilized.

For example, if the voltage of the first input signal fluctuates periodically and the frequency of the voltage fluctuation is high, the first
Due to the operation delay of the differential amplifier circuit, the voltage fluctuation of the first amplified signal may not follow the voltage fluctuation of the first input signal. Similarly, if the voltage of the second input signal fluctuates periodically and the frequency of the voltage fluctuation is high, the second input signal is delayed with respect to the voltage fluctuation of the second input signal due to the operation delay of the second differential amplifier circuit. There is a possibility that the voltage fluctuation of the amplified signal 2 does not follow. Such a delay in the voltage fluctuation of the first amplified signal and the second amplified signal causes the voltage of the third amplified signal generated by the third differential amplifier circuit to not reach a predetermined value. With respect to such a problem, according to the input circuit of the first aspect, the voltage of the first amplified signal is adjusted by the first voltage adjusting means, and the voltage of the second amplified signal is adjusted by the second voltage adjusting means. Is adjusted, the voltage of the third amplified signal can be shifted to a predetermined level. Therefore, even when the voltage of the first input signal and the voltage of the second input signal fluctuate at high speed, the stable operation of the predetermined circuit to which the third amplified signal is supplied is maintained. .

According to the second aspect, the first voltage adjusting means in the input circuit according to the first aspect is configured to increase a logically low level voltage in the first amplified signal. The second voltage adjusting means is configured to increase a logical low level voltage in the second amplified signal.

According to such a configuration, for example, when the first input signal and the second input signal are complementary signals and these voltages fluctuate periodically, the first input signal becomes logically low. When the voltage is at the level, the voltage value becomes larger than that of the conventional input circuit without the first voltage adjusting means,
The voltage of the first amplified signal generated by the differential amplifier circuit is
It will fluctuate on the high voltage side. Similarly, when the second input signal is at a logical low level, the voltage value becomes larger than that of the conventional input circuit without the second voltage adjusting means, and is generated by the second differential amplifier circuit. The voltage of the second amplified signal fluctuates on the high voltage side. Therefore,
Even when the frequency of the voltage fluctuation of the first and second input signals is high, the operation time for switching the first and second input signals from a logically low level to a logically high level can be reduced. . Thus, for example, when the third amplified signal is input to the inverter gate, the voltage variation range of the third amplified signal can be adjusted to be adapted to the threshold voltage of the transistor constituting the inverter gate, and the inverter gate can be adjusted. The response speed of the operation is improved.

According to a third aspect of the present invention, in the input circuit according to the second aspect, the first voltage adjusting means includes one electrode and a gate electrode to which the first amplified signal is applied,
A first voltage-adjusting P-channel transistor having the other electrode to which a voltage higher than the voltage of the first amplified signal is applied can be used. Similarly, the second voltage adjusting means includes a second electrode having one electrode to which the second amplified signal is applied and a gate electrode, and a second electrode having the other electrode to which a voltage higher than the voltage of the second amplified signal is applied. P for voltage adjustment
A channel transistor can be used. According to the present invention, it is possible to realize the first voltage adjusting unit and the second voltage adjusting unit with a simple circuit configuration.

According to a fourth aspect, the first voltage adjusting means in the input circuit according to the first aspect is configured to reduce a logically high level voltage in the first amplified signal. The second voltage adjusting means is configured to reduce a logically high level voltage in the second amplified signal.

According to such a configuration, for example, when the first input signal and the second input signal are complementary signals and these voltages fluctuate periodically, the first input signal becomes logically high. When the level is at the level, the voltage value is smaller than that of the conventional input circuit without the first voltage adjusting means, and the voltage of the first amplified signal generated by the first differential amplifier circuit is lower on the low voltage side. Will fluctuate. Similarly, when the second input signal is at a logically high level, the voltage value becomes smaller than that of the conventional input circuit without the second voltage adjusting means, and the second input signal generated by the second differential amplifier circuit is generated. The voltage of the amplified signal 2 fluctuates on the low voltage side. Therefore, even when the frequency of the voltage fluctuation of the first and second input signals is high, the operation time for switching the first and second input signals from a logically high level to a logically low level can be reduced. It is planned. Thus, for example, when the third amplified signal is input to the inverter gate, the voltage variation range of the third amplified signal can be adjusted to be adapted to the threshold voltage of the transistor constituting the inverter gate, and the inverter gate can be adjusted. The response speed of the operation is improved.

According to a fifth aspect of the present invention, in the input circuit according to the sixth aspect, the first voltage adjusting means includes one electrode and a gate electrode to which the first amplified signal is applied, and
A first voltage adjusting N-channel transistor having another electrode to which a voltage lower than the voltage of the first amplified signal is applied can be used. Similarly, the second voltage adjusting means has a second electrode to which a second amplified signal is supplied and a gate electrode, and a second electrode to which a voltage lower than the voltage of the second amplified signal is applied. It is possible to use the voltage adjusting N-channel transistor. According to the present invention, it is possible to realize the first voltage adjusting unit and the second voltage adjusting unit with a simple circuit configuration.

According to the sixth aspect, the third differential amplifier circuit is configured to include a constant current source whose output current is controlled according to the third amplified signal. According to such a configuration, it is possible to increase the voltage when the third amplified signal is at a logically high level and decrease the voltage when the third amplified signal is at a logically low level. Therefore, since the amplitude of the voltage of the third amplified signal can be increased, for example, when this third amplified signal is input to the inverter gate, the response speed of the operation of the inverter gate can be improved.

According to a seventh aspect of the present invention, the constant current source according to the sixth aspect may be a transistor having a gate electrode to which a signal having a phase opposite to that of the third amplified signal is input. is there. According to such a configuration, the output current of the constant current source is directly controlled according to the voltage level of the third amplified signal. That is, it is possible to increase the amplitude of the third amplified signal with a lean circuit configuration.

[0029]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
A preferred embodiment of the input circuit according to the present invention will be described in detail. In the following description, components having substantially the same function and configuration will be denoted by the same reference numerals, and redundant description will be omitted.

(First Embodiment) In an input circuit 1 according to a first embodiment, as shown in FIG. 1, a first sense amplifier 211 is different from a conventional input circuit 201 by a first difference. The configuration has been changed to the first sense amplifier 11 as a dynamic amplifier circuit, and the second sense amplifier 221 has been changed to the second sense amplifier 21 as a second differential amplifier circuit.

The first sense amplifier 11 is provided with a P-transistor 12 as a first voltage adjusting means with respect to the first sense amplifier 211 in the conventional input circuit 201.
Are added. The second sense amplifier 21 is the second sense amplifier 21 in the conventional input circuit 201.
Has a configuration in which a P transistor 22 as a second voltage adjusting means is added to the sense amplifier 221 of FIG.

Next, the connection of each component of the input circuit 1 according to the first embodiment will be described. A first sense amplifier 11 is connected to a node N1, which is an input point of an input signal IN as a first input signal from outside the input circuit 1.
And the gate of a P transistor 224 belonging to the second sense amplifier 21 are connected. On the other hand, a node N2, which is an input point of an input signal INN as a second input signal from the outside of the input circuit 1, is connected to the gate of the P transistor 214 belonging to the first sense amplifier 11 and the second sense amplifier 21. Are connected.

Here, the connection inside the first sense amplifier 11 will be described. The source of the P transistor 212 is connected to the power supply, the drain is connected to the node N211 and the gate is connected to the ground. And
The node N211 has a source of the P transistor 213,
The source of the P transistor 214 and the source of the P transistor 12 are commonly connected. P transistor 2
The drain of the transistor 13, the drain and gate of the N transistor 215, and the gate of the N transistor 216 are commonly connected to a node N212. N transistor 215
And the source of the N transistor 216 are commonly connected to the ground. The drain of the P transistor 214, the drain of the N transistor 216,
The drain and gate of P transistor 12 are commonly connected to node N3.

Next, the connection contents inside the second sense amplifier 21 will be described. The source of the P transistor 222 is
The power supply is connected, the drain is connected to the node N221, and the gate is connected to the ground. The source of the P transistor 223 and the P
Source of transistor 224 and P transistor 2
Two sources are commonly connected. P transistor 22
3, the drain and gate of the N transistor 225, and the gate of the N transistor 226 are connected to the node N
222 is commonly connected. The source of the N transistor 225 and the source of the N transistor 226 are commonly connected to the ground. And P transistor 2
The drain of the transistor 24, the drain of the N transistor 226, and the drain and gate of the P transistor 22 are commonly connected to a node N4.

The third sense amplifier 231 is connected to the nodes N3, N4 and N5, similarly to the conventional input circuit 201. Further, an inverter 2 is connected to the node N5.
41, and an inverter 243 are sequentially connected.
A predetermined circuit (not shown) is connected to the output of the inverter 243, and an output signal O is supplied to the circuit.
The UT will be supplied.

The operation of the input circuit 1 according to the first embodiment having the above configuration will be described with reference to FIG. FIG. 2A corresponds to FIG. 10A showing the operation of the conventional input circuit 201, and FIG. 2B corresponds to FIG. 10B.

First, the voltages of input signals IN and INN (Vi
1, Vi2), when the input signal IN is at the L level and the input signal INN is at the H level in the time region [1] where there is no change in the first sense amplifier, as shown in FIG. 11, the voltage (V
a1) is lower than the voltage (Va2) of the node N4 which is the output node of the second sense amplifier 21. Therefore, the node N which is the output node of the third sense amplifier 231
5, the voltage (Va3) becomes L level and the inverter 2
The output signal OUT output via the terminals 41 and 243 is L
Level.

Incidentally, the first sense amplifier 11 includes a P transistor 12 characteristic of the present invention. When the voltage (Va1) of the node N3 decreases, the ON state of the P transistor 12 increases, so that the node N3 is affected by the power supply voltage. Therefore, as compared with the conventional input circuit 201 having no P-transistor 12, the voltage of the node N3 (Va
1) becomes higher.

Next, when the voltage (Vi1) of the input signal IN and the voltage (Vi2) of the input signal INN are reversed, that is, when the time domain [1] shifts to the time domain [2], the input signals IN, In response to the voltage fluctuation of INN, the voltage (Va1) of the node N3 increases, and conversely, the voltage (Va2) of the node N4 starts to decrease. And, as described above, the first
The peak voltage pN3 (about 2.2 V) of the node N3 with respect to the first fluctuation of the input signals IN and INN due to the action of the P transistor 12 provided in the sense amplifier 11 of FIG.
Is higher than the value (about 1.8 V) of the conventional input circuit 201 shown in FIG. As a result, the difference between the peak voltage value pN3 of the node N3 and the peak voltage value pN4 of the node N4 is sufficiently ensured, and the node N5
(Va3) exceeds the threshold voltage of the inverter 241 and the voltage of the output signal OUT rises. After that, the voltage of the output signal OUT is changed to the input signals IN,
It fluctuates according to the fluctuation of the voltage (Vi1, Vi2) of INN.

On the other hand, the voltages of the input signals IN and INN (Vi
1, Vi2), when the input signal IN is at the H level and the input signal INN is at the L level in the time region [1] in which there is no change in the second sense amplifier as shown in FIG. The voltage (V
a2) becomes lower than the voltage (Va2) of the node N3 which is the output node of the first sense amplifier 11. Therefore, the node N which is the output node of the third sense amplifier 231
5, the voltage (Va3) becomes H level and the inverter 2
The output signal OUT output via the terminals 41 and 243 is H
Level.

Incidentally, the second sense amplifier 21 is provided with a P transistor 22 characteristic of the present invention, like the first sense amplifier 11. When the voltage (Va2) of the node N4 decreases, the ON state of the P transistor 22 increases, so that the node N4 is affected by the power supply voltage. Therefore, the voltage (Va2) of the node N4 in the time domain [1] is higher than that of the conventional input circuit 201 having no P transistor 22.

Next, when the voltage (Vi1) of the input signal IN and the voltage (Vi2) of the input signal INN are reversed, that is, when the time domain [1] is shifted to the time domain [2], the input signals IN, In response to the voltage fluctuation of INN, the voltage (Va2) of the node N4 increases, and conversely, the voltage (Va1) of the node N3 starts to decrease. As described above, the P transistor 22 provided in the second sense amplifier 21 is used.
The peak voltage pN4 (about 2.0 V) of the node N4 with respect to the first fluctuation of the input signals IN and INN.
Is higher than the value (about 1.7 V) of the conventional input circuit 201 shown in FIG. As a result, the difference between the peak voltage value pN4 of the node N4 and the peak voltage value pN3 of the node N3 is sufficiently ensured, and the node N5
(Va3) falls below the threshold voltage of the inverter 241 and the voltage of the output signal OUT decreases. After that, the voltage of the output signal OUT is changed to the input signals IN,
It fluctuates according to the fluctuation of the voltage (Vi1, Vi2) of INN.

As described above, the input circuit 1 according to the first embodiment of the present invention includes the input signals IN, INN
, The peak voltage pN3 of the node N3 and the peak voltage pN4 of the node N4 for the first fluctuation of the voltages (Vi1, Vi2) of the input signals IN, INN in the time domain [2] are sufficient. It is possible to make a significant difference. Therefore, according to the input circuit 1 according to the first embodiment, the input signals IN, INN
Of the voltage (Vi1, Vi2) at the output signal O
In addition to stably outputting as a UT, even when the voltages (Vi1, Vi2) of the input signals IN, INN are switched at a high frequency of, for example, several hundred MHz or more,
The first voltage fluctuation of the input signals IN and INN can be reliably output as the output signal OUT.

(Second Embodiment) As shown in FIG. 3, an input circuit 31 according to a second embodiment is different from the input circuit 1 according to the first embodiment in that a third sense amplifier is used. 231 has a configuration changed to the third sense amplifier 41, and other configurations are substantially the same.

The third sense amplifier 41 is configured such that the N-transistor 232 has a constant current with respect to the conventional input circuit 201 and the third sense amplifier 231 provided in the input circuit 1 according to the first embodiment. It has a configuration changed to an N transistor 42 as a source.

Next, the connection of each component of the input circuit 31 according to the second embodiment will be described. Input circuit 31
The gate of a P-transistor 213 belonging to the first sense amplifier 11 and the gate of a P-transistor 224 belonging to the second sense amplifier 21 are connected to a node N1, which is an input point of an input signal IN from outside the device. . On the other hand, a node N2 which is an input point of an input signal INN from outside the input circuit 31 has a gate of a P transistor 214 belonging to the first sense amplifier 11 and a P transistor 223 belonging to the second sense amplifier 21.
Gates are connected.

The gate of the N transistor 233 provided in the third sense amplifier 41 is connected to the node N3, which is the output node of the first sense amplifier 11,
Node N4 which is an output node of second sense amplifier 21
Is connected to the gate of the N-transistor 234 provided in the third sense amplifier 41.

Next, the connection contents inside the third sense amplifier 41 will be described. The source of the N transistor 42 is connected to the ground, and the drain is connected to the node N231. The source of the N-transistor 233 and the source of the N-transistor 234 are commonly connected to the node N231. The drain of N transistor 233, the drain and gate of P transistor 235, and P
The gate of the transistor 236 and the N transistor 4
The two gates are commonly connected to a node N232.
The source of the P transistor 235 and the source of the P transistor 236 are commonly connected to a power supply. The drain of the N transistor 234 and the drain of the P transistor 236 are connected to the node N5.

Further, an inverter 24 is connected to the node N5.
1, and the inverter 243 are sequentially connected. A predetermined circuit (not shown) is connected to the output of the inverter 243, and an output signal OU is supplied to the circuit.
T will be supplied.

The operation of the input circuit 31 having the above configuration according to the second embodiment will be described with reference to FIG. 4A corresponds to FIG. 2A showing the operation of the input circuit 1 according to the first embodiment, and FIG. 4B corresponds to FIG. 2B. Corresponding.

First, the voltages of input signals IN and INN (Vi
1, Vi2), when the input signal IN is at the L level and the input signal INN is at the H level in the time domain [1], as shown in FIG. 11, the voltage (V
a1) is lower than the voltage (Va2) of the node N4 which is the output node of the second sense amplifier 21. Therefore, the node N5 which is the output node of the third sense amplifier 41
(Va3) attains an L level, and the inverter 24
The output signal OUT output via the terminals 1 and 243 becomes L level.

Incidentally, the first sense amplifier 11 includes a P transistor 12 characteristic of the present invention. When the voltage (Va1) of the node N3 decreases, the ON state of the P transistor 12 increases, so that the node N3 is affected by the power supply voltage. Therefore, as compared with the conventional input circuit 201 having no P-transistor 12, the voltage of the node N3 (Va
1) becomes higher.

Next, when the voltage (Vi1) of the input signal IN and the voltage (Vi2) of the input signal INN are reversed, that is, when the time domain [1] shifts to the time domain [2], the input signals IN, In response to the voltage fluctuation of INN, the voltage (Va1) of the node N3 increases, and conversely, the voltage (Va2) of the node N4 starts to decrease. And, as described above, the first
Due to the action of the P transistor 12 provided in the sense amplifier 11, the peak voltage value pN3 of the node N3 with respect to the first fluctuation of the input signals IN and INN is changed by the conventional input circuit 201 shown in FIG. It is higher than the value. As a result, the voltage of the node N3 (Va
1) and the voltage (Va2) at the node N4 is sufficiently ensured, the voltage (Va3) at the node N5 exceeds the threshold voltage of the inverter 241, and the voltage of the output signal OUT rises. After that, the voltage of the output signal OUT becomes
It fluctuates according to voltage fluctuations of the input signals IN and INN.

On the other hand, the voltages of input signals IN and INN (Vi
1, Vi2), when the input signal IN is at the H level and the input signal INN is at the L level in the time region [1] where there is no change, as shown in FIG. The voltage (V
a2) becomes lower than the voltage (Va1) of the node N3 which is the output node of the first sense amplifier 11. Therefore, the node N5 which is the output node of the third sense amplifier 41
(Va3) attains the H level, and the inverter 24
The output signal OUT output via the terminals 1 and 243 becomes H level.

Incidentally, the second sense amplifier 21 includes a P transistor 22 characteristic of the present invention, like the first sense amplifier 11. This P transistor 22
Is turned on when the voltage (Va2) of the node N4 decreases, the node N4 is affected by the power supply voltage. Therefore, the voltage (Va2) of the node N4 in the time domain [1] is higher than that of the conventional input circuit 201 having no P transistor 22.

Next, when the voltage (Vi1) of the input signal IN and the voltage (Vi2) of the input signal INN are reversed, that is, when the time domain [1] shifts to the time domain [2], the input signals IN, In response to the voltage fluctuation of INN, the voltage (Va2) of the node N4 increases, and conversely, the voltage (Va1) of the node N3 starts to decrease. Then, as described above, the second
The peak voltage value pN4 of the node N4 with respect to the first fluctuation of the input signals IN and INN is changed by the action of the P transistor 22 provided in the sense amplifier 21 of the conventional input circuit 201 shown in FIG. It is higher than the value. As a result, the voltage of the node N4 (Va
2) and the voltage at the node N3 (Va1) is sufficiently ensured, and the voltage at the node N5 (Va3) is
, And the voltage of the output signal OUT drops. After that, the voltage of the output signal OUT fluctuates according to the voltage fluctuation of the input signals IN and INN.

By the way, when the voltage (Va3) of the node N5 rises with the voltage fluctuation of the input signals IN and INN,
The voltage of the node N232 inside the third sense amplifier 41 decreases. Then, the ON state of the N-transistor 42 whose gate is connected to the node N232 weakens, and the voltage (Va3) of the node N5 further rises. Conversely, when the voltage (Va3) of the node N5 decreases,
The ON state of the N transistor 42 is strengthened, and the voltage (Va3) of the node N5 is further reduced.

As described above, the input circuit 31 according to the second embodiment of the present invention has the same effects as the input circuit 1 according to the first embodiment, and also has the following unique effects. Have. The gate voltage of the N-transistor 42 provided in the third sense amplifier 41 is controlled according to the voltage (Va3) of the node N5.
, The response characteristic of the inverter 241 connected to the node N5 is improved. Therefore, the input circuit 3 according to the second embodiment
According to 1, it becomes possible to amplify the input signals IN and INN with high frequencies more reliably and to stably supply the output signal OUT to a predetermined circuit (not shown) to be connected.

(Third Embodiment) As shown in FIG. 5, an input circuit 51 according to a third embodiment is different from the conventional input circuit 201 in that the third sense amplifier 231 has a third difference. The configuration is changed to a third sense amplifier 61 as a dynamic amplifier circuit, and an N-transistor 52 as a first voltage adjusting unit and an N-transistor 53 as a second voltage adjusting unit are added. .

The third sense amplifier 61 includes P transistors 62, 63, 64 and N transistor 6
5, 66. The third sense amplifier 61 has P transistors 63 and 64 as input ports.
Are generally used as P-type sense amplifiers.

Next, the connection of each component of the input circuit 51 according to the third embodiment will be described. Input circuit 51
A node N1 which is an input point of an input signal IN from outside the gate of the P transistor 213 belonging to the first sense amplifier 211 and the second sense amplifier 21
Are connected. On the other hand, a node N2 which is an input point of an input signal INN from outside the input circuit 51 has a gate of a P transistor 214 belonging to the first sense amplifier 211 and a P transistor 2 belonging to the second sense amplifier 221.
23 gates are connected.

The third sense amplifier 61 is connected to a node N3 which is an output node of the first sense amplifier 211.
Is connected to the gate of an N transistor 63 provided in
Further, the drain and gate of the N transistor 52 are connected. On the other hand, the node N4, which is the output node of the second sense amplifier 221, is connected to the gate of the N-transistor 64 provided in the third sense amplifier 61, and further connected to the drain and gate of the N-transistor 53. I have. The sources of the N-transistor 52 and the N-transistor 53 are both connected to the ground.

Next, the connection contents inside the third sense amplifier 61 will be described. The source of P transistor 62 is connected to the power supply, the drain is connected to node N61,
The gate is connected to the ground. The source of the P transistor 63 and the source of the P transistor 64 are commonly connected to the node N61. The drain of the P transistor 63, the drain and gate of the N transistor 65, and the gate of the N transistor 66 are commonly connected to a node N62. N transistor 65
And the source of the N transistor 66 are commonly connected to the ground. And the P transistor 6
4 and the drain of the N transistor 66 are connected to the node N5.

Further, an inverter 24 is connected to the node N5.
1, and the inverter 243 are sequentially connected. A predetermined circuit (not shown) is connected to the output of the inverter 243, and an output signal OU is supplied to the circuit.
T will be supplied.

The operation of the input circuit 51 having the above configuration according to the third embodiment will be described with reference to FIG. FIG. 6A corresponds to FIGS. 2 and 4A showing the operation of the input circuits 1 and 31 according to the first and second embodiments, and FIG. This corresponds to (b) of (2) and (4).

First, the voltages of input signals IN and INN (Vi
1, Vi2), when the input signal IN is at the L level and the input signal INN is at the H level in the time domain [1], as shown in FIG. The voltage (Va1) of the node N3 which is the output node of 211 is lower than the voltage (Va2) of the node N4 which is the output node of the second sense amplifier 221. Therefore, the voltage (Va3) of the node N5, which is the output node of the third sense amplifier 61, becomes L level, and the output signal OUT outputted through the inverters 241 and 243 is output.
Becomes L level.

The node N4 is provided with an N-transistor 53 characteristic of the present invention. The on-state of the N-transistor 53 increases when the voltage (Va3) of the node N4 rises, so that the node N4 is affected by the ground. Therefore, the voltage (Va2) of the node N4 in the time domain [1] is lower than that of the conventional input circuit 201 having no N transistor 53.

Next, when the voltage (Vi1) of the input signal IN and the voltage (Vi2) of the input signal INN are reversed, that is, when the time domain [1] shifts to the time domain [2], the input signals IN, In response to the voltage fluctuation of INN, the voltage (Va1) of the node N3 increases, and conversely, the voltage (Va2) of the node N4 starts to decrease. As described above, the peak voltage value pN4 of the node N4 with respect to the first voltage fluctuation of the input signals IN and INN is changed by the operation of the N-transistor 53 connected to the node N4 as shown in FIG. It is lower than the value in the input circuit 201. As a result, the difference between the peak voltage value pN3 of the node N3 and the peak voltage value pN4 of the node N4 is sufficiently ensured, the voltage (Va3) of the node N5 exceeds the threshold voltage of the inverter 241, and the voltage of the output signal OUT rises. Will do. After that, the voltage of the output signal OUT becomes
It fluctuates according to voltage fluctuations of the input signals IN and INN.

On the other hand, the voltages of input signals IN and INN (Vi
1, Vi2), when the input signal IN is at the H level and the input signal INN is at the L level in the time domain [1], as shown in FIG. The voltage (Va2) of the node N4 which is the output node of the node 221 is lower than the voltage (Va1) of the node N3 which is the output node of the first sense amplifier 211. Therefore, the voltage (Va3) of the node N5, which is the output node of the third sense amplifier 61, becomes H level, and the output signal OUT output through the inverters 241 and 243 is output.
Becomes H level.

The node N3 is provided with an N transistor 52 characteristic of the present invention. Since the ON state of the N-transistor 52 increases when the voltage (Va1) of the node N3 increases, the node N3 is affected by the ground. Therefore, the voltage (Va1) of the node N3 in the time domain [1] is lower than that of the conventional input circuit 201 having no N transistor 52.

Next, when the voltage (Vi1) of the input signal IN and the voltage (Vi2) of the input signal INN are reversed, that is, when the time domain [1] shifts to the time domain [2], the input signals IN, In response to the voltage fluctuation of INN, the voltage (Va2) of the node N4 increases, and conversely, the voltage (Va1) of the node N3 starts to decrease. The peak voltage value pN3 of the node N3 with respect to the first fluctuation of the input signals IN and INN is changed by the operation of the N transistor 52 connected to the node N3 as described above. It is lower than the value in the circuit 201.
As a result, the difference between the peak voltage value pN3 at the node N3 and the peak voltage value pN4 at the node N4 is sufficiently ensured, the voltage (Va3) at the node N5 falls below the threshold voltage of the inverter 241, and the voltage of the output signal OUT becomes Will decrease. After that, the voltage of the output signal OUT becomes
It fluctuates according to voltage fluctuations of the input signals IN and INN.

As described above, the input circuit 51 according to the third embodiment of the present invention includes the input signals IN, IN
Even when the frequency of N is high, the peak voltage value pN3 of the node N3 and the peak voltage value pN4 of the node N4 with respect to the first fluctuation of the voltages (Vi1, Vi2) of the input signals IN, INN in the time domain [2]. It is possible to make a sufficient difference. Therefore, the input circuit 51
According to the above, the voltages (Vi1, Vi1) of the input signals IN, INN are
In addition to amplifying the fluctuation of 2) and stably outputting the output signal OUT, the voltages (Vi1, Vi2) of the input signals IN and INN are switched at a high frequency of, for example, several hundred MHz or more. Also input signals IN, INN
Can be reliably output as the output signal OUT.

Further, the first, second,
The third sense amplifiers 211, 221 and 61 are all composed of P-type sense amplifiers having substantially the same circuit. Therefore, for example, when the input circuit 51 is formed on a semiconductor substrate, manufacturing efficiency is improved. As a result, the throughput is improved.

(Fourth Embodiment) As shown in FIG. 7, an input circuit 71 according to a fourth embodiment is different from the conventional input circuit 201 in that the first sense amplifier 211 has a first difference. The first sense amplifier 81 is changed to a dynamic amplifier circuit, the second sense amplifier 221 is changed to a second sense amplifier 91 as a second differential amplifier circuit, and the third sense amplifier 231 is changed to a third sense amplifier 231. Has been changed to a third sense amplifier 101 as a differential amplifier circuit.

The first sense amplifier 81 includes N transistors 82, 83, 84, an N transistor 87 as first voltage adjusting means, and P transistors 85, 86. The gates of the N transistors 83, 84 are provided. Is used as an input port, and is generally called an N-type sense amplifier.

The second sense amplifier 91 includes N transistors 92, 93, 94, an N transistor 97 as second voltage adjusting means, and P transistors 95, 96. The gates of the N transistors 93, 94 are provided. Is used as an input port, and is generally called an N-type sense amplifier.

The third sense amplifier 101 includes a P transistor 102 as a constant current source, a P transistor 103,
It is generally referred to as a P-type sense amplifier because it includes an N-channel transistor 104 and N-transistors 105 and 106, and the gates of the P-transistors 103 and 104 are used as input ports.

Next, the connection of each component of the input circuit 71 according to the fourth embodiment will be described. Input circuit 71
The gate of an N-transistor 83 belonging to the first sense amplifier 81 and the gate of an N-transistor 94 belonging to the second sense amplifier 91 are connected to a node N1 which is an input point of an input signal IN from outside of the device. . On the other hand, a first sense amplifier 81 is connected to a node N2 which is an input point of an input signal INN from outside the input circuit 71.
And the gate of an N transistor 93 belonging to the second sense amplifier 91 are connected.

Here, the connection contents inside the first sense amplifier 81 will be described. The source of the N transistor 82 is
The ground is connected, the drain is connected to the node N81, and the gate is connected to the power supply. The source of the N transistor 83, the source of the N transistor 84, and the source of the N transistor 87 are commonly connected to the node N81. The drain of N transistor 83, the drain and gate of P transistor 85, and P
The gates of the transistors 86 are commonly connected to a node N82. The source of the P transistor 85 and the source of the P transistor 86 are commonly connected to a power supply. The drain of the N transistor 84, the drain of the P transistor 86, and the drain and gate of the N transistor 87 are commonly connected to a node N3.

Next, the connection inside the second sense amplifier 91 will be described. The source of the N-transistor 92 is connected to the ground, the drain is connected to the node N91, and the gate is connected to the power supply. And node N
The source of the N transistor 93, the source of the N transistor 94, and the source of the N transistor 97 are commonly connected to 91. The drain of the N-transistor 93,
The drain and gate of P transistor 95 and the gate of P transistor 96 are commonly connected to node N92. The source of the P transistor 95 and the source of the P transistor 96 are commonly connected to a power supply. The drain of the N transistor 94, the drain of the P transistor 96, and the drain and gate of the N transistor 97 are commonly connected to a node N4.

Next, the connection contents inside the third sense amplifier 101 will be described. The source of the P transistor 102 is connected to the power supply, the drain is connected to the node N101, and the gate is connected to the node N102.
The source of the P transistor 103 and the source of the P transistor 104 are commonly connected to the node N101. The drain of the P transistor 103, the drain and gate of the N transistor 105, and the gate of the N transistor 106 are commonly connected to a node N102. The source of the N transistor 105 and the source of the N transistor 106 are commonly connected to the ground. The drain of the P transistor 104 and the drain of the N transistor 106 are commonly connected to a node N5.

The inverter 24 is connected to the node N5.
1, and the inverter 243 are sequentially connected. A predetermined circuit (not shown) is connected to the output of the inverter 243, and an output signal OU is supplied to the circuit.
T will be supplied.

The operation of the input circuit 71 according to the fourth embodiment having the above configuration will be described.

The voltages (Vi1, V1) of the input signals IN, INN
When the input signal IN is at the L level and the input signal INN is at the H level in the time domain where there is no change in i2), the voltage (Va1) of the node N3, which is the output node of the first sense amplifier 81, becomes The voltage is lower than the voltage (Va2) of the node N4, which is the output node of the second sense amplifier 91. Therefore, the voltage (Va3) of the node N5, which is the output node of the third sense amplifier 101, becomes L level, and the output signal OUT output via the inverters 241 and 243 becomes L level.

The second sense amplifier 91 includes an N transistor 97 characteristic of the present invention. This N
Since the on-state of the transistor 97 increases when the voltage (Va2) of the node N4 increases, the transistor 97 is compared with the conventional input circuit 201 having no N-transistor 97.
(Va2) becomes lower.

On the other hand, the voltages of input signals IN and INN (Vi
1, Vi2), when the input signal IN is at the H level and the input signal INN is at the L level, the voltage (Va2) of the node N4, which is the output node of the second sense amplifier 91, becomes , First sense amplifier 81
Is lower than the voltage (Va1) of the node N3, which is the output node of. Therefore, the voltage (Va3) of the node N5, which is the output node of the third sense amplifier 101, goes high, and the output signal OUT output via the inverters 241 and 243 goes high.

The first sense amplifier 81 has an N transistor 87 characteristic of the present invention. This N
The on-state of the transistor 87 increases when the voltage (Va1) of the node N3 rises, so that the transistor 87 is compared with the conventional input circuit 201 having no N-transistor 87.
(Va1) becomes lower.

As described above, according to the input circuit 71 according to the fourth embodiment of the present invention, the N transistor 87 provided in the first sense amplifier 81
The voltage when the node N3 is at the H level can be reduced, and the voltage when the node N4 is at the H level can be reduced by the N transistor 97 provided in the second sense amplifier 91. It becomes possible.
Therefore, similarly to the input circuits 1, 31, and 51 according to the first, second, and third embodiments, even if the frequency of the voltage fluctuation of the input signals IN, INN is high, the input signals IN, IN,
It is possible to cause a sufficient difference between the peak voltage value of the node N3 and the peak voltage value of the node N4 with respect to the first fluctuation of the voltage (Vi1, Vi2) of INN. Thereby, the voltages (Vi1, Vi2) of the input signals IN, INN are obtained.
Is switched at a high frequency of, for example, several hundred MHz or more, it is possible to reliably output the first voltage fluctuation of the input signals IN and INN as the output signal OUT. Since the first sense amplifier 81 and the second sense amplifier 91 are N-type sense amplifiers, the input circuits 1, 31, and 5 according to the first, second, and third embodiments are used.
1, compared to the voltages of input signals IN and INN (Vi1,
Even when Vi2) fluctuates near the power supply voltage, it is possible to reliably receive the voltage fluctuations of the input signals IN and INN.

When the voltages (Vi1, Vi2) of the input signals IN, INN fluctuate, the voltages (Va1, Va2) of the nodes N3, N4 fluctuate accordingly, and further, the voltage (Va3) of the node N5 fluctuates. I do. Here, when the voltage (Va3) of the node N5 increases, the voltage of the node N102 inside the third sense amplifier 101 decreases. Then, the P whose gate is connected to this node N102
The on state of the transistor 102 is increased, and the voltage (Va3) of the node N5 is further increased. Conversely, when the voltage (Va3) of the node N5 decreases, the ON state of the P transistor 102 weakens, and the voltage (Va3) of the node N5 decreases.
3) will be lower.

That is, according to the input circuit 71 according to the fourth embodiment of the present invention, the third sense amplifier 101
Is configured so as to be controlled in accordance with the voltage (Va3) of the node N5, the voltage amplitude at the node N5 is enlarged and connected to the node N5. The response characteristics of the inverter 241 are improved. Therefore,
According to the input circuit 71 according to the fourth embodiment, the input signals IN and INN having high frequencies are reliably amplified, and the output signal OUT is output to a predetermined circuit (not shown) to be connected.
Can be supplied stably.

(Fifth Embodiment) As shown in FIG. 8, an input circuit 111 according to a fifth embodiment is different from the conventional input circuit 201 in that the first sense amplifier 211 has a first differential amplifier. It is changed to a first sense amplifier 121 as an amplifier circuit, the second sense amplifier 221 is changed to a second sense amplifier 131 as a second differential amplifier circuit, and further, as a first voltage adjusting means. P transistor 11
It has a configuration in which a P transistor 113 as second and second voltage adjusting means is added.

The first sense amplifier 121 has a configuration in which the N transistor 87 is omitted from the first sense amplifier 81 in the input circuit 71 according to the fourth embodiment. Further, the second sense amplifier 131 is different from the second sense amplifier 91 in the input circuit 71 according to the fourth embodiment in that the N transistor 9
7 is omitted.

Next, the connection of each component of the input circuit 111 according to the fifth embodiment will be described. Input circuit 1
A node N1, which is an input point of an input signal IN from outside the N.11, has a gate of an N transistor 83 belonging to the first sense amplifier 121 and a second sense amplifier 1
The gate of an N-transistor 94 belonging to 31 is connected. On the other hand, an input signal IN from outside the input circuit 111
The gate of the N-transistor 84 belonging to the first sense amplifier 121 and the gate of the N-transistor 93 belonging to the second sense amplifier 131 are connected to a node N2 which is an input point of N.

Here, the connection inside the first sense amplifier 121 will be described. The source of the N transistor 82 is connected to the ground, the drain is connected to the node N81, and the gate is connected to the power supply. The source of the N transistor 83 and the source of the N transistor 84 are commonly connected to the node N81. N
The drain of the transistor 83, the drain and gate of the P transistor 85, and the gate of the P transistor 86 are commonly connected to a node N82. The source of the P transistor 85 and the source of the P transistor 86 are commonly connected to a power supply. The drain of the N transistor 84 and the drain of the P transistor 86 are commonly connected to a node N3.

Next, the connection contents inside the second sense amplifier 131 will be described. The source of the N transistor 92 is
The ground is connected, the drain is connected to the node N91, and the gate is connected to the power supply. The source of the N transistor 93 and the source of the N transistor 94 are commonly connected to the node N91. The drain of the N transistor 93, the drain and gate of the P transistor 95, and the gate of the P transistor 96 are commonly connected to a node N92. P transistor 95
And the source of the P transistor 96 are commonly connected to a power supply. The drain of the N transistor 94 and the drain of the P transistor 96 are commonly connected to a node N4.

The drain and gate of the P transistor 112 characteristic of the present invention are connected to the node N3 which is the output node of the first sense amplifier 121.
On the other hand, a node N4, which is an output node of the second sense amplifier 131, is connected to a P transistor
Drain and gate are connected. The sources of the P transistor 112 and the P transistor 113 are
Both are connected to the power supply.

Note that the third sense amplifier 231 is connected to the nodes N3, N4, and N5, similarly to the conventional input circuit 201. Further, an inverter 2 is connected to the node N5.
41, and an inverter 243 are sequentially connected.
A predetermined circuit (not shown) is connected to the output of the inverter 243, and an output signal O is supplied to the circuit.
The UT will be supplied.

The operation of the input circuit 111 having the above configuration according to the fifth embodiment will be described.

First, the voltages of input signals IN and INN (Vi
1, Vi2), when the input signal IN is at the L level and the input signal INN is at the H level, the voltage (Va1) at the node N3, which is the output node of the first sense amplifier 121, is low. , The second sense amplifier 1
It becomes lower than the voltage (Va2) of the node N4, which is the output node of No. 31. Therefore, the voltage (Va3) of the node N5 which is the output node of the third sense amplifier 231 becomes L level, and the output signal OUT output via the inverters 241 and 243 becomes L level.

When the voltage (Va1) of the node N3 decreases, the ON state of the P-transistor 112, which is characteristic of the present invention, increases, and the voltage of the node N3 is lower than that of the conventional input circuit 201 having no P-transistor 112. (Va
1) becomes higher.

On the other hand, the voltages of input signals IN and INN (Vi
In the time domain where there is no change in (1, Vi2), when the input signal IN is at the H level and the input signal INN is at the L level, the voltage (Va2) of the node N4, which is the output node of the second sense amplifier 131, becomes , First sense amplifier 1
It becomes lower than the voltage (Va1) of the node N3, which is the output node of No. 21. Therefore, the voltage (Va3) of the node N5 which is the output node of the third sense amplifier 231 becomes H level, and the output signal OUT output through the inverters 241 and 243 becomes H level.

When the voltage (Va2) of the node N4 decreases, the ON state of the P-transistor 113, which is characteristic of the present invention, increases, and the voltage of the node N4 is lower than that of the conventional input circuit 201 having no P-transistor 113. (Va
2) is higher.

As described above, according to the input circuit 111 according to the fifth embodiment of the present invention, the node N3
Is connected to the node N by the P transistor 112 connected to
3 is at the L level, the voltage value is increased, and P transistor 113 connected to node N4 provides
The voltage value when node N4 is at L level can be increased. Therefore, similarly to the input circuits 1, 31, 51, and 71 according to the first, second, third, and fourth embodiments, even if the frequency of the voltage fluctuation of the input signals IN and INN is high, the input signal IN , INN (Vi1,
It is possible to cause a sufficient difference between the peak voltage value of the node N3 and the peak voltage value of the node N4 with respect to the first change of Vi2). As a result, the input signals IN, I
Even when the voltage (Vi1, Vi2) of the NN switches at a high frequency of, for example, several hundred MHz or more, the input signal I
The first voltage fluctuation of N and INN can be reliably output as the output signal OUT. Since the first sense amplifier 121 and the second sense amplifier 131 are N-type sense amplifiers, the voltages of the input signals IN and INN are similar to those of the input circuit 71 according to the fourth embodiment. Even when the voltage is high and close to the power supply voltage, it is possible to reliably receive the voltage fluctuation of the input signals IN and INN.

Further, the first and second input circuits 111
Since the second and third sense amplifiers 121, 131, and 231 are all constituted by N-type sense amplifiers having substantially the same circuit, for example, when the input circuit 111 is formed on a semiconductor substrate, the manufacturing efficiency is reduced. As a result, the throughput is improved.

As described above, the preferred embodiments of the present invention have been described with reference to the accompanying drawings, but the present invention is not limited to such examples. It is clear that a person skilled in the art can conceive various changes or modifications within the scope of the technical idea described in the claims, and those modifications naturally fall within the technical scope of the present invention. It is understood to belong.

For example, in the input circuit 1 according to the first embodiment, the P circuit provided in the first sense amplifier 11
The source of the transistor 12 and the source of the P transistor 22 provided in the second sense amplifier 21 may be connected to a power supply.

Further, in the input circuit 71 according to the fourth embodiment, the N circuit provided in the first sense amplifier 81 is provided.
The source of the transistor 87 and the source of the N transistor 97 provided in the second sense amplifier 91 may be connected to the ground.

[0108]

As described above, according to the input circuit of the present invention, even if the voltage of the first input signal and the voltage of the second input signal fluctuate at a high speed, the input circuit can be used. It is possible to supply a stable third amplified signal to the connected predetermined circuit.

Further, according to the sixth and seventh aspects, since the amplitude of the voltage of the third amplified signal can be increased, for example, when this third amplified signal is input to a predetermined circuit such as an inverter gate, It is possible to improve the response speed of the operation.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an input circuit according to a first embodiment of the present invention.

FIG. 2 is a waveform chart showing an operation of the input circuit of FIG.

FIG. 3 is a circuit diagram of an input circuit according to a second embodiment of the present invention.

FIG. 4 is a waveform chart showing an operation of the input circuit of FIG.

FIG. 5 is a circuit diagram of an input circuit according to a third embodiment of the present invention.

FIG. 6 is a waveform chart showing the operation of the input circuit of FIG.

FIG. 7 is a circuit diagram of an input circuit according to a fourth embodiment of the present invention.

FIG. 8 is a circuit diagram of an input circuit according to a fifth embodiment of the present invention.

FIG. 9 is a circuit diagram of a conventional input circuit.

FIG. 10 is a waveform chart showing an operation of the input circuit of FIG. 9;

[Explanation of symbols]

 Reference Signs List 1 input circuit 11 first sense amplifier 21 second sense amplifier 231 third sense amplifier IN, INN input signal N3, N4 node OUT output signal

Claims (7)

[Claims] 1. A first amplifier for amplifying a difference between a voltage of a first input signal and a voltage of a second input signal and outputting a first amplified signal.
A second differential amplifier circuit that amplifies a difference between a voltage of the first input signal and a voltage of the second input signal and outputs a second amplified signal; And a third differential amplifier circuit for amplifying a difference between the voltage of the amplified signal of the second amplified signal and the voltage of the second amplified signal and outputting a third amplified signal. An input circuit comprising: first voltage adjusting means for adjusting the voltage of the amplified signal; and second voltage adjusting means for adjusting the voltage of the second amplified signal. 2. The method according to claim 1, wherein the first voltage adjusting means increases a logically low level voltage of the first amplified signal, and the second voltage adjusting means adjusts a logical low level voltage of the second amplified signal. 2. The input circuit according to claim 1, wherein the input circuit increases a logic low level voltage. 3. The first voltage adjusting means includes one electrode and a gate electrode to which the first amplified signal is applied, and
And a second electrode to which a voltage higher than the voltage of the first amplified signal is applied. The second voltage adjusting means includes a second voltage adjusting means, And a second electrode to which a voltage higher than the voltage of the second amplified signal is applied. The input circuit according to claim 2. 4. The first voltage adjusting means reduces a logically high level voltage in the first amplified signal, and the second voltage adjusting means reduces a logically high voltage in the second amplified signal. 2. The input circuit according to claim 1, wherein the input circuit reduces a logic high level voltage. 5. The first voltage adjusting means includes one electrode and a gate electrode to which the first amplified signal is applied, and
And a second electrode to which a voltage lower than the voltage of the first amplified signal is applied. The second voltage adjusting means includes: , And a second electrode to which a voltage lower than the voltage of the second amplified signal is applied. The input circuit according to claim 4. 6. The third differential amplifier circuit includes a constant current source whose output current is controlled according to the third amplified signal. 5. The input circuit according to any one of 5. 7. The input circuit according to claim 6, wherein the constant current source is a transistor having a gate electrode to which a signal having a phase opposite to that of the third amplified signal is input.