JPH11340571A - Nitride semiconductor element - Google Patents

Nitride semiconductor element

Info

Publication number
JPH11340571A
JPH11340571A JP14450298A JP14450298A JPH11340571A JP H11340571 A JPH11340571 A JP H11340571A JP 14450298 A JP14450298 A JP 14450298A JP 14450298 A JP14450298 A JP 14450298A JP H11340571 A JPH11340571 A JP H11340571A
Authority
JP
Japan
Prior art keywords
layer
nitride semiconductor
electrode
substrate
gan
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14450298A
Other languages
Japanese (ja)
Other versions
JP3360812B2 (en
Inventor
Takao Yamada
孝夫 山田
Shuji Nakamura
修二 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nichia Chemical Industries Ltd
Original Assignee
Nichia Chemical Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nichia Chemical Industries Ltd filed Critical Nichia Chemical Industries Ltd
Priority to JP14450298A priority Critical patent/JP3360812B2/en
Publication of JPH11340571A publication Critical patent/JPH11340571A/en
Application granted granted Critical
Publication of JP3360812B2 publication Critical patent/JP3360812B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Semiconductor Lasers (AREA)
  • Led Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To improve adhesion between an n-electrode and a supporting body by providing a first layer of metal obtaining ohmic contact with an n-type nitride semiconductor, a second layer containing a metal whose melting point is higher than that of Al and a third layer containing Sn in the n-electrode from a side close to a second main face. SOLUTION: An element structure having an n-side clad layer 14, formed of the superlattice structure of an undoped AlGaN layer and a Si doped n-type GaN layer and a p-side clad layer 18, formed of the super lattice structure of an Mg doped AlGaN layer and an undoped GaN layer, is formed in the first main face side of a nitride semiconductor substrate 10 formed of an n-type nitride semiconductor. An n-electrode 30 is formed on the second main face side of the nitride semiconductor substrate 10. A first layer 31 of a metal for obtaining ohmic contact with the n-type nitride semiconductor, a second layer 32 containing metal whose melting point is higher than Al, and a third layer 33 containing Sn or In, are stacked and formed in the n-electrode 30 from a side close to the second main face.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は窒化物半導体(InX
YGa1-X-YN、0≦X、0≦Y、X+Y≦1)からなる発
光ダイオード(LED)、レーザダイオード(LD)、
スーパールミネッセントダイオード(SLD)等の発光
素子、光センサー、太陽電池等の受光素子、あるいはト
ランジスタ、パワーデバイス等の電子デバイスに使用さ
れる窒化物半導体素子に関する。
The present invention relates to a nitride semiconductor (In XA).
a light emitting diode (LED), a laser diode (LD) composed of l Y Ga 1-XY N, 0 ≦ X, 0 ≦ Y, X + Y ≦ 1);
The present invention relates to a light emitting element such as a super luminescent diode (SLD), an optical sensor, a light receiving element such as a solar cell, or a nitride semiconductor element used for an electronic device such as a transistor or a power device.

【0002】[0002]

【従来の技術】我々はGaN基板の上に、活性層を含む
窒化物半導体レーザ素子を作製して、世界で初めて室温
での連続発振1万時間以上を達成したことを発表した
(ICNS'97 予稿集,October 27-31,1997,P444-446、及び
Jpn.J.Appl.Phys.Vol.36(1997)pp.L1568-1571)。さら
に、前記レーザ素子よりサファイアを除去してGaN単
独とすることにより、5mW出力でも1万時間以上の連
続発振に成功したことを発表した。(Jpn.J.Appl.Phys.
Vol.37(1998)pp.L309-L312、及びAppl.Phys.Lett.Vol.7
2(1998)No.16,2014-2016)
2. Description of the Related Art We have manufactured a nitride semiconductor laser device including an active layer on a GaN substrate and have achieved the world's first continuous oscillation of over 10,000 hours at room temperature (ICNS'97). Proceedings, October 27-31, 1997, P444-446, and
Jpn.J.Appl.Phys.Vol.36 (1997) pp.L1568-1571). Furthermore, it was announced that continuous oscillation of 10,000 hours or more was achieved even at a power of 5 mW by removing sapphire from the laser element and using GaN alone. (Jpn.J.Appl.Phys.
Vol.37 (1998) pp.L309-L312 and Appl.Phys.Lett.Vol.7
2 (1998) No. 16, 2014-2016)

【0003】以上のレーザ素子は、アンドープGaN基
板のキャリア濃度が不十分であるため、そのGaN裏面
側からn電極を取り出さず、窒化物半導体面側からn電
極、及びp電極を取り出した構造となっている。このよ
うに同一面側からn、p、2種類の電極を取り出す構造
ではチップサイズが大きくなるため、チップサイズを小
さくするためには、基板裏面側から電極を取り出す必要
がある。しかしアンドープGaNはキャリア濃度が低い
ので電極を形成できず、ある程度のキャリア濃度を得る
ためには、GaN基板成長中にn型不純物をドープしな
ければならない。
The above laser device has a structure in which the n-electrode and p-electrode are taken out from the nitride semiconductor surface side without taking out the n-electrode from the GaN back surface side because the carrier concentration of the undoped GaN substrate is insufficient. Has become. In such a structure in which n, p and two types of electrodes are taken out from the same surface side, the chip size becomes large. Therefore, in order to reduce the chip size, it is necessary to take out the electrodes from the back surface side of the substrate. However, since undoped GaN has a low carrier concentration, an electrode cannot be formed. In order to obtain a certain carrier concentration, n-type impurities must be doped during GaN substrate growth.

【0004】[0004]

【発明が解決しようとする課題】GaN基板にn型不純
物をドープして、例えば1017/cm3以上のキャリア濃
度が得られると、基板の裏面側からn電極を取り出すこ
とができる。基板の裏面側に電極が設けられる場合、電
極形成前に基板の裏面側はポリシングされて鏡面状にさ
れることが多い。ポリシングでは例えばダイヤモンド研
磨剤が用いられるため、n型窒化物半導体成長面(as-g
rown)面に比較して、その表面に受けるダメージが大き
い。そのため基板面とn電極とで良好なオーミックを得
ようとすると、特別な工夫が必要である。
When a GaN substrate is doped with an n-type impurity to obtain a carrier concentration of, for example, 10 17 / cm 3 or more, an n-electrode can be taken out from the back surface of the substrate. When an electrode is provided on the back surface of the substrate, the back surface of the substrate is often polished to a mirror surface before forming the electrode. In polishing, for example, a diamond abrasive is used, so that the n-type nitride semiconductor growth surface (as-g
The damage to the surface is greater than that of the rown) surface. Therefore, a special device is required to obtain a good ohmic between the substrate surface and the n-electrode.

【0005】また、n電極側を支持体にダイボンドする
と、ダイボンド材料により電極のオーミック性が失われ
る可能性がある。特にレーザ素子のように局所的に高温
となる素子では時間経過と共に、熱によりオーミック性
が失われると、駆動電圧が上昇し、素子寿命に直接関わ
ってくる。また、窒化物半導体基板を用いた新規な構造
の素子では、n電極と支持体とを強固に接着させる接着
技術も良く知られていないのが実状である。
When the n-electrode side is die-bonded to the support, the ohmic property of the electrode may be lost due to the die-bonding material. In particular, in an element such as a laser element, which has a locally high temperature, if the ohmic property is lost due to heat with the passage of time, the driving voltage increases and directly affects the element life. In addition, in a device having a novel structure using a nitride semiconductor substrate, a bonding technique for firmly bonding an n-electrode and a support is not well known.

【0006】従って、本発明はGaN基板を用いた素子
を実用化するに際し、GaN基板の裏面側に設けられた
n電極と支持体との接着性、及びn電極のオーミック性
を維持できる信頼性に優れた窒化物半導体素子を実現す
ることにある。
Accordingly, when the present invention is applied to the practical use of an element using a GaN substrate, the reliability of maintaining the adhesiveness between the n-electrode provided on the back side of the GaN substrate and the support and the ohmic property of the n-electrode can be maintained. Another object of the present invention is to realize a nitride semiconductor device having excellent characteristics.

【0007】[0007]

【課題を解決するための手段】本発明の窒化物半導体素
子は、n型窒化物半導体よりなる窒化物半導体基板の第
1の主面側に、n型窒化物半導体層及びp型窒化物半導
体層を有する素子構造が形成され、その窒化物半導体基
板の第2の主面側にn電極が形成され、そのn電極と支
持体とが対向して素子が支持体にダイボンディングされ
てなる窒化物半導体素子であって、前記n電極は、第2
の主面に接近した側から、n型窒化物半導体と良好なオ
ーミック接触が得られる金属を含む第1の層と、Alよ
りも高融点金属を含む第2の層と、Sn若しくはInを
含む第3の層とを有する少なくとも3層構造を具備する
ことを特徴とする。
A nitride semiconductor device according to the present invention comprises an n-type nitride semiconductor layer and a p-type nitride semiconductor on a first main surface side of a nitride semiconductor substrate made of an n-type nitride semiconductor. An element structure having a layer is formed, an n-electrode is formed on the second main surface side of the nitride semiconductor substrate, and the n-electrode and the support face each other, and the element is die-bonded to the support. A semiconductor device, wherein the n-electrode comprises a second
A first layer containing a metal that provides good ohmic contact with the n-type nitride semiconductor, a second layer containing a metal having a higher melting point than Al, and Sn or In And at least a three-layer structure including a third layer.

【0008】また、本発明の素子では、前記n電極と第
2の主面との間に、n型不純物がドープされた窒化物半
導体層が成長されていることを特徴とする。その窒化物
半導体層のn型不純物濃度は、第2の主面近傍の窒化物
半導体基板のn型不純物濃度よりも大きくすることが望
ましい。
In the device according to the present invention, a nitride semiconductor layer doped with an n-type impurity is grown between the n-electrode and the second main surface. It is desirable that the n-type impurity concentration of the nitride semiconductor layer be higher than the n-type impurity concentration of the nitride semiconductor substrate near the second main surface.

【0009】第1の層はW、Al、Ti、Zr、V、N
bからなる群から選択された少なくとも一種の金属を含
むことを特徴とする。好ましい具体例としては、W/A
l、Ti/Al、Ti/Au、V/Al、V/Auが挙
げられる。
The first layer is made of W, Al, Ti, Zr, V, N
b. At least one metal selected from the group consisting of b. As a preferred specific example, W / A
1, Ti / Al, Ti / Au, V / Al, and V / Au.

【0010】第2の層はW、Ti、Zr、Pt、Mo、
Au、Niからなる群から選択された少なくとも一種の
金属を含むことを特徴とする。
The second layer is made of W, Ti, Zr, Pt, Mo,
It contains at least one metal selected from the group consisting of Au and Ni.

【0011】第3の層はAu、Ge、Si、Agからな
る群から選択された少なくとも一種の金属と、Sn若し
くはInとを含むことを特徴とする。好ましい組み合わ
せとしては、Au/Sn(In)、Au/Ge/Sn
(In)、Au/Ag/Sn(In)が挙げられる。
The third layer is characterized by containing at least one metal selected from the group consisting of Au, Ge, Si, and Ag, and Sn or In. Preferred combinations are Au / Sn (In), Au / Ge / Sn
(In) and Au / Ag / Sn (In).

【0012】また、窒化物半導体基板の第1の主面と、
第2の主面との間に少なくともInを含む窒化物半導体
層が形成されていることを特徴とする。Inを含む窒化
物半導体は、InGaN層を有する層が好ましく、単層
でもまたInGaNとInを含まない層とを積層した多
層膜でも良い。この層を形成することにより、窒化物半
導体基板が劈開されやすくなる傾向にある。基板を劈開
する場合、窒化物半導体のM面(11−00)、即ち、
窒化物半導体の結晶形を6角柱で近似した場合、その側
面に相当する6種類の面で劈開することが望ましい。
A first main surface of the nitride semiconductor substrate;
A nitride semiconductor layer containing at least In is formed between the second semiconductor layer and the second main surface. The nitride semiconductor containing In is preferably a layer having an InGaN layer, and may be a single layer or a multilayer film in which InGaN and a layer not containing In are stacked. By forming this layer, the nitride semiconductor substrate tends to be easily cleaved. When cleaving the substrate, the M-plane (11-00) of the nitride semiconductor, that is,
When the crystal form of the nitride semiconductor is approximated by a hexagonal prism, it is desirable to cleave at six types of planes corresponding to the side surfaces.

【0013】[0013]

【発明の実施の形態】本発明ではn型不純物をドープし
たn型窒化物半導体基板の第2の主面(以下、第2の主
面を裏面ということがある。)側に、少なくとも3層構
造を有するn電極を設けている。第1の層は基板裏面側
のn型窒化物半導体と良好なオーミックを得るための電
極材料を含む層である。またこの第1の層は窒化物半導
体基板の裏面に必ずしも接して形成する必要はなく、例
えば、窒化物半導体基板の裏面上に、さらに成長された
窒化物半導体層を介して成長されていても良い。裏面側
にさらに成長される窒化物半導体層のn型不純物濃度
は、窒化物半導体基板裏面近傍のn型不純物濃度(例え
ば5μm)よりも、大きくすることが望ましい。この作
用は、新たに窒化物半導体を裏面側に成長させることに
より、研磨、剥離等により裏面側に受けたダメージをas
-grownの窒化物半導体で回復することができる。さら
に、その新たに成長させる窒化物半導体層のn型不純物
濃度を、裏面近傍よりも大きくして、その層をコンタク
ト層とすると、オーミック性がさらに良くなり、順方向
電圧を低下させることができる。
DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, at least three layers are provided on a second main surface (hereinafter, the second main surface is sometimes referred to as a back surface) of an n-type nitride semiconductor substrate doped with an n-type impurity. An n-electrode having a structure is provided. The first layer is a layer containing an n-type nitride semiconductor on the back surface of the substrate and an electrode material for obtaining a good ohmic. The first layer does not necessarily need to be formed in contact with the back surface of the nitride semiconductor substrate. For example, even if the first layer is grown on the back surface of the nitride semiconductor substrate via the nitride semiconductor layer further grown. good. It is desirable that the n-type impurity concentration of the nitride semiconductor layer further grown on the back surface side be higher than the n-type impurity concentration (for example, 5 μm) near the back surface of the nitride semiconductor substrate. This effect is achieved by newly growing a nitride semiconductor on the back surface side, so that the damage on the back side due to polishing, peeling, etc. is reduced.
-Can be recovered with grown nitride semiconductor. Further, when the n-type impurity concentration of the newly grown nitride semiconductor layer is made higher than that near the rear surface and the layer is used as a contact layer, the ohmic property is further improved and the forward voltage can be reduced. .

【0014】窒化物半導体基板のn型不純物濃度は5×
1016/cm3以上、5×1018/cm3以下で、好ましくは
1×1018/cm3以下に調整する。5×1018/cm3より
も多いと、窒化物半導体基板の結晶性が悪くなって、結
晶欠陥が多くなる傾向にある。また5×1016/cm3
りも少ないと、十分なキャリア濃度が窒化物半導体基板
に付与できず、裏面側に電極を形成すると、駆動電圧が
高くなる。裏面側に新たに形成する窒化物半導体層の好
ましい不純物濃度としては5×1017/cm3以上、好ま
しくは1×1018/cm3以上、さらに好ましくは3×1
18/cm3以上にする。またこの高n型不純物濃度の窒
化物半導体と第2の主面との間に、アンドープ若しくは
n型不純物濃度が裏面近傍よりも少ない窒化物半導体を
0.1μm以下の膜厚で形成しても良い。アンドープ、
少量n型不純物濃度の窒化物半導体層は、裏面側に受け
たダメージを回復して、高キャリア濃度のn型窒化物半
導体をその上に成長しやすくする。n型不純物としては
Si、Ge、Sn、S、Ti、Zr等が挙げられるが、
最も好ましくはSiを用いる。なお、高不純物濃度の窒
化物半導体の膜厚は特に限定しないが、通常10オング
ストローム以上、10μm以下の膜厚で成長させること
が望ましい。
The n-type impurity concentration of the nitride semiconductor substrate is 5 ×
It is adjusted to 10 16 / cm 3 or more and 5 × 10 18 / cm 3 or less, preferably 1 × 10 18 / cm 3 or less. If it is more than 5 × 10 18 / cm 3, the crystallinity of the nitride semiconductor substrate tends to deteriorate, and the number of crystal defects tends to increase. If it is less than 5 × 10 16 / cm 3 , a sufficient carrier concentration cannot be imparted to the nitride semiconductor substrate, and if an electrode is formed on the back surface side, the driving voltage becomes high. The preferred impurity concentration of the newly formed nitride semiconductor layer on the back side is 5 × 10 17 / cm 3 or more, preferably 1 × 10 18 / cm 3 or more, and more preferably 3 × 1 / cm 3 or more.
0 18 / cm 3 or more. Further, between the nitride semiconductor having a high n-type impurity concentration and the second main surface, a nitride semiconductor having an undoped or n-type impurity concentration lower than that near the back surface is formed to a thickness of 0.1 μm or less. good. Undoped,
The nitride semiconductor layer having a small amount of n-type impurity concentration recovers damage received on the back surface side, and facilitates the growth of a high carrier concentration n-type nitride semiconductor thereon. Examples of the n-type impurities include Si, Ge, Sn, S, Ti, and Zr.
Most preferably, Si is used. Although the thickness of the nitride semiconductor having a high impurity concentration is not particularly limited, it is generally preferable to grow the nitride semiconductor with a thickness of 10 Å to 10 μm.

【0015】窒化物半導体基板の第1の主面上に素子構
造を形成して、第2の主面側に電極を形成して、第2の
主面側をダイボンディングする場合、その接着性、電極
材料の安定性が非常に重要である。本発明の素子では、
第1の層によりn型窒化物半導体と良好なオーミック接
触を得ている。さらに、第2の層はバリア層であり、素
子駆動中、電極形成時あるいはメタライジング等の熱処
理により、電極材料が拡散して、オーミックを損なわな
いようにしている。さらに第3の層は支持体との低温で
の接着強化層であり、Sn、若しくはInを含む層とす
ることにより、例えばヒートシンク、サブマウント、リ
ードフレームのような支持体のの密着性を向上させるこ
とができる。しかし前記のように、熱処理等でSn、I
nが拡散すると、n電極のオーミック性を悪くする恐れ
がある。本発明ではAlよりも高融点金属を有する第2
の層がバリア層として作用しているため、第3の層に含
まれるSn、Inが拡散することが無く、安定したオー
ミックが得られることができる。さらに、通常ウェーハ
からチップ状の素子を作製する場合、基板裏面側にn電
極を形成してから、劈開、ダイシング等により分離され
る。本発明の素子ではn電極が3層構造を有しているた
めに、劈開時、ダイシング等の物理的作用により電極と
基板との界面にストレスが係っても、電極が基板から剥
がれにくくなる。
When an element structure is formed on the first main surface of the nitride semiconductor substrate, an electrode is formed on the second main surface side, and the second main surface side is die-bonded, the adhesiveness is high. In addition, the stability of the electrode material is very important. In the device of the present invention,
Good ohmic contact with the n-type nitride semiconductor is obtained by the first layer. Further, the second layer is a barrier layer, which prevents the electrode material from diffusing due to heat treatment during element driving, electrode formation, metallizing, or the like, and does not damage ohmic. Further, the third layer is a low-temperature adhesion-enhancing layer with the support, and is made of a layer containing Sn or In to improve the adhesion of the support such as a heat sink, a submount, or a lead frame. Can be done. However, as described above, Sn, I
If n diffuses, the ohmic property of the n electrode may be deteriorated. In the present invention, a second metal having a metal having a higher melting point than Al is used.
Since the layer functions as a barrier layer, Sn and In contained in the third layer are not diffused, and a stable ohmic can be obtained. Furthermore, when a chip-shaped element is manufactured from a normal wafer, an n-electrode is formed on the back surface of the substrate and then separated by cleavage, dicing, or the like. In the device of the present invention, since the n-electrode has a three-layer structure, even when stress is applied to the interface between the electrode and the substrate due to a physical action such as dicing during cleavage, the electrode is hardly peeled off from the substrate. .

【0016】第1の層はW、Al、Ti、Zr、V、N
bからなる群から選択された少なくとも一種の金属を含
み、好ましくはこの内の少なくとも2種類、少なくとも
一種とAuを加えた、少なくとも2種類とすることが望
ましい。第1の層は合金の状態でも、あるいは多層膜構
造でも良い。好ましい具体例としては、W/Al、Ti
/Al、Ti/Au、V/Al、V/Auが挙げられ、
これらの組み合わせにおいて、金属の比は特に限定しな
い。
The first layer is made of W, Al, Ti, Zr, V, N
At least one metal selected from the group consisting of b, preferably at least two of these, and at least two of at least one and Au added. The first layer may be in an alloy state or a multilayer structure. Preferred specific examples include W / Al, Ti
/ Al, Ti / Au, V / Al, V / Au,
In these combinations, the metal ratio is not particularly limited.

【0017】第2の層はW、Ti、Zr、Pt、Mo、
Au、Niからなる群から選択された少なくとも一種の
金属を含み、特に好ましくはW、Ti、Pt、Niを用
いる。これらの金属はバリア層として作用し、第3の層
のSn、Inが第1の層に拡散するのを防止できる。第
2の層は第1の層よりも厚く形成する方がバリア層とし
て好ましい。
The second layer is composed of W, Ti, Zr, Pt, Mo,
It contains at least one metal selected from the group consisting of Au and Ni, and particularly preferably uses W, Ti, Pt and Ni. These metals function as barrier layers, and can prevent Sn and In of the third layer from diffusing into the first layer. The second layer is preferably formed thicker than the first layer as a barrier layer.

【0018】第3の層はAu、Ge、Si、Agからな
る群から選択された少なくとも一種の金属と、Sn若し
くはInとを含む層とすることが望ましい。好ましい組
み合わせとしては、Au/Sn(In)、Au/Ge/
Sn(In)、Au/Ag/Sn(In)が挙げられ、
第3の層も合金の状態でも、多層膜の状態でも良い。こ
れらの組み合わせからなる層は、特に支持体と強い接着
力を有する。
The third layer is preferably a layer containing at least one metal selected from the group consisting of Au, Ge, Si, and Ag, and Sn or In. Preferred combinations are Au / Sn (In), Au / Ge /
Sn (In), Au / Ag / Sn (In),
The third layer may be in the form of an alloy or a multilayer. Layers composed of these combinations have a particularly strong adhesion to the support.

【0019】例えば、基板の劈開により少なくとも一つ
の端面が露出されるようにチップ状に分離される場合、
n電極は基板の裏面のほぼ全面に形成されていても、本
発明の3層構造の電極は裏面から剥がれにくい。
For example, when the substrate is separated into chips so that at least one end face is exposed by cleavage of the substrate,
Even if the n-electrode is formed on almost the entire back surface of the substrate, the electrode having the three-layer structure of the present invention is hardly peeled off from the back surface.

【0020】[0020]

【実施例】図1は本発明の一実施例に係るレーザ素子の
構造を示す模式的な断面図であり、共振面に平行な方向
で素子を切断した際の図を示すものである。以下、この
図を元に実施例1について説明する。なお本発明の素子
はレーザ素子に限定されるものではない。
FIG. 1 is a schematic sectional view showing the structure of a laser device according to one embodiment of the present invention, and shows a view when the device is cut in a direction parallel to a resonance surface. Hereinafter, Embodiment 1 will be described with reference to FIG. The device of the present invention is not limited to a laser device.

【0021】[実施例1]2インチ角のSiドープGa
Nよりなる窒化物半導体基板10を用意する。この窒化
物半導体基板10は、以下のようにして成長させたもの
である。
[Example 1] 2 inch square Si-doped Ga
A nitride semiconductor substrate 10 made of N is prepared. This nitride semiconductor substrate 10 is grown as follows.

【0022】(窒化物半導体基板10)2インチφ、C
面を主面とするサファイアよりなる異種基板1をMOV
PE反応容器内にセットし、500℃で、トリメチルガ
リウム(TMG)、アンモニア(NH3)を用い、Ga
Nよりなる低温バッファ層を200オングストロームの
膜厚で成長させる。低温バッファ層成長後、1050℃
で同じくGaNよりなる下地層を4μmの膜厚で成長さ
せる。下地層成長後、ウェーハを反応容器から取り出
し、この下地層の表面に、ストライプ幅10μm、スト
ライプ間隔(窓部)2μmのSiO2よりなる保護膜を
形成する。保護膜形成後、ウェーハを再度MOVPEの
反応容器内にセットし、温度を1050℃にして、TM
G、アンモニアを用い、アンドープGaN層を5μm成
長させ、SiO2の表面を覆う。
(Nitride semiconductor substrate 10) 2 inch φ, C
MOV of a heterogeneous substrate 1 made of sapphire whose main surface is
It was set in a PE reaction vessel, and at 500 ° C., trimethylgallium (TMG) and ammonia (NH 3 ) were used.
A low temperature buffer layer of N is grown to a thickness of 200 Å. 1050 ° C after low temperature buffer layer growth
Then, an underlayer made of GaN is also grown to a thickness of 4 μm. After the growth of the underlayer, the wafer is taken out of the reaction vessel, and a protective film made of SiO 2 having a stripe width of 10 μm and a stripe interval (window portion) of 2 μm is formed on the surface of the underlayer. After the formation of the protective film, the wafer was set again in the MOVPE reaction vessel, the temperature was set to 1050 ° C., and the TM
An undoped GaN layer is grown to a thickness of 5 μm using G and ammonia to cover the surface of SiO 2 .

【0023】第1のGaN層11:成長後、ウェーハを
MOVPE装置からHVPE装置に移送しGaメタル
と、アンモニア、HCl、不純物ガスとしてシランガス
を用い、Siを3×1017/cm3ドープしたn型GaN
層よりなる第1のGaN層11を200μmの膜厚で成
長させる。
First GaN layer 11: After growth, the wafer is transferred from the MOVPE apparatus to the HVPE apparatus, and Ga metal, ammonia, HCl, and silane gas are used as impurity gases, and n is doped with Si at 3 × 10 17 / cm 3. Type GaN
A first GaN layer 11 composed of a layer is grown to a thickness of 200 μm.

【0024】中間層12:次に800℃において、TM
I(トリメチルインジウム)、TMG、アンモニアを用
い、アンドープIn0.3Ga0.7Nよりなる中間層12を
500オングストローム成長させる。
Intermediate layer 12: Next, at 800 ° C., TM
Using I (trimethylindium), TMG, and ammonia, an intermediate layer 12 made of undoped In 0.3 Ga 0.7 N is grown to 500 Å.

【0025】第2のGaN層13:次に、900℃にし
て、Siを1×1018/cm3ドープしたGaNよりなる
第2のGaN層13を1μmの膜厚で成長させる。第2
のGaN層13は、中間層12の成長温度とほぼ同じ、
若しくは中間層の成長温度より高温で、かつn側クラッ
ド層21の成長温度よりも低温で成長させることによ
り、Inを含む中間層の分解を防止でき、結晶性の良い
層を成長できる。なおこの第2のGaN層は窒化第1の
GaN層と同一組成とすることが望ましい。第2のGa
N層成長後、サファイア基板側から研磨して、サファイ
ア基板、低温成長バッファ層、下地層、保護膜及びアン
ドープGaN層を除去することにより、総膜厚170μ
mの第1のGaN層11、中間層12及び第2のGaN
層13からなる窒化物半導体基板10を作製する。な
お、中間層12及び第2のGaN層13は、第1のGa
N層11成長後、サファイア基板からアンドープGaN
層までを除去した後、as-grown側の第1のGaN層の表
面に形成しても良い。
Second GaN layer 13: Next, at 900 ° C., a second GaN layer 13 made of GaN doped with 1 × 10 18 / cm 3 of Si is grown to a thickness of 1 μm. Second
GaN layer 13 is substantially the same as the growth temperature of the intermediate layer 12,
Alternatively, by growing at a temperature higher than the growth temperature of the intermediate layer and lower than the growth temperature of the n-side cladding layer 21, decomposition of the intermediate layer containing In can be prevented, and a layer having good crystallinity can be grown. It is desirable that the second GaN layer has the same composition as the first nitrided GaN layer. Second Ga
After growing the N layer, the sapphire substrate is polished from the sapphire substrate side to remove the sapphire substrate, the low-temperature growth buffer layer, the underlayer, the protective film, and the undoped GaN layer.
m of the first GaN layer 11, the intermediate layer 12, and the second GaN
The nitride semiconductor substrate 10 including the layer 13 is manufactured. Note that the intermediate layer 12 and the second GaN layer 13 are formed of the first Ga
After growing the N layer 11, undoped GaN is deposited from the sapphire substrate.
After removing up to the layer, it may be formed on the surface of the first GaN layer on the as-grown side.

【0026】(素子構造成長)次に、第2のGaN層1
3の上に、30オングストロームのアンドープAl0.16
Ga0.84N層/30オングストロームのSiドープn型
GaN層との超格子構造からなる総膜厚1.2μmのn
側クラッド層14 0.1μmのアンドープGaNからなるn側光ガイド層
15、100オングストロームのSiドープIn0.02
0.98N障壁層/40オングオングストロームのアンド
ープIn0.15Ga0.85N井戸層との多重量子井戸構造か
らなる総膜厚380オングストロームの活性層16 0.1μmのアンドープGaNからなるp側光ガイド層
17 30オングストロームのMgドープAl0.16Ga0.84
層/30オングストロームのアンドープGaN層との超
格子構造からなる総膜厚0.6μmp側クラッド層18 150オングストロームのMgドープp型GaNからな
るp側コンタクト層19を順に積層する。
(Element Structure Growth) Next, the second GaN layer 1
3 on top of 30 Angstroms of undoped Al 0.16
N having a total thickness of 1.2 μm and having a superlattice structure of a Ga 0.84 N layer / 30 Å Si-doped n-type GaN layer
Side cladding layer 14 0.1 μm undoped GaN n-side light guide layer 15, 100 Å Si-doped In 0.02 G
a 0.98 N barrier layer / 40 Å undoped In 0.15 Ga 0.85 N well layer and a multiple quantum well structure with a total film thickness of 380 Å 16 active layer 16 0.1 μm undoped GaN p-side optical guide layer 17 30 Angstrom Mg-doped Al 0.16 Ga 0.84 N
A total thickness of 0.6 μmp-side cladding layer 18 having a superlattice structure with a layer / 30 Å undoped GaN layer A p-side contact layer 19 made of 150 Å Mg-doped p-type GaN is sequentially laminated.

【0027】(n側コンタクト層40)活性層を含むダ
ブルへテロ構造の素子構造成長後、ウェーハを反対にひ
っくり返し、サファイア基板除去側の窒化物半導体基板
10を上にする。そしてこの研磨側の窒化物半導体基板
10の上に、Siを3×1018/cm3ドープしたGaN
よりなるn側コンタクト層40を5μmの膜厚で成長さ
せる。
(N-side contact layer 40) After the growth of the device structure having the double hetero structure including the active layer, the wafer is turned upside down, and the nitride semiconductor substrate 10 on the side from which the sapphire substrate is removed faces upward. Then, on the polished nitride semiconductor substrate 10, GaN doped with 3 × 10 18 / cm 3 of Si was used.
The n-side contact layer 40 is grown to a thickness of 5 μm.

【0028】(p電極形成工程)以上のようにして窒化
物半導体を成長させたウェーハを反応容器から取り出
し、最上層のp側コンタクト層19の表面に、所定の形
状のマスクを介して、幅1.5μmのストライプからな
るSiO2よりなる保護膜を形成する。保護膜形成後、
図1に示すように、p側クラッド層18とp側光ガイド
層17との界面付近までエッチングを行い、幅1.5μ
mのストライプ状の導波路を形成する。
(P-electrode forming step) The wafer on which the nitride semiconductor has been grown as described above is taken out of the reaction vessel, and the width of the wafer is formed on the surface of the uppermost p-side contact layer 19 through a mask having a predetermined shape. A protective film made of SiO 2 consisting of 1.5 μm stripes is formed. After forming the protective film,
As shown in FIG. 1, the etching was performed to the vicinity of the interface between the p-side cladding layer 18 and the p-side light guide layer 17 and the width was 1.5 μm.
An m-shaped striped waveguide is formed.

【0029】ストライプ導波路形成後、窒化物半導体層
の表面にZrO2よりなる絶縁膜100を形成する。絶
縁膜100形成後、p側コンタクト層の上に形成したS
iO 2を溶解除去し、リフトオフ法によりSiO2と共
に、p側コンタクト層の上にあるZrO2を除去する。
After forming the stripe waveguide, the nitride semiconductor layer
ZrO on the surface ofTwoAn insulating film 100 is formed. Absolute
After the edge film 100 is formed, the S film formed on the p-side contact layer
iO TwoIs dissolved and removed by lift-off method.TwoWith
The ZrO on the p-side contact layerTwoIs removed.

【0030】絶縁膜100形成後、Ni/Auからなる
p電極20を図1に示すように、絶縁膜100を介して
p側コンタクト層19と良好なオーミックが得られるよ
うに形成する。
After the formation of the insulating film 100, a p-electrode 20 made of Ni / Au is formed so as to obtain a good ohmic contact with the p-side contact layer 19 via the insulating film 100 as shown in FIG.

【0031】(n電極30形成工程) 第1の層31:次に、n側コンタクト層40のほぼ全面
にTiを0.01μm、その上にAlを0.05μm製
膜する。 第2の層32:第1の層と同一面積で、Ti0.05μ
mを製膜し、その上にとNi0.05μmを製膜して第
2の層32を0.1μm製膜する。 第3の層33:第2の層の上にAu(80%)/Sn
(20%)合金よりなる第3の層を1μm製膜する。
(Step of Forming N-Electrode 30) First Layer 31: Next, Ti is formed on substantially the entire surface of the n-side contact layer 40 at 0.01 μm, and Al is formed thereon at 0.05 μm. Second layer 32: the same area as the first layer, Ti0.05μ
m is formed, and Ni and 0.05 μm are formed thereon to form the second layer 32 having a thickness of 0.1 μm. Third layer 33: Au (80%) / Sn on the second layer
(20%) A third layer of an alloy is formed to a thickness of 1 μm.

【0032】その後、ウェーハを300℃で熱処理す
る。熱処理後、電極を部分的にエッチングして、電極間
の電流、電圧をオーミックコンタクトを測定したとこ
ろ、ほぼ直線を示し、良好なオーミックコンタクトが得
られていることが確認された。
Thereafter, the wafer is heat-treated at 300.degree. After the heat treatment, the electrodes were partially etched, and the current and voltage between the electrodes were measured for the ohmic contact. As a result, it was confirmed that a substantially ohmic contact was obtained, indicating that a good ohmic contact was obtained.

【0033】以上のようにしてp、n両電極形成後、窒
化物半導体基板10のM面で基板10を劈開して、ウェ
ーハをバー(bar)状と成し、そのバーの劈開面に共振面
を作製する。さらに共振面に垂直な方向でバーをダイシ
ングして400μm(共振器長)×400μm角のレー
ザチップとする。レーザチップ作製後、n電極がn側コ
ンタクト層40から剥がれたものはなかった。
After the formation of the p and n electrodes as described above, the substrate 10 is cleaved at the M plane of the nitride semiconductor substrate 10 to form a bar into a wafer, and resonance occurs at the cleaved surface of the bar. Make a surface. Further, the bar is diced in a direction perpendicular to the resonance surface to obtain a laser chip of 400 μm (resonator length) × 400 μm square. After the fabrication of the laser chip, none of the n-electrodes was peeled off from the n-side contact layer 40.

【0034】レーザチップ作製後、n電極30側をAu
でメタライズされたヒートシンクに熱圧着して、図1に
示すようにAu線をワイヤーボンディングしてレーザ素
子とする。このレーザ素子に室温でレーザ発振を試みた
ところ、発振波長408.5nm、閾値電流密度2kA
/cm2において室温連続発振を示し、閾値における電圧
は従来のものに比較して、約10%低下した。さらに電
流値を上げて出力を上げ、40mWとして20時間連続
発振させた後も、40mWにおける電圧、電流とも、最
初とほとんど変化しなかった。また素子の長辺の方向か
ら、真横に1kgの加重を負荷して素子を剥がそうと試
みたところ、強固に付着しており、素子の剥がれは無か
った。
After the fabrication of the laser chip, the n-electrode 30 side is Au
Is heat-pressed onto the metalized heat sink, and an Au wire is wire-bonded as shown in FIG. 1 to form a laser element. When laser oscillation was attempted on this laser device at room temperature, the oscillation wavelength was 408.5 nm, and the threshold current density was 2 kA.
/ Cm 2 showed continuous oscillation at room temperature, and the voltage at the threshold decreased by about 10% as compared with the conventional one. Even after the current value was further increased and the output was increased, and continuous oscillation was performed at 40 mW for 20 hours, both the voltage and the current at 40 mW hardly changed from the first. Further, when an attempt was made to peel the element by applying a load of 1 kg to the side from the long side of the element and the element was peeled off, the element was firmly attached and there was no peeling of the element.

【0035】さらに実施例1において、第2の層をTi
/Niに代えて、W、Zr、Pt、Mo、Auをそれぞ
れ0.1μm厚で形成したところ、実施例1とほぼ同一
の特性を有するレーザ素子が得られた。
Further, in Example 1, the second layer was made of Ti
When W, Zr, Pt, Mo, and Au were each formed to a thickness of 0.1 μm instead of / Ni, a laser element having almost the same characteristics as in Example 1 was obtained.

【0036】一方、実施例1で第2の層をAlとしたと
ころ、時間経過と共に、閾値電流、電圧が上昇し、約1
0時間で素子の寿命がつきた。そのn電極を分析してみ
ると、第1の層は積層構造ではなく、TiとAlとが一
部合金したような状態となり、さらに第1の層側にSn
が拡散してきていた。なお本実施例では第1の層は一部
Ti、Alが合金化した状態、第2層はNi、Tiが一
部合金化した状態となっていた。
On the other hand, when the second layer was made of Al in Example 1, the threshold current and the voltage increased over time,
The life of the device was extended at 0 hours. When the n-electrode is analyzed, the first layer does not have a laminated structure, but has a state in which Ti and Al are partially alloyed.
Was spreading. In this example, the first layer was in a state where Ti and Al were partially alloyed, and the second layer was in a state where Ni and Ti were partially alloyed.

【0037】[実施例2]実施例1のn電極30形成工
程において、第1の層をW(0.01μm)/Al
(0.05μm)との積層構造とし、第2の層にW
(0.1μm)を形成し、第3の層にAu(80%)、
Sn(20%)を含む層とする他は実施例1と同様にし
てレーザ素子を作製したところ、実施例1とほぼ同等の
特性を有する素子が得られた。さらに中間層にWに代え
てTi、Zr、Pt、Mo、Au、Niをそれぞれ同一
膜厚で形成したところ、ほぼ同等の特性を有する素子が
得られた。
[Embodiment 2] In the step of forming the n-electrode 30 of the embodiment 1, the first layer is formed of W (0.01 μm) / Al
(0.05 μm), and the second layer has W
(0.1 μm), and Au (80%) in the third layer,
A laser device was manufactured in the same manner as in Example 1 except that a layer containing Sn (20%) was used. As a result, an element having substantially the same characteristics as in Example 1 was obtained. Furthermore, when Ti, Zr, Pt, Mo, Au, and Ni were formed in the intermediate layer to have the same thickness, respectively, an element having substantially the same characteristics was obtained.

【0038】[実施例3]実施例1のn電極30形成工
程において、第1の層をW(0.01μm)/Al
(0.05μm)との積層構造とし、第2の層にPt
(0.1μm)を形成し、第3の層にAu(80%)、
Si(10%)、In(10%)を含む層とする他は実
施例1と同様にしてレーザ素子を作製したところ、実施
例1とほぼ同等の特性を有する素子が得られた。さらに
中間層にPtに代えて、W、Ti、Zr、Mo、Auを
それぞれ同一膜厚で形成したところ、ほぼ同等の特性を
有する素子が得られた。なお第1の層はWとAlとが一
部合金化したような状態となっており、その上に第2の
層であるPt層、その上に第3の層であるAu、Si、
In合金からなる3層構造を有していた。
[Embodiment 3] In the step of forming the n-electrode 30 of the embodiment 1, the first layer is formed of W (0.01 μm) / Al
(0.05 μm), and the second layer is made of Pt.
(0.1 μm), and Au (80%) in the third layer,
A laser device was manufactured in the same manner as in Example 1 except that a layer containing Si (10%) and In (10%) was obtained. As a result, an element having substantially the same characteristics as in Example 1 was obtained. Furthermore, when W, Ti, Zr, Mo, and Au were formed in the intermediate layer in the same film thickness, respectively, an element having substantially the same characteristics was obtained. Note that the first layer is in a state in which W and Al are partially alloyed, and the second layer is a Pt layer, and the third layer is Au, Si,
It had a three-layer structure made of an In alloy.

【0039】[実施例4]実施例1のn電極30形成工
程において、第1の層をTi(0.01μm)/V
(0.01μm)、Au(0.08μm)との積層構造
とし、第2の層にZr(0.1μm)を形成し、第3の
層にAu(80%)、Ge(10%)、Sn(10%)
を含む層とする他は実施例1と同様にしてレーザ素子を
作製したところ、実施例1とほぼ同等の特性を有する素
子が得られた。さらに中間層にZrに代えて、W、T
i、Pt、Moをそれぞれ同一膜厚で形成したところ、
ほぼ同等の特性を有する素子が得られた。なお、第2の
層においてAuを試していないのは第1の層で最後にA
uが積層されていることによる。
[Embodiment 4] In the step of forming the n-electrode 30 of the embodiment 1, the first layer is formed of Ti (0.01 μm) / V
(0.01 μm) and Au (0.08 μm), Zr (0.1 μm) is formed in the second layer, and Au (80%), Ge (10%), and Sn (10%)
When a laser device was manufactured in the same manner as in Example 1 except that the layer was formed, a device having substantially the same characteristics as in Example 1 was obtained. Further, instead of Zr for the intermediate layer, W, T
When i, Pt, and Mo were formed with the same film thickness,
An element having substantially the same characteristics was obtained. The reason why Au was not tried in the second layer is that the Au
This is because u is laminated.

【0040】[実施例5]実施例1のn電極30形成工
程において、第1の層をZr(0.01μm)/Nb
(0.01)/Au(0.04μm)との積層構造と
し、第2の層にMo(0.1μm)を形成し、第3の層
にAu(80%)、Ag(5%)、Sn(15%)を含
む層とする他は実施例1と同様にしてレーザ素子を作製
したところ、実施例1とほぼ同等の特性を有する素子が
得られた。さらに中間層にMoに代えて、W、Ti、P
t、Zrをそれぞれ同一膜厚で形成したところ、オーミ
ック性は実施例1のものに比べてやや劣るが、ほぼ同等
の特性を有する素子が得られた。
[Embodiment 5] In the step of forming the n-electrode 30 of the embodiment 1, the first layer is formed of Zr (0.01 μm) / Nb.
(0.01) / Au (0.04 μm), Mo (0.1 μm) is formed in the second layer, and Au (80%), Ag (5%), When a laser device was manufactured in the same manner as in Example 1 except that the layer containing Sn (15%) was used, an element having substantially the same characteristics as in Example 1 was obtained. Further, instead of Mo, W, Ti, P
When t and Zr were formed to have the same film thickness, an element having substantially the same characteristics was obtained although the ohmic property was slightly inferior to that of Example 1.

【0041】[実施例6]実施例1において、n側コン
タクト層40を形成せずに直接、窒化物半導体基板の裏
面側にn電極30を形成する他は同様にしてレーザ素子
を得たところ、オーミック性は実施例1のものに比べて
やや劣るが、ほぼ同等の特性を有する素子が得られた。
Example 6 A laser device was obtained in the same manner as in Example 1, except that the n-electrode 30 was formed directly on the back surface of the nitride semiconductor substrate without forming the n-side contact layer 40. Although the ohmic property was slightly inferior to that of Example 1, an element having substantially the same characteristics was obtained.

【0042】[0042]

【発明の効果】このように本発明の素子によると、Ga
N基板と良好なオーミック性が得られて、しかも接着力
が良く、劣化しにくい安定したn電極が提供できる。な
お本明細書では最も過酷な条件で使用されるレーザ素子
について説明したが、本発明はレーザ素子だけでなく、
GaN基板を用い、そのGaN基板の裏面にn電極が形
成される全ての窒化物半導体素子に適用可能である。
As described above, according to the device of the present invention, Ga
It is possible to provide a stable n-electrode which has good ohmic properties with an N-substrate, has good adhesive strength, and is hardly deteriorated. In this specification, the laser element used under the most severe conditions has been described, but the present invention is not limited to the laser element,
The present invention is applicable to all nitride semiconductor devices in which a GaN substrate is used and an n-electrode is formed on the back surface of the GaN substrate.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明の一実施例に係るレーザ素子の構造を
示す模式断面図。
FIG. 1 is a schematic sectional view showing the structure of a laser device according to one embodiment of the present invention.

【符号の説明】[Explanation of symbols]

10・・・窒化物半導体基板 (11・・・第1のGaN層) (12・・・中間層) (13・・・第2のGaN層) 14・・・n側クラッド層 15・・・n側光ガイド層 16・・・活性層 17・・・p側光ガイド層 18・・・p側クラッド層 19・・・p側コンタクト層 40・・・n側コンタクト層 20・・・p電極 30・・・n電極 (31・・・第1の層) (32・・・第2の層) (33・・・第3の層) 100・・・絶縁膜 Reference Signs List 10: nitride semiconductor substrate (11: first GaN layer) (12: intermediate layer) (13: second GaN layer) 14: n-side cladding layer 15: n-side light guide layer 16 ... active layer 17 ... p-side light guide layer 18 ... p-side cladding layer 19 ... p-side contact layer 40 ... n-side contact layer 20 ... p-electrode 30 ... n electrode (31 ... first layer) (32 ... second layer) (33 ... third layer) 100 ... insulating film

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 n型窒化物半導体からなる窒化物半導体
基板の第1の主面側に、n型窒化物半導体層及びp型窒
化物半導体層を有する素子構造が形成され、その窒化物
半導体基板の第2の主面側にn電極が形成され、そのn
電極と支持体とが対向して、素子が支持体にダイボンデ
ィングされてなる窒化物半導体素子であって、 前記n電極は、第2の主面に接近した側から、n型窒化
物半導体と良好なオーミック接触が得られる金属を含む
第1の層と、Alよりも高融点金属を含む第2の層と、
Sn若しくはInを含む第3の層とを有する少なくとも
3層構造を具備することを特徴とする窒化物半導体素
子。
An element structure having an n-type nitride semiconductor layer and a p-type nitride semiconductor layer is formed on a first main surface side of a nitride semiconductor substrate made of an n-type nitride semiconductor, and the nitride semiconductor An n-electrode is formed on the second principal surface side of the substrate, and the n-electrode is formed on the n-electrode.
An electrode and a support are opposed to each other, and the device is die-bonded to the support. The n-electrode includes an n-type nitride semiconductor and an n-type nitride semiconductor. A first layer containing a metal that provides a good ohmic contact, a second layer containing a metal having a higher melting point than Al,
A nitride semiconductor device having at least a three-layer structure including a third layer containing Sn or In.
【請求項2】 前記n電極と第2の主面との間に、n型
不純物がドープされた窒化物半導体層が成長されている
ことを特徴とする請求項1に記載の窒化物半導体素子。
2. The nitride semiconductor device according to claim 1, wherein a nitride semiconductor layer doped with an n-type impurity is grown between said n-electrode and a second main surface. .
【請求項3】 前記窒化物半導体層のn型不純物濃度
が、第2の主面近傍の窒化物半導体基板のn型不純物濃
度よりも大きいことを特徴とする請求項2に記載の窒化
物半導体素子。
3. The nitride semiconductor according to claim 2, wherein an n-type impurity concentration of the nitride semiconductor layer is higher than an n-type impurity concentration of the nitride semiconductor substrate near the second main surface. element.
【請求項4】 前記第1の層はW、Al、Ti、Zr、
V、Nbからなる群から選択された少なくとも一種の金
属を含むことを特徴とする請求項1に記載の窒化物半導
体素子。
4. The first layer is made of W, Al, Ti, Zr,
The nitride semiconductor device according to claim 1, wherein the nitride semiconductor device includes at least one metal selected from the group consisting of V and Nb.
【請求項5】 前記第2の層はW、Ti、Zr、Pt、
Mo、Au、Niからなる群から選択された少なくとも
一種の金属を含むことを特徴とする請求項1に記載の窒
化物半導体素子。
5. The second layer is made of W, Ti, Zr, Pt,
The nitride semiconductor device according to claim 1, wherein the nitride semiconductor device includes at least one metal selected from the group consisting of Mo, Au, and Ni.
【請求項6】 前記第3の層はAu、Ge、Si、Ag
からなる群から選択された少なくとも一種の金属と、S
n若しくはInとを含むことを特徴とする請求項1に記
載の窒化物半導体素子。
6. The third layer is made of Au, Ge, Si, Ag.
At least one metal selected from the group consisting of
2. The nitride semiconductor device according to claim 1, comprising n or In.
【請求項7】 前記窒化物半導体基板の第1の主面と、
第2の主面との間に少なくともInを含む窒化物半導体
層が形成されていることを特徴とする請求項1乃至6の
内のいずれか1項に記載の窒化物半導体素子。
7. A first main surface of the nitride semiconductor substrate,
The nitride semiconductor device according to any one of claims 1 to 6, wherein a nitride semiconductor layer containing at least In is formed between the nitride semiconductor layer and the second main surface.
JP14450298A 1998-05-26 1998-05-26 Nitride semiconductor device Expired - Fee Related JP3360812B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14450298A JP3360812B2 (en) 1998-05-26 1998-05-26 Nitride semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14450298A JP3360812B2 (en) 1998-05-26 1998-05-26 Nitride semiconductor device

Publications (2)

Publication Number Publication Date
JPH11340571A true JPH11340571A (en) 1999-12-10
JP3360812B2 JP3360812B2 (en) 2003-01-07

Family

ID=15363861

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14450298A Expired - Fee Related JP3360812B2 (en) 1998-05-26 1998-05-26 Nitride semiconductor device

Country Status (1)

Country Link
JP (1) JP3360812B2 (en)

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004006718A (en) * 2002-03-26 2004-01-08 Sanyo Electric Co Ltd Nitride group semiconductor element and manufacturing method thereof
US6895029B2 (en) 2001-09-27 2005-05-17 Sharp Kabushiki Kaisha Nitride semiconductor laser device
JP2005244148A (en) * 2004-02-27 2005-09-08 Super Nova Optoelectronics Corp Gallium nitride based light emitting diode and its manufacturing method
JP2006128389A (en) * 2004-10-28 2006-05-18 Sharp Corp Nitride semiconductor device and manufacturing method therefor
US7123640B2 (en) 2002-07-17 2006-10-17 Sharp Kabushiki Kaisha Nitride semiconductor laser device chip and laser apparatus including the same
WO2007007634A1 (en) * 2005-07-08 2007-01-18 Nec Corporation Electrode structure, semiconductor device and methods for manufacturing those
US7170101B2 (en) 2001-05-15 2007-01-30 Sharp Kabushiki Kaisha Nitride-based semiconductor light-emitting device and manufacturing method thereof
JP2007251178A (en) * 2006-03-17 2007-09-27 Samsung Electro Mech Co Ltd Nitride semiconductor single crystal substrate, its manufacturing method, and method of manufacturing vertical structure nitride light emitting element using the same
US7327770B2 (en) 2003-04-24 2008-02-05 Sharp Kabushiki Kaisha Nitride semiconductor laser device
US7629623B2 (en) 2002-03-26 2009-12-08 Sanyo Electric Co., Ltd. Nitride-based semiconductor device and method of fabricating the same
US7683398B2 (en) 2007-03-02 2010-03-23 Mitsubishi Electric Corporation Nitride semiconductor device having a silicon-containing connection layer and manufacturing method thereof
JP2010177716A (en) * 2010-05-21 2010-08-12 Sharp Corp Nitride semiconductor laser element, method of manufacturing the same, and optical device using the same
US8030677B2 (en) 2006-07-31 2011-10-04 Panasonic Corporation Semiconductor light emitting element and method for manufacturing same
JP2013058636A (en) * 2011-09-08 2013-03-28 Tamura Seisakusho Co Ltd β-Ga2O3-BASED SUBSTRATE, LED ELEMENT, AND METHOD FOR MANUFACTURING THE SAME
US9006792B2 (en) 2011-09-12 2015-04-14 Mitsubishi Chemical Corporation Light emitting diode element
JP2015199650A (en) * 2014-03-31 2015-11-12 日本碍子株式会社 Method for introducing dopant to group 13 nitride free-standing substrate, group 13 nitride free-standing substrate, led element and method for manufacturing led element
US9437525B2 (en) 2013-04-30 2016-09-06 Toyoda Gosei Co., Ltd. Semiconductor device and manufacturing method thereof

Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7170101B2 (en) 2001-05-15 2007-01-30 Sharp Kabushiki Kaisha Nitride-based semiconductor light-emitting device and manufacturing method thereof
US6895029B2 (en) 2001-09-27 2005-05-17 Sharp Kabushiki Kaisha Nitride semiconductor laser device
JP2004006718A (en) * 2002-03-26 2004-01-08 Sanyo Electric Co Ltd Nitride group semiconductor element and manufacturing method thereof
US7655484B2 (en) 2002-03-26 2010-02-02 Sanyo Electric Co., Ltd. Nitride-based semiconductor device and method of fabricating the same
US7629623B2 (en) 2002-03-26 2009-12-08 Sanyo Electric Co., Ltd. Nitride-based semiconductor device and method of fabricating the same
US7123640B2 (en) 2002-07-17 2006-10-17 Sharp Kabushiki Kaisha Nitride semiconductor laser device chip and laser apparatus including the same
US7327770B2 (en) 2003-04-24 2008-02-05 Sharp Kabushiki Kaisha Nitride semiconductor laser device
JP2005244148A (en) * 2004-02-27 2005-09-08 Super Nova Optoelectronics Corp Gallium nitride based light emitting diode and its manufacturing method
US8203152B2 (en) 2004-10-28 2012-06-19 Sharp Kabushiki Kaisha Nitride semiconductor devices including a separation preventing layer
JP2006128389A (en) * 2004-10-28 2006-05-18 Sharp Corp Nitride semiconductor device and manufacturing method therefor
JP4601391B2 (en) * 2004-10-28 2010-12-22 シャープ株式会社 Nitride semiconductor device and manufacturing method thereof
WO2007007634A1 (en) * 2005-07-08 2007-01-18 Nec Corporation Electrode structure, semiconductor device and methods for manufacturing those
JP5067158B2 (en) * 2005-07-08 2012-11-07 日本電気株式会社 Electrode structure, semiconductor element, and manufacturing method thereof
JP2007251178A (en) * 2006-03-17 2007-09-27 Samsung Electro Mech Co Ltd Nitride semiconductor single crystal substrate, its manufacturing method, and method of manufacturing vertical structure nitride light emitting element using the same
US8334156B2 (en) 2006-03-17 2012-12-18 Samsung Electronics Co., Ltd. Nitride semiconductor single crystal substrate, and methods of fabricating the same and a vertical nitride semiconductor light emitting diode using the same
US7859086B2 (en) 2006-03-17 2010-12-28 Samsung Led Co., Ltd. Nitride semiconductor single crystal substrate, and methods of fabricating the same and a vertical nitride semiconductor light emitting diode using the same
US8222670B2 (en) 2006-07-31 2012-07-17 Panasonic Corporation Semiconductor light emitting element and method for manufacturing same
US8030677B2 (en) 2006-07-31 2011-10-04 Panasonic Corporation Semiconductor light emitting element and method for manufacturing same
US8163576B2 (en) 2007-03-02 2012-04-24 Mitsubishi Electric Corporation Nitride semiconductor device having a silicon-containing layer and manufacturing method thereof
US7683398B2 (en) 2007-03-02 2010-03-23 Mitsubishi Electric Corporation Nitride semiconductor device having a silicon-containing connection layer and manufacturing method thereof
JP2010177716A (en) * 2010-05-21 2010-08-12 Sharp Corp Nitride semiconductor laser element, method of manufacturing the same, and optical device using the same
JP2013058636A (en) * 2011-09-08 2013-03-28 Tamura Seisakusho Co Ltd β-Ga2O3-BASED SUBSTRATE, LED ELEMENT, AND METHOD FOR MANUFACTURING THE SAME
US9006792B2 (en) 2011-09-12 2015-04-14 Mitsubishi Chemical Corporation Light emitting diode element
US9437525B2 (en) 2013-04-30 2016-09-06 Toyoda Gosei Co., Ltd. Semiconductor device and manufacturing method thereof
JP2015199650A (en) * 2014-03-31 2015-11-12 日本碍子株式会社 Method for introducing dopant to group 13 nitride free-standing substrate, group 13 nitride free-standing substrate, led element and method for manufacturing led element

Also Published As

Publication number Publication date
JP3360812B2 (en) 2003-01-07

Similar Documents

Publication Publication Date Title
JP3705047B2 (en) Nitride semiconductor light emitting device
JP3223832B2 (en) Nitride semiconductor device and semiconductor laser diode
JP3360812B2 (en) Nitride semiconductor device
JP3031415B1 (en) Nitride semiconductor laser device
JP3456413B2 (en) Method for growing nitride semiconductor and nitride semiconductor device
JP3292083B2 (en) Method for manufacturing nitride semiconductor substrate and method for manufacturing nitride semiconductor element
JP3087831B2 (en) Nitride semiconductor device
JPH11177175A (en) Nitride semiconductor device
JP4665394B2 (en) Nitride semiconductor laser device
JPH11330610A (en) Nitride semiconductor laser
JP4360071B2 (en) Manufacturing method of nitride semiconductor laser device
JP4043087B2 (en) Nitride semiconductor device manufacturing method and nitride semiconductor device
JPH10145006A (en) Compound semiconductor device
JP2000196201A (en) Nitride semiconductor laser element
JP3859356B2 (en) Method of manufacturing nitride semiconductor device
JP3847000B2 (en) Nitride semiconductor device having nitride semiconductor layer with active layer on nitride semiconductor substrate and method for growing the same
JP3604278B2 (en) Nitride semiconductor laser device
JP2004104088A (en) Nitride semiconductor device
JP3537984B2 (en) Nitride semiconductor laser device
JP3216118B2 (en) Nitride semiconductor device and method of manufacturing the same
JP4100013B2 (en) Nitride semiconductor laser device and manufacturing method thereof
JP2000058972A (en) Nitride semiconductor laser element
JPH10290047A (en) Nitride semiconductor element
JPH11312841A (en) Nitride semiconductor laser element
JP2005101536A (en) Nitride semiconductor laser element

Legal Events

Date Code Title Description
R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081018

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081018

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091018

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091018

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091018

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101018

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101018

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111018

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111018

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121018

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121018

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131018

Year of fee payment: 11

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees