JPH11340221A - Manufacture of semiconductor integrated circuit device and semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form insulating films on the surface of a substrate without giving any damage to the substrate nor raising the peeling problem of the insulating films by forming a first insulating film on the surface of the substrate under such a condition that the peeling of the first insulating film and damage to the substrate are not caused in a first insulating film forming process. SOLUTION: A first insulating film 9a is formed on the main surface of a semiconductor substrate 1 by the high density plasma(HDP) CVD method under such a film forming condition that no damage is given to a gate insulating film 5i and a substrate 1, such as the semiconductor substrate, etc., and the adhesion between the substrate 1 and film 9a can be secured. Then a second insulating film 10a is formed on the first insulating film 9a by the HDP CVD method without setting the condition set to the first insulating film 9a. Therefore, the substrate 1 is not damaged, because the substrate 1 is protected by the first insulating film 9a, and the occurrence of such a problem that the second insulating film 10a is separated from the first insulating film 9a is prevented, because the adhesion between the insulating films 9a and 10a is good.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor integrated circuit device and a semiconductor integrated circuit device technology, and more particularly to a technology effective when applied to a film forming technology using a plasma chemical reaction.

[0002]

2. Description of the Related Art In a manufacturing process of a semiconductor integrated circuit device, various plasma processes using a plasma chemical reaction are performed. For example, plasma CVD (Chemical
The Vapor Deposition process has already been established as a manufacturing technology for semiconductor integrated circuit devices. In the plasma CVD process, a reactive gas is discharged under reduced pressure to generate reactive species such as electrons, ions, and radicals that cannot be stably obtained at normal pressure, and to promote a predetermined chemical reaction to form a film. This is a technology that performs processing. Therefore, a low-temperature process, a dry process, and the like can be realized, which is a very preferable technique for manufacturing a semiconductor integrated circuit device. In addition, for example, it has excellent characteristics such as being excellent in moisture absorption resistance and water permeability resistance, having a small leak current due to stable combination of the constituent elements of the film, and being capable of depositing an insulating film having good film quality. I have.

[0003] A method of generating this plasma includes, for example, a capacitively coupled plasma (CCP).
sma) CVD method and inductively coupled plasma (ICP: In)
Inductive Cuppled Plasma, ECR: Electron Cycrotoro
n Resonance, helicon plasma) CVD method. In the capacitive coupling type, two plate electrodes are arranged in parallel inside a reaction tube at a predetermined distance from each other, and a high frequency is applied to one or both of the electrodes. There is an excellent feature that the uniformity of can be secured. On the other hand, the inductively coupled type generates plasma by applying high frequency (or low frequency) from outside the reaction tube by a coil or the like, and has less internal contamination, and is about 2 times less than the capacitively coupled type.
There is an excellent feature that an order of magnitude higher density plasma (High Density Plasma) can be formed.

In recent years, in a semiconductor integrated circuit device, an advanced embedding technique for embedding an adjacent wiring with an insulating film without forming a void due to miniaturization of a wiring structure constituting the semiconductor integrated circuit device has been developed. Is needed. This is because, for example, the dimension of the wiring in the width direction (horizontal direction) is miniaturized with miniaturization of the wiring, while the dimension of the wiring in the thickness direction (vertical direction) suppresses an increase in current density. , Because it can not be too thin from the viewpoint of ensuring the reliability of wiring,
This is because the aspect ratio (interconnection height / interval between interconnections) tends to increase between adjacent interconnections. Also, for example, in a semiconductor integrated circuit device, a trench-type element isolation structure is being adopted in order to realize flattening and miniaturization, and an insulating film is formed in a trench dug in a semiconductor substrate to constitute the isolation structure. This is because it is necessary to embed without causing voids. One method of embedding such a step is, for example, a bias CVD method. In this method, for example, a plasma CVD process is performed while applying a high frequency (RF) bias to a semiconductor wafer, and a film is formed while performing film formation and sputter etching.

The plasma CVD method and the bias C
Regarding the VD method, for example, Baifukan Co., Ltd., issued on June 10, 1997, "Advanced Electronics I
-17 ULSI process technology "P73-P74 and P
77 to P79.

[0006]

However, the plasma C
The present inventor has found that in the film forming technique by the VD method, there is a problem of peeling off an insulating film formed by a plasma CVD method and a problem of element failure due to damage during film formation.

The improvement of the film quality of the film formed by the plasma CVD method is described in (1). High temperature of the semiconductor substrate during film formation,
(2) Higher output of high frequency power for plasma generation, (3) Higher plasma density, etc., but the upper limit of (1) above has an upper limit due to the influence on the characteristics of semiconductor devices. Therefore, the methods (2) and (3) are effective.

However, in the case of covering the wiring by forming an insulating film such as a silicon oxide film by a plasma CVD method, if the above conditions (2) and (3) are adopted, during the film forming process, As a result of an increase in the amount of oxygen applied to the wiring and oxidation of the wiring surface, there is a problem in that the adhesion of the insulating film formed by the plasma CVD method to the wiring is reduced and the insulating film is separated. .

When the conditions (2) and (3) are adopted when the insulating film is formed by the plasma CVD method, the ion current flowing from the plasma to the semiconductor wafer and the electron current flowing from the semiconductor wafer to the plasma increase. To reduce the breakdown voltage of the gate insulating film and the threshold voltage (Vth)
As a result of device failures such as fluctuations of the semiconductor substrate, physical damage to the semiconductor substrate, or creation of a chemically unstable state on the surface of the semiconductor substrate, the reliability and yield of the semiconductor integrated circuit device are increased. There is a problem that is reduced.

Therefore, an object of the present invention is to provide a plasma CVD method.
It is an object of the present invention to provide a technique capable of depositing an insulating film without damaging a base and causing a problem of peeling of the insulating film in a film forming process by a method.

Another object of the present invention is to provide a plasma CV
It is an object of the present invention to provide a technique capable of depositing a high-quality insulating film without damaging a base and causing a problem of peeling of an insulating film in a film forming process by the D method.

Another object of the present invention is to provide a plasma CV
In the film forming process by the method D, a technique capable of depositing an insulating film without damaging the base, without causing a problem of peeling of the insulating film, and without generating a void in the depression of the base. To provide.

Another object of the present invention is to provide a plasma C
In the film forming process by the VD method, it is possible to form a high-quality insulating film without causing an increase in the film forming time, without damaging the base, and without causing a problem of peeling of the insulating film. It is to provide the technology that can be done.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0015]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, according to the method of manufacturing a semiconductor integrated circuit device of the present invention, a first insulating film is formed on a semiconductor substrate by plasma CVD.
A step of depositing by a D method or a high-density plasma CVD method, and a second step on the semiconductor substrate after the step of depositing the first insulating film.
Plasma CVD or high-density plasma CVD of insulating film
And a step of applying the first insulating film under the condition that the peeling of the first insulating film and the damage to the underlayer do not occur in the step of applying the first insulating film. It is.

Further, the method for manufacturing a semiconductor integrated circuit device according to the present invention comprises the steps of: depositing a first insulating film on a semiconductor substrate by a plasma CVD method or a high-density plasma CVD method;
Depositing a second insulating film on the semiconductor substrate after the step of depositing the first insulating film by a plasma CVD method or a high-density plasma CVD method. The high-frequency power applied between the semiconductor substrate and the plasma is made lower than the high-frequency power applied between the semiconductor substrate and the plasma when the second insulating film is formed.

Further, in the method of manufacturing a semiconductor integrated circuit device according to the present invention, in the step of depositing the second insulating film, high-frequency power is applied to the semiconductor substrate so that both film formation and sputtering are performed. The second insulating film is deposited.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings. (Note that components having the same functions in all drawings for describing the embodiments are denoted by the same reference numerals.) , And the repeated explanation is omitted).

(Embodiment 1) FIGS. 1 to 5 are cross-sectional views of essential parts during a manufacturing process of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIGS. High density plasma C used in integrated circuit device manufacturing process
It is explanatory drawing of a VD apparatus.

In the first embodiment, a case in which an insulating film is deposited by, for example, a high density plasma (HDP) CVD method will be described. This HDP / CVD method is a conventional plasma CVD method.
This is a method in which film formation is performed at a plasma density (electron density) of the order of 10 ¹¹ / cm ^2, which is about two orders of magnitude higher than that of the plasma CVD method. Further, it has a feature that the temperature of ions and neutral particles is low. In the following description, a case where the present invention is applied to, for example, a method of manufacturing a logic circuit will be described.

As shown in FIG. 1, a semiconductor substrate 1 is made of, for example, p ^- type silicon single crystal, and has a n-type
Well 2N and p-well 2P are formed. For example, phosphorus or arsenic is introduced into n-well 2N to be set to n-type, and p-well 2P is set to p-type by introducing, for example, boron. On the main surface of the semiconductor substrate 1, a field insulating film 3 for forming an isolation portion made of, for example, a silicon oxide film is formed. However, the structure of the isolation portion is not limited to this, and can be variously changed. For example, a shallow trench buried isolation structure formed by embedding an isolation insulating film in a shallow isolation trench may be used. And
In the element forming region surrounded by the field insulating film 3,
For example, an n-channel MIS • FET (Metal Insulato)
r Semiconductor Field Effect Transistor:
QN is formed. Note that a p-channel type MIS • FET is also formed in other regions. The nMISQN and the pMIS make CMIS
(Complimentary MIS) circuit is constituted.

The nMISQN includes a pair of semiconductor regions 4nd and 4nd formed in a p-well, a gate insulating film 5i formed on the main surface of the semiconductor substrate 1, and a gate electrode 6ng formed thereon. Have. The pair of semiconductor regions 4nd and 4nd are regions for forming the source / drain regions of the nMISQN, and are formed apart from each other with the channel region interposed therebetween. The gate length is, for example, about 0.25 μm. Each semiconductor region 4nd, 4nd
Is set to n-type by introducing, for example, phosphorus or arsenic. Note that each of the semiconductor regions 4nd and 4nd may be configured to have a low-concentration region and a high-concentration region. This low concentration region is a region mainly for suppressing the hot carrier effect, and is adjacent to the channel region. The high-concentration region is formed at a position planarly separated from the channel region by the plane dimension of the low-concentration region. The low-concentration region and the high-concentration region are both set to n-type, but the impurity concentration that determines the conductivity type in the low-concentration region is set lower than that in the high-concentration region. Further, a structure in which a silicide layer such as tungsten silicide is provided on the semiconductor region 4nd may be employed. This makes it possible to reduce the contact resistance between the semiconductor region 4nd and the wiring. Further, a pocket region may be provided near the bottom corner of the semiconductor region on the channel region side. This pocket region is a region for suppressing punch-through between the source and the drain, and is set to a conductivity type opposite to the conductivity type of the semiconductor regions 4nd and 4nd.

The gate insulating film 5i has a thickness of, for example, 8
It is made of a silicon oxide film of about nm. Note that the gate insulating film 5i may be formed of an oxynitride film (SiON). Thus, the generation of interface states in the gate insulating film 5ni can be suppressed, and the number of electron traps in the gate insulating film 5i can be reduced, so that the hot carrier resistance of the gate insulating film 5i can be improved. Therefore, the reliability of the gate insulating film 5i can be improved. As such an oxynitriding method of the gate insulating film 5i, for example, a method of performing a high-temperature heat treatment in an NH ₃ gas atmosphere or a NO ₂ gas atmosphere when forming the gate insulating film 5i by an oxidation process, a silicon oxide film, or the like After forming a gate insulating film 5i, a method of forming a nitride film on the upper surface thereof, a method of performing an oxidation treatment for forming the gate insulating film 5i after ion-implanting nitrogen into the main surface of the semiconductor substrate 1, or a method of forming a gate electrode After ion-implanting nitrogen into the polysilicon film for formation, heat treatment is performed to introduce nitrogen into the gate insulating film 5.
i and the like.

The gate electrode 6ng is made of, for example, low-resistance polysilicon. However, the structure of the gate electrode 6ng is as follows.
The present invention is not limited to this, and various modifications can be made. For example, a polycide structure in which a silicide layer such as tungsten silicide is provided on low-resistance polysilicon or a barrier metal such as titanium nitride or tungsten nitride on low-resistance polysilicon is used. A polymetal structure in which a metal film such as tungsten is provided via a film may be used. When a polymetal structure is employed, the electrical resistance of the gate electrode 6ng can be significantly reduced. This structure is particularly effective when the gate width of the gate electrode 6ng is long. In addition, the gate electrode 6pg on the left side of FIG. 1 indicates a gate electrode of pMIS. Since the structure of the gate electrode 6pg is the same as that of the gate electrode 6ng, the description is omitted.

On the side and upper surfaces of the gate electrodes 6 ng and 6 pg, a sidewall 7 and a cap insulating film 8 made of, for example, a silicon oxide film, a silicon nitride film or a composite film thereof are formed. Side wall 7
When the cap insulating film 8 is formed of a silicon nitride film, the sidewall 7 and the cap insulating film 8 function as an etching stopper when a connection hole is formed in the interlayer insulating film such that the semiconductor region 4nd or the like is exposed. By doing so, the connection holes can be formed in a self-aligned manner with good alignment, so that the layout area of the element can be miniaturized, the reliability can be improved, and the characteristics can be improved.

First, an insulating film (first insulating film) 9a is formed on the main surface of the semiconductor substrate 1 as shown in FIG.
It is deposited by the DP / CVD method. However, here, the film formation process is performed under such a condition that the base such as the gate insulating film 5i and the semiconductor substrate 1 is not damaged and the adhesion to the base is ensured. Specifically, HDP / CV described later
The film forming process is performed with the high frequency power for substrate bias in the D apparatus set to, for example, 500 W or 0 (zero) W. Thus, the base is not damaged by the deposition of the insulating film 9a, and the insulating film 9a is not peeled off. The temperature of the semiconductor substrate 1 during film formation is, for example, 3
It is about 00 ° C to 350 ° C.

The insulating film 9a is formed to have a substantially uniform thickness so as to conform to the base, and the thickness is, for example, about 20 nm to 160 nm, but is not particularly limited. For example, it is 100 nm. Lower 2
0 nm is a thickness in consideration of ensuring the withstand voltage of the insulating film 9a.
When the insulating film is applied by the method, the insulating film 9a itself is not broken, and the base of the insulating film 9a is not damaged. If the upper limit of 160 nm is made thicker, the insulating film 9a buried between adjacent wirings or in a trench or the like is formed.
The thickness is in consideration of preventing voids (voids) from being formed therein.

The constituent material of the insulating film 9a is, for example, a silicon oxide film. In the HDP / CVD process, for example, a mixed gas of monosilane, one of oxygen or nitrous oxide, and argon is used. However, the gas type is not limited to this and can be variously changed. For example, a mixed gas of disilane and either oxygen or nitrous oxide, TEOS (Tetraethoxysilane), and oxygen, nitrous oxide or ozone can be used. A mixed gas with any of them may be used.

The insulating film 9a is not limited to a silicon oxide film but can be variously modified. For example, a silicon nitride film, a fluorine-containing silicon oxide film, a BPSG (Boro
Phospho Silicate Glass), PSG (Phospho Silica)
te Glass) or a silicon oxynitride film. Insulating film 9
When a is a silicon nitride film, the gas type may be, for example, a mixed gas of monosilane, disilane, TEOS, or silicon tetrafluoride and at least one of ammonia and nitrogen. In the case of the fluorine-containing silicon oxide film, the gas species is, for example, a mixed gas of either silicon tetrafluoride or silicon difluoride and either oxygen or nitrous oxide, silicon tetrafluoride, silicon difluoride or A mixed gas of any of ethane hexafluoride, any of monosilane, disilane or TEOS, and any of oxygen or nitrous oxide may be used.
In the case of BPSG, the gas species is, for example, any of monosilane, disilane or TEOS, and TMOP (trimethylp
A mixed gas of any of hosphate, TMP (trimethylphosphate), phosphine or TEOP (triethylphosphate), any of TMB (trimethylborate) or diborane, and any of oxygen, nitrous oxide or ozone may be used. As a gas type in the case of PSG, for example, a mixed gas of any of monosilane, disilane, or TEOS, any of TMOP, TMP, phosphine, or TEOP, and any of oxygen, nitrous oxide, or ozone may be used. The gas species for the silicon oxynitride film is, for example, monosilane, disilane or TEO.
A mixed gas of any one of S, at least one of ammonia and nitrogen, and one of oxygen, nitrous oxide, and ozone may be used.

Subsequently, an insulating film (second insulating film) 10a is applied on the insulating film 9a by the HDP / CVD method in the processing chamber of the HDP / CVD apparatus having the insulating film 9a applied. However, here, the film forming process is performed by a normal HDP / CVD method without adding the conditions as in the case of the insulating film 9a. Specifically, high-frequency power for substrate bias in an HDP / CVD apparatus to be described later is, for example, 2400
The film formation process is performed while the film formation and the sputter etching are operated in a state set to about W. Etching at this time /
The depot ratio is, for example, about 0.36. The temperature of the semiconductor substrate 1 during film formation is, for example, about 300 ° C. to 400 ° C.
The pressure in the processing chamber at the time of film formation is lower than that at the time of film formation of the insulating film 9a. The material of the insulating film 10a (a modification thereof) and the type of gas at the time of film formation (the modification thereof) are the same as those of the insulating film 9
a, the description is omitted, but the insulating film 10a
The flow rate of each gas at the time of film formation is increased as compared with the case of the insulating film 9a.

In the first embodiment, the insulating film 1
Since the base is protected by the insulating film 9a when forming the film 0a by the HDP / CVD method, the base is not damaged, and the adhesion between the insulating film 9a and the insulating film 10a is good. There is no problem that the insulating film 10a peels off. Therefore, without causing damage to the base and without causing a problem of peeling of the insulating film 10a,
Furthermore, without causing voids (voids) in the depressions of the base, for example, the amount of hydrogen and moisture contained in the insulating film 10a is low, the moisture absorption and the water permeability are excellent, and the insulating film 1
The constituent element 0a is bonded in a stable state, so that an insulating film 10a of good film quality can be deposited, for example, a leak current is unlikely to flow.

FIG. 3 shows a TEG (Test E) after these steps.
lement Group) region. A test gate electrode 6tg is formed on the field insulating film 3 and the gate insulating film 5i. This gate insulating film 5i
And the gate electrode 6tg is formed by the gate insulating film 5i described above.
And the gate electrodes 6 ng and 6 pg are formed at the same time. The gate electrode 6tg is directly covered with the insulating film 9a, and the insulating film 10a is provided thereon.

After the steps of forming the insulating films 9a and 10a, as shown in FIG.
(Chemical Mechanical Polishing) method or the like. Note that the method of flattening the insulating film 10a is not limited to this method.
The surface may be flattened by applying a G (Spin On Glass) film or the like. Subsequently, the semiconductor regions 4n are formed on the insulating films 9a and 10a.
After drilling a connection hole 11 such that d and a part of the gate electrode 6pg are exposed, a metal film such as tungsten or titanium nitride is deposited by a CVD method or the like, and the metal film is further cut by a CMP method to form a connection. Hole 11
The plug 12 is formed therein. After that, for example, tungsten, aluminum, aluminum-silicon-copper alloy, or the like is deposited on the insulating film 10a by a sputtering method or the like, and is patterned by photolithography and dry etching to form the first layer wiring 13. Form.

Next, an insulating film (first insulating film) 9b is formed on the main surface of the semiconductor substrate 1 as shown in FIG.
Apply by D method. In this case, the film formation conditions, materials (variation examples), and thicknesses are the same as those of the insulating film 9a, and a description thereof will be omitted. Accordingly, the underlying layer is not damaged by the deposition of the insulating film 9b, and the surface of the first-layer wiring 13 can be prevented from being oxidized by forming the film under the above-described conditions. Film 9 caused by
No peeling of b occurs.

Subsequently, an insulating film (second insulating film) 10b is applied on the insulating film 9b by the HDP / CVD method in the processing chamber of the HDP / CVD apparatus having the insulating film 9b applied. In this case, the film forming conditions, materials (variation examples), and thickness are the same as those of the insulating film 10a, and thus description thereof is omitted. Also in this case, when the insulating film 10b is formed by the HDP-CVD method, the underlying layer is not damaged (in this case, adjacent to each other) without causing damage to the underlying layer and without causing a problem of peeling of the insulating film 10a. The insulating film 10b having good film quality can be deposited without generating a void between the first-layer wirings 13). Thereafter, the upper surface of the insulating film 10b is shaved by the CMP method or the like to be flattened, or is flattened by, for example, applying an SOG film as described above, and then the semiconductor integrated circuit device is manufactured through a normal wiring forming process. I do.

Next, the HDP · C used in the first embodiment
The VD device will be described with reference to FIGS. Fig. 6 shows a single-wafer ECR (Electron Cyclotron Resonance) plasma CV.
The D device 14 is shown. ECR plasma CVD equipment 1
Reference numeral 4 denotes a plasma chamber 14a for generating high-density oxygen under ECR conditions, a waveguide for introducing a microwave (for example, 2.45 GHz) into the plasma chamber 14a, and a plasma chamber 14a.
a, a reaction chamber 14c for reacting an oxygen plasma transported by a diverging magnetic field from the plasma chamber 14a with a film forming gas, a film forming gas (monosilane, disilane, etc.) in the reaction chamber 14c. ), A supply pipe 14d2 for supplying a gas (such as argon and oxygen) for generating sputter etching into the plasma chamber 14a, and a semiconductor substrate 1 (semiconductor wafer) installed in the reaction chamber 14c. And a mounting table 14e for mounting.

The mounting table 14e is, for example, a semiconductor substrate 1
Has an electrostatic chuck mechanism for fixing the electrostatic chuck. A high frequency power supply 14g for substrate bias is electrically connected to the mounting table 14e via a matching unit 14f.
It is possible to supply high-frequency power to the semiconductor substrate 1 during the film forming process. By supplying this high-frequency power, a DC self-bias voltage is generated between the semiconductor substrate 1 and the plasma, so that ions and the like in the plasma can be attracted toward the semiconductor substrate 1 to perform sputter etching.

In the above description, the high frequency power supplied from the high frequency power supply 14g when forming the insulating films 9a and 9b is lower than the high frequency power supplied from the high frequency power supply 14g when forming the insulating films 10a and 10b. I have. Thereby, at the time of applying the insulating films 9a and 9b, the voltage difference between the semiconductor substrate 1 and the plasma can be reduced, and the amount and energy of oxygen and argon ions attracted to the semiconductor substrate 1 can be reduced. Therefore, damage and oxidation of the base (particularly, oxidation of the wiring surface due to irradiation with oxygen ions) can be reduced. Therefore, the insulating films 9a and 9b can be deposited without damaging the base and without causing the problem of peeling of the insulating films 9a and 9b.

The mounting table 14 is provided below the mounting table 14e.
A cooling chamber 14h for cooling e is provided. Cooling water such as pure water is supplied to the cooling chamber 14h through a supply pipe 14h1. Further, the mounting table 14e is provided with a temperature sensor 14i for detecting the temperature of the semiconductor substrate 1. Reference numeral 14j indicates a supply pipe for supplying helium or the like between the upper surface of the mounting table 14e and the semiconductor substrate 1, and 14k indicates an auxiliary coil.

Next, FIG. 7 shows a single wafer type ICP (Inductive
Coupled Plasma) device 15 is shown. ICP device 1
5 is a high-frequency power source 1 connected to a coil 15b wound around a chamber 15a made of a dielectric material (for example, quartz or alumina).
High-frequency power is supplied from 5c1 through a matching unit 15d1 to generate high-density plasma in the chamber 15a with inductive coupling energy. A high-frequency power supply 15c2 is electrically connected to a mounting table 15e on which the semiconductor substrate 1 is mounted via a matching unit 15d2, and supplies a high-frequency power for substrate bias to the semiconductor substrate 1 during a film forming process. Is possible. By supplying this high-frequency power, a DC self-bias voltage is generated between the semiconductor substrate 1 and the plasma, so that ions and the like in the plasma can be attracted toward the semiconductor substrate 1 to perform sputter etching.

In the above description, the high-frequency power supplied from the high-frequency power supply 15c2 when forming the insulating films 9a and 9b is
When forming the insulating films 10a and 10b, the high-frequency power supply 15c is used.
2 is lower than the high frequency power supplied from However, in addition to this method, the high-frequency power supplied from the high-frequency power supply 15c1 when forming the insulating films 9a and 9b is set lower than the high-frequency power supplied from the high-frequency power supply 15c1 when forming the insulating films 10a and 10b. May be. As a result, the insulating films 9a, 9
b does not cause a problem of peeling, and the insulating film 9a,
9b can be applied. The reference numeral 15f indicates a vacuum exhaust pipe. The above-mentioned gas is supplied into the processing chamber (plasma chamber and reaction chamber) formed by the chamber 15a.

Next, FIG. 8 shows another example of the single wafer type ICP device 15. Components having the same functions as those in FIG. 7 are denoted by the same reference numerals. HDP is connected to the low frequency power supply 15
It is formed with inductive coupling energy by supplying low frequency (for example, 300 to 400 kHz) power from c3.
When the insulating films 10a and 10b are formed, a high frequency (for example, 13.5) is supplied from the high frequency power supply 15c2 to the mounting table 15e.
(6 MHz) power is supplied. As a result, a DC self-bias voltage is generated between the semiconductor substrate 1 and the plasma, and ions and the like in the plasma can be attracted toward the semiconductor substrate 1 to perform sputter etching. The turbo pump 15g is a pump for setting the degree of vacuum in the processing chamber at a high speed. The gate valve 15h is a valve that separates the processing chamber from the turbo pump 15g.

Next, FIG. 9 shows a single-wafer type helicon (Helicon).
3) shows a plasma device 16. The helicon plasma device 16 is an antenna 1 in which high-frequency (for example, 13.56 MHz) power is supplied from a high-frequency power supply 16b1 around a dielectric (for example, quartz or alumina) bell jar 16a.
6c and a double coil 16d1,1 disposed on the outer periphery thereof.
6d2, so that the plasma generated in the bell jar 16a can be diffused into the bucket 16e. The inner diameter of the bucket 16e is a bell jar 16
It is formed to be larger than the inner diameter of a, and a permanent magnet 16f is installed on the outer periphery. Also, bucket 1
A mounting table 16h on which the gas ring 16g and the semiconductor substrate 1 are mounted is provided in 6e. Gas ring 16
g is a film forming gas (eg, monosilane, disilane, etc.)
Can be supplied. The sputter etching gas is supplied through a supply pipe 16i above the bell jar 16a.

A high-frequency power supply 16b2 for substrate bias is electrically connected to the mounting table 16h, so that high-frequency power can be supplied to the semiconductor substrate 1 during the film forming process. By supplying this high-frequency power, a DC self-bias voltage is generated between the semiconductor substrate 1 and the plasma, so that ions and the like in the plasma can be attracted toward the semiconductor substrate 1 to perform sputter etching.

In the above description, the high-frequency power supplied from the high-frequency power supply 16b2 when forming the insulating films 9a and 9b is
When forming the insulating films 10a and 10b, the high-frequency power supply 16b is used.
2 is lower than the high frequency power supplied from Thereby, the insulating films 9a and 9 are not damaged without damaging the base.
b does not cause a problem of peeling, and the insulating film 9a,
9b can be applied.

The mounting table 16h has an electrostatic chuck mechanism for attracting the semiconductor substrate 1 with static electricity. The mounting table 16h can move up and down. When automatically placing one of the plurality of semiconductor substrates in the load lock chamber 16j on the mounting table 16h, the mounting table 16
h falls downward in FIG. The evacuation pipe 16k is mechanically connected to, for example, a turbo molecular pump.

According to the first embodiment, the following effects can be obtained.

(1). Insulating film 10 by HDP / CVD process
Prior to depositing the insulating films 9a and 9b,
Under a condition that does not cause damage to the base or peeling of the insulating film.
The insulating film 1 is deposited by the DP / CVD process.
Since the insulating films 9a and 9b protect the base and function as a film for securing the adhesion with the insulating films 10a and 10b when the 0a and 10b are deposited, the insulating films 10a and 10b having good film quality are provided.
10b is formed on the insulating film 10 without damaging the base.
a, 10b can be applied without causing a problem of peeling, and without generating voids in the depressions of the base.

(2) According to the above (1), the yield and reliability of the semiconductor integrated circuit device can be improved.

(3) By depositing the insulating films 9a, 9b 10a, 10b in the same room of the same device, the insulating film 9a, 9b 10a, 10b can be formed without increasing the manufacturing time of the semiconductor integrated circuit device.
a, 9b, 10a and 10b can be attached.

(Embodiment 2) FIG. 10 is an explanatory view of a manufacturing apparatus used in a manufacturing process of a semiconductor integrated circuit device according to another embodiment of the present invention, and FIG. 11 is a view of a manufacturing apparatus showing a modification of FIG. FIG.

In the second embodiment, the insulating films 9a and 9b shown in FIG.
The insulating films 10a and 10b are formed of the same HD as in the first embodiment.
It is deposited with a P-CVD device. That is, the insulating films 9a, 9
b is formed by a normal plasma CVD method, and the insulating film 10a,
10b is formed by the HDP / CVD method. Plasma density (electron density) in this normal plasma CVD method
Is lower than that of HDP, for example, about 10 ⁹ / cm ² .

Also in the second embodiment, the insulating film 9a,
In step 9b, the film formation process is performed under conditions that do not damage the base and ensure adhesion to the base. In particular,
The film forming process is performed with a high-frequency power supplied to an upper electrode (an electrode on which the semiconductor substrate 1 is not mounted) in a parallel plate type CVD apparatus to be described later set between 200 W and 1200 W. Thus, the bases are not damaged by the deposition of the insulating films 9a and 9b, and the insulating films 9a and 9b are not damaged.
No peeling of b occurs. Although the thicknesses and constituent materials (modifications) of the insulating films 9a and 9b may be the same as those in the first embodiment,
In the second embodiment, as a gas for forming the insulating films 9a and 9b, for example, a mixed gas of TEOS, oxygen, and helium gas as a carrier gas is used. The temperature of the semiconductor substrate 1 at the time of film formation was, for example, about 400 ° C. Note that the film forming conditions and constituent materials of the insulating films 10a and 10b are the same as those in the first embodiment, and a description thereof will be omitted.

Next, a single wafer type / parallel plate type plasma CVD apparatus 17 used in the second embodiment will be described with reference to FIG. In a processing chamber 17a of the plasma CVD apparatus 17, an upper electrode 17b and a lower electrode 17c are provided in parallel with each other. The distance between the main surface of the upper electrode 17b and the main surface of the lower electrode 17c is, for example, about 7.1 mm. The upper electrode 17b is electrically connected to a high-frequency power supply 17d, so that high-frequency (for example, 13.56 Mhz) power is supplied to the upper electrode 17b. In the above description, the high-frequency power supplied from the high-frequency power supply 17d when forming the insulating films 9a and 9b is
The film formation process is performed in a state set between 0 W and 1200 W.

The upper electrode 17b has a function part as a gas dispersion plate for dispersing a processing gas into the processing chamber 17a. That is, a process gas such as TEOS, oxygen, and helium is supplied to the gas chamber in the upper electrode 17b through the supply pipe 17e, and further, the gas dispersion plate portion of the main surface (the lower surface in FIG. 10) of the upper electrode 17b. From the inside of the processing chamber 17a. A thermocouple 17f is provided on the lower electrode 17c so that the temperature of the semiconductor substrate 1 can be measured. Also,
A lamp 17g for heating the semiconductor substrate 1 is provided below the lower electrode 17c. Note that reference numeral 17
h is a pressure gauge for measuring the pressure in the processing chamber 17a.

FIG. 11 is a view showing a modification of the single-wafer type parallel plate type plasma CVD apparatus 17 shown in FIG.
Components having the same functions as those described above are denoted by the same reference numerals. In this plasma CVD apparatus 17, a high-frequency power supply 17d1 is electrically connected to the lower electrode 17c, whereby a high-frequency power for substrate bias is supplied to the semiconductor substrate 1 to perform film formation and sputter etching. Membrane treatment is possible. In this case, when forming the insulating films 9a and 9b, only the high-frequency power from the high-frequency power supply 17d may be reduced, or the high-frequency power from the high-frequency power supply 17d1 may be reduced or set to 0 (zero).

According to the second embodiment, the same effect as that of the first embodiment can be obtained.

(Embodiment 3) FIGS. 12 to 14 are cross-sectional views of essential parts during a manufacturing process of a semiconductor integrated circuit device according to another embodiment of the present invention.

In the third embodiment, a case where the present invention is applied to a method of forming a shallow trench isolation portion in a semiconductor integrated circuit device, for example, will be described.

First, as shown in FIG.
Insulating film 1 made of, for example, a silicon nitride film
8 is formed by a normal thermal CVD method (for example, a normal pressure CVD method or a low pressure CVD method), and a photoresist pattern 19 on which an isolation region is exposed and an element region is covered is formed thereon by photolithography. Formed by technology. Subsequently, using the photoresist pattern 19 as a mask, the insulating film 18 and the semiconductor substrate 1 exposed therefrom are removed by etching to form an isolation groove 20 in the main surface of the semiconductor substrate 1. Thereafter, after removing the photoresist pattern 19, as shown in FIG. 13, insulating films 9a and 10a are sequentially formed on the semiconductor substrate 1 from below by a plasma CVD method in the same manner as in the first and second embodiments. (The insulating film 9a is described in the first embodiment.
Is adopted by the HDP / CVD method, and when the second embodiment is adopted, it is applied by the ordinary plasma CVD method.) Thereafter, the insulating films 10a and 9a on the main surface of the semiconductor substrate 1 are shaved by a CMP method or the like using the lower insulating film 18 as an etching stopper. Subsequently, by removing the remaining insulating film 18, the insulating films 9 a and 10 a are buried only in the separation groove 20 to form the separation part 21, as shown in FIG.

In the third embodiment as well, the same effects as in the first embodiment can be obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the first to third embodiments, and the present invention is not limited thereto. It goes without saying that various changes can be made.

For example, in the first to third embodiments,
The case where the first insulating film is formed by the HDP-CVD method or the plasma CVD method has been described. However, the present invention is not limited to this, and various changes can be made. The first insulating film may be formed by a CVD method or a thermal oxidation method. In the case of these insulating films, damage to the underlayer and peeling of the film do not occur during film formation. Therefore, the film may be formed so as not to cause voids in the underlying depression, and the thickness thereof is the same as that of the first embodiment.

In the first embodiment, the case where the first insulating film and the second insulating film are formed by the HDP / CVD method will be described. In the second embodiment, the first insulating film is formed by the ordinary plasma CVD method. Although the case where the second insulating film is formed by the HDP / CVD method has been described, the present invention is not limited to this, and the first insulating film and the second insulating film are formed by the normal plasma CVD method. Also, if the first insulating film is HD
Formed by the P-CVD method, and the second insulating film is formed by ordinary plasma C
It may be formed by a VD method.

In the second embodiment, the case where the high-frequency power source is electrically connected to the upper electrode has been described. However, the present invention is not limited to this. For example, the high-frequency power source and the low-frequency power source may be connected to the upper electrode. A two-frequency excitation CVD apparatus having a structure connected to a power supply may be used.

In the above description, the case where the invention made by the present inventor is mainly applied to the logic circuit manufacturing technique which is the application field as the background has been described.
However, the present invention is not limited to this. For example, a DRAM (Dyna
mic Random Access Memory), SRAM (Static Rando)
m Access Memory) or flash memory (EEPR)
The present invention can be applied to a semiconductor memory circuit such as OM (Electrically Erasable Programmable ROM) or a memory-logic mixed circuit in which a semiconductor memory circuit and a logic circuit are provided on the same semiconductor substrate. Further, the present invention can be applied to a semiconductor integrated circuit device provided with a bipolar transistor on a semiconductor substrate.

[0068]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, in the process of depositing the second insulating film, the first insulating film functions as a film that protects the base and ensures adhesion to the second insulating film. Therefore, the second insulating film can be deposited without damaging the base and without causing a problem of peeling of the second insulating film.

(2) According to the present invention, the second insulating film is formed of HDP
By applying the CVD method, the second insulating film having good film quality can be applied without damaging the base and without causing the problem of peeling of the second insulating film.

(3) According to the present invention, by depositing the first insulating film and the second insulating film in the same chamber of the same HDP / CVD apparatus, the film is formed in the film forming process by the plasma CVD method. An insulating film with good film quality can be deposited without increasing the processing time, without damaging the base, and without causing a problem of peeling of the insulating film.

(4) According to the present invention, the second insulating film is deposited while applying both high-frequency power to the semiconductor substrate and performing both film formation and sputtering. The second insulating film can be applied without causing voids, damaging the base, or causing a problem of peeling of the second insulating film.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor integrated circuit device according to an embodiment of the present invention during a manufacturing step thereof;

FIG. 2 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 1;

3 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 2;

FIG. 4 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 3;

5 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 4;

FIG. 6 is an explanatory diagram of a high-density plasma CVD apparatus used in a manufacturing process of a semiconductor integrated circuit device.

FIG. 7 is an explanatory diagram of a high-density plasma CVD apparatus used in a manufacturing process of a semiconductor integrated circuit device.

FIG. 8 is an explanatory diagram of a high-density plasma CVD apparatus used in a manufacturing process of a semiconductor integrated circuit device.

FIG. 9 is an explanatory diagram of a high-density plasma CVD apparatus used in a manufacturing process of a semiconductor integrated circuit device.

FIG. 10 is an explanatory diagram of a manufacturing apparatus used in a manufacturing process of a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 11 is an explanatory diagram of a manufacturing apparatus showing a modification of FIG. 10;

FIG. 12 is a fragmentary cross-sectional view of a semiconductor integrated circuit device according to another embodiment of the present invention during a manufacturing step thereof;

13 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 12;

14 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 13;

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2N n well 2P p well 3 field insulating film 4nd semiconductor region 5i gate insulating film 6ng gate electrode 6pg gate electrode 7 sidewall 8 cap insulating film 9a, 9b insulating film (first insulating film) 10a, 10b insulating film ( 11 second connection film 12 plug 13 first layer wiring 14 ECR plasma CVD apparatus 14a plasma chamber 14b magnetic coil 14c reaction chamber 14d1, 14d2 supply pipe 14e mounting table 14f matching unit 14g high frequency power supply 14h cooling chamber 14h1 supply pipe 14i Temperature sensor 14j Supply pipe 14k Auxiliary coil 15 ICP device 15a Chamber 15b Coil 15c1 High frequency power supply 15c2 High frequency power supply 15c3 Low frequency power supply 15d1 Matching device 15e Mounting table 15f Vacuum exhaust pipe 15g Turbo pump 15h Gate valve Reference Signs List 6 helicon plasma device 16a bell jar 16b1 high frequency power supply 16b2 high frequency power supply 16c antenna 16d1, 16d2 coil 16e bucket 16f permanent magnet 16g gas ring 16h mounting table 16i supply pipe 16j load lock chamber 16k vacuum exhaust pipe 17 parallel plate type plasma CVD apparatus 17a Chamber 17b Upper electrode 17c Lower electrode 17d High-frequency power supply 17d1 High-frequency power supply 17e Supply tube 17f Thermocouple 17g Lamp 17h Pressure gauge 18 Insulating film 19 Photoresist pattern 20 Separation groove 21 Separation section QN n-channel MIS / FET

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Katsuhiko Hotta 5-22-1, Josuihonmachi, Kodaira-shi, Tokyo Inside Hitachi Cho-SII Systems Co., Ltd.

Claims (7)

[Claims] A first insulating film is formed on a semiconductor substrate by plasma C.
A step of depositing by a VD method or a high-density plasma CVD method, and a step of depositing a second insulating film on the semiconductor substrate after the step of depositing the first insulating film by a plasma CVD method or a high-density plasma CVD method.
And a step of depositing the first insulating film by a method D. In the step of depositing the first insulating film, the first insulating film is deposited under conditions such that peeling of the first insulating film and damage to the base do not occur. A method for manufacturing a semiconductor integrated circuit device. 2. A method according to claim 1, wherein a first insulating film is formed on the semiconductor substrate by plasma C.
A step of depositing by a VD method or a high-density plasma CVD method, and a step of depositing a second insulating film on the semiconductor substrate after the step of depositing the first insulating film by a plasma CVD method or a high-density plasma CVD method.
Applying a high frequency power applied between the semiconductor substrate and the plasma during the process of forming the first insulating film, and applying the high frequency power to the semiconductor substrate during the formation of the second insulating film. A method for producing a semiconductor integrated circuit device, the method comprising lowering the high-frequency power to be applied between the two. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the first insulating film is formed so that no void is formed in the depression of the base and the first insulating film conforms to the base. A method for manufacturing a semiconductor integrated circuit device. 4. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein in the step of depositing the second insulating film, high-frequency power is applied to the semiconductor substrate to form a film and perform sputtering. A method of manufacturing a semiconductor integrated circuit device, wherein the second insulating film is applied while both of them are operated. 5. A step of depositing a first insulating film on a semiconductor substrate by thermal CVD or thermal oxidation, and a step of depositing a second insulating film on the semiconductor substrate after the step of depositing the first insulating film by plasma C.
Applying a VD method or a high-density plasma CVD method, wherein the first insulating film is formed so that no void is formed in the depression of the base and the first insulating film conforms to the base. Of manufacturing a semiconductor integrated circuit device. 6. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said first insulating film has a thickness of 20 nm to 160 nm. Manufacturing method. 7. A semiconductor device comprising: a first insulating film on a semiconductor substrate; and a second insulating film formed on the first insulating film, wherein the first insulating film is formed such that no void is formed in a depression of the base. The second insulating film is formed by applying a high-frequency power between the semiconductor substrate and plasma during the film formation by the high-density plasma CVD method so that both the film formation and the sputtering are performed. A semiconductor integrated circuit device characterized by being formed.