JPH08316313A - Formation of contact hole - Google Patents

Abstract

PURPOSE: To prevent the shortcircuit between a wiring formed inside a contact hole and a conductive pattern formed outside the contact hole and secure the breakdown strength therebetween. CONSTITUTION: In a first step, a gate electrode 13 for a conductive pattern is formed on a silicon substrate 11 and a side wall 16 which has an etch selectivity and insulation property against an interlayer insulating film 18 is formed on the side wall of the electrode 13. In a second step, an insulative protection film 17 having an etch selectivity against the film 18 is formed in such a condition that it covers the electrode 13 and side wall 16. Further, in a third step, the film 18 is formed on the film 17 and, after a contact hole 20 is made in the film 18 between the electrodes 13 in a fourth step, the film 17 on the bottom of the hole 20 is removed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a contact hole for connecting a substrate and wiring in a semiconductor device or between wirings of multiple layers.

[0002]

2. Description of the Related Art With the miniaturization of semiconductor devices, a self-aligned contact technique that makes it unnecessary to consider a design margin for alignment on a mask becomes important in a contact hole process. In addition, when the wiring is made multi-layered, it is necessary to flatten the interlayer insulating film in order to prevent disconnection of the wiring and to prevent etching residue in the step portion of the wiring material. Further, if the step is large, a so-called focus margin in the lithography process cannot be sufficiently obtained, and from this point as well, it is necessary to flatten the interlayer insulating film.

When both the techniques of planarizing the interlayer insulating film and self-aligning contact are applied to the memory cell portion, for example, as shown in FIG. 5, a gate formed on a silicon substrate 111 via a gate insulating film 112. An offset oxide film 114 is provided on the electrode 113, and a stopper insulating film 115 serving as an etching stopper at the time of etching for forming a contact hole is provided. Further, LDD sidewalls 116 made of an oxide film are formed on each side wall of the gate electrode 113 and the offset oxide film 114. The interlayer insulating film 117 has a flattened structure. In such a structure, in order to form the contact hole 118, the stopper insulating film 115 is etched in the first-stage etching. Then, in the second-stage etching, the etching is performed under the condition that the oxide film of the interlayer insulating film 117 and the insulating film 115 have substantially the same etching rate. In the second stage, it is desirable to perform etching under the condition that the etching rate of the silicon nitride film formed by low pressure CVD, which is the stopper insulating film 115, is higher than that of the oxide film.

[0004]

However, in the etching for forming the contact hole, there is no etching condition at the present time which achieves the above condition while ensuring the selection ratio with respect to the underlying silicon substrate.

Therefore, when the device is further miniaturized and the distance between the gate electrodes becomes narrower, the portion where the contact hole 118 is to be formed is filled with the stopper insulating film 115, as shown in FIG. At the time of the second etching in the step of opening the contact hole 118, as shown in (2) of FIG.
4 is etched to expose the gate electrode 113, and a short circuit with a wiring (not shown) formed in the contact hole 118 occurs.

Further, as shown in FIG. 7, when the film thickness of the stopper insulating film 115 made of a silicon nitride film is thinned, the inside of the contact hole 118 is not filled with the stopper insulating film 115, but the LDD sidewall having a low selection ratio is formed. 1
The shoulder portion of 16 is etched to form the gate electrode 113.
It becomes impossible to secure the breakdown voltage between the wiring and the wiring (not shown) formed in the contact hole 118.

It is an object of the present invention to provide a method of forming a contact hole which can secure a breakdown voltage between wirings inside and outside the contact hole without causing a short circuit in the contact hole.

[0008]

SUMMARY OF THE INVENTION The present invention is a method for forming a contact hole, which has been made to achieve the above object. That is, after forming an insulating film in a state of covering a plurality of conductive patterns formed on a substrate and having an offset insulating film provided on the upper portion, a contact hole is formed in the insulating film between the conductive patterns. In the method, in the first step, after forming a conductive pattern on the substrate, a sidewall having etching resistance and insulating property against etching of the insulating film is formed on the sidewall of the conductive pattern. Next, in a second step, an insulating protective film having etching resistance against etching of the insulating film is formed so as to cover the conductive pattern and the sidewall. Then, in a third step, an insulating film is formed on the insulating protective film. Then, in a fourth step, after forming a contact hole in the insulating film between the conductive patterns, the insulating protective film at the bottom of the contact hole is removed.

Further, in the first step, each conductive pattern is formed in a state in which an offset insulating film having etching resistance and insulating property against the etching of the insulating film is provided on the upper surface. Next, in a second step, sidewalls having etching resistance and insulating properties against etching of the insulating film are formed on the sidewalls of each conductive pattern and each offset insulating film. Subsequently, in a third step, the insulating film is formed so as to cover the offset insulating film and the sidewall. Then, in a fourth step, contact holes are formed in the insulating film between the conductive patterns.

[0010]

In the method of forming the contact hole, the sidewall and the insulating protective film are formed by using a material having etching resistance against etching of the insulating film.
The sidewalls are hardly etched by the etching for forming the contact holes. Further, the offset insulating film is protected by the insulating protective film. Furthermore, since the insulating protective film on the gate electrode and the substrate has a higher selection ratio at the time of etching when forming the contact hole than the insulating protective film on the sidewall portion, the film thickness of the insulating protective film Can be formed thin. Therefore, even if the space between the conductive patterns is narrowed, the space between the conductive patterns is not filled with the insulating protective film.

Further, in the method of forming the offset insulating film and the sidewall having etching resistance and insulating property against the etching of the insulating film, in the etching at the time of forming the contact hole, the offset insulating film and the sidewall are formed. Hardly etched. Therefore, even if the space between the conductive patterns is narrowed, the space between the conductive patterns is not filled with the insulating protective film.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to the forming process chart of FIG. In the figure, as an example of a method of forming a contact hole in an insulating film between conductive patterns, LDD (Ligh
A case where a contact hole is formed in an interlayer insulating film between gate electrodes of a MOS (metal-oxide film-semiconductor) type transistor having a tly doped drain structure is shown.

As shown in FIG. 1A, a silicon substrate 11 is used as the substrate. First, in the first step, the gate insulating film 12 made of a silicon oxide film is formed on the silicon substrate 11.
The gate electrode 13 and the offset insulating film 14 made of a silicon oxide film are formed by a usual manufacturing method. Then
A silicon nitride film 15 having an etching resistance and an insulating property against the etching of silicon oxide is formed to a thickness of, for example, 100 nm by a low pressure chemical vapor deposition (hereinafter referred to as LPCVD) method so as to cover the entire surface on the gate electrode 13 side. ~
A film having a thickness of 170 nm is formed. The film forming conditions, as an example, the flow rate is 50sccm for the reaction gas (hereinafter, represents the flow rate represented by cm ³ / min at a flow rate in the standard state sccm) dichlorosilane (SiH ₂ Cl ₂₎ and flow rate of 2
Ammonia (NH ₃ ) of 00 sccm and flow rate of 2000
Using sccm of nitrogen (N ₂ ), the pressure of the reaction atmosphere is set to 70 Pa and the substrate temperature is set to 760 ° C.

Next, as shown in FIG. 1B, the silicon nitride film (15) is etched back to form sidewalls 16 on the side walls of the gate electrode 13 and the offset insulating film 14. As the dry etching conditions at this time, for example, a single-wafer type magnetron reactive ion etching apparatus is used, and the flow rate of the etching gas is 23 sccm.
Flow rate of 78 scc with trifluoromethane (CHF ₃ )
m carbon monoxide is used. The pressure of the etching atmosphere is set to 2.7 Pa, the RF power is set to 1.4 kW, and the temperature of the susceptor of the etching apparatus is set to 20 ° C.

Subsequently, as shown in FIG. 1C, the second step is performed. In this step, the insulating protective film 17 serving as an etching stopper during etching for forming a contact hole is formed on the gate electrode 13 by, for example, LPCVD.
It is formed on the entire side surface. The insulating protective film 17 is made of a silicon nitride film and is formed to have a thickness of 20 nm to 30 nm, for example. The film forming conditions for the silicon nitride film are almost the same as the film forming conditions for the silicon nitride film (15) except for the film forming time.

Next, the third step is performed. In this process, C
The interlayer insulating film 18 is formed of a silicon oxide film on the insulating protective film 17 by the VD method. As the CVD conditions at this time, for example, a parallel plate single-wafer plasma CVD apparatus is used, and tetraethoxysilane (TEOS) with a flow rate of 800 sccm and oxygen (O ₂ ) with 600 sccm are used as film forming gases. In addition, the pressure of the film forming atmosphere is 1.13 k.
Pa, substrate temperature is 400 ° C., and RF power is 700 W.

Next, the fourth step shown in FIG. 1 (4) is performed.
In this step, a resist pattern 19 serving as an etching mask for opening a contact hole is formed on the interlayer insulating film 18 by a lithography technique (for example, resist coating, exposure, development, baking, etc.). Then, using the resist pattern 19 as an etching mask, the interlayer insulating film 18 is etched to form a contact hole 20.
To form. In the etching at this time, the insulating protective film 17 and the sidewall 16 made of a silicon nitride film are formed.
The condition that the etching selection ratio is high is used. The etching conditions, for example, using a single-wafer type magnetron reactive ion etching device, the etching gas,
Octafluorocyclobutane (C _{4 with a} flow rate of 8 sccm)
F ₈ ), carbon monoxide (CO) with a flow rate of 60 sccm, and argon (Ar) with a flow rate of 200 sccm are used. The pressure of the etching atmosphere is set to 5.3 Pa, the RF power is set to 1.6 kW, and the susceptor temperature of the etching apparatus is set to 20 ° C.

After that, the insulating protective film 17 on the bottom of the contact hole 20 is etched to form the underlying silicon substrate 1.
Expose 1 As the etching conditions, for example, a single-wafer type magnetron reactive ion etching device is used, and trifluoromethane (CHF ₃ ) with a flow rate of 40 sccm and oxygen (O ₂ ) with a flow rate of 10 sccm are used as etching gas. The pressure of the etching atmosphere is set to 2.7 Pa, the RF power is set to 1.0 kW, and the susceptor temperature of the etching apparatus is set to 20 ° C.

Although not shown, the resist pattern 19 is then removed by ashing and a cleaning process using sulfuric acid / hydrogen peroxide mixture.

In the first embodiment of the method of forming a contact hole, the sidewall 16 and the insulating protective film 17 are formed using a silicon nitride film having etching resistance against the etching of the interlayer insulating film 18. Therefore, the sidewalls 16 are hardly etched during the etching for forming the contact holes 20. In addition, the offset insulating film 14 is protected by the insulating protective film 17 during etching. Furthermore, since the insulating protective film 17 on the gate electrode 13 and the surface of the silicon substrate 11 has a higher selection ratio at the time of etching when forming the contact hole 20, as compared with the insulating protective film 17 on the sidewall 16, The insulating protective film 17 can be formed thin. Therefore, even if the gap between the gate electrodes 13 becomes narrower, the insulating protective film 17 is provided between the gate electrodes 13.
Will not be embedded by.

Next, a method of forming a stress relaxation film for relaxing the stress from the silicon nitride film around the gate electrode or a part thereof in the first embodiment will be described with reference to FIG.

As shown in FIG. 2A, at least in the first step, after the gate electrode 13 and the offset insulating film 14 are patterned and before the silicon nitride film (15) is formed, The stress relaxation film 31 is formed on the sidewalls of the electrode 13 and the offset insulating film 14. For example, the silicon oxide film 31 is formed by the CVD method so as to cover the gate electrode 13 and the offset insulating film 14.

After that, as shown in FIG. 2B, the silicon oxide film (31) is etched back and the stress relaxation film 3 is formed on the side walls of the gate electrode 13 and the offset insulating film 14.
2 may be formed. After that, the steps after the formation of the silicon nitride film (15) may be performed in the same manner as described in the first embodiment. In this case, the stress of the side wall (16) formed of the silicon nitride film is relaxed.

Alternatively, the steps subsequent to the formation of the silicon nitride film (15) may be performed without etching back the silicon oxide film in the above step. In this case, as shown in (3) of FIG. 2, it is necessary to remove the silicon oxide film 32 (the portion indicated by the chain double-dashed line) at the bottom of the contact hole 20 during the etching for opening the contact hole 20. . In this case, the stress of the sidewall 16 is relaxed. At the same time, since the silicon nitride film is not in contact with the silicon substrate 11, the transistor characteristics can be improved.

Next, a second embodiment will be described with reference to the process chart of FIG. In the figure, as an example, LDD (Lightly Do
A case where a contact hole is formed between the gate electrodes of a MOS (metal-oxide film-semiconductor) type transistor having a ped drain structure is shown.

As shown in FIG. 3A, in the first step,
The gate insulating film 12 and the gate electrode forming film 41 are formed on the silicon substrate 11 by an ordinary manufacturing method. Then LP
A CVD method is used to form a silicon nitride film 42 on the gate electrode forming film 41, which serves as a protective film having etching resistance and insulating properties against etching of an interlayer insulating film formed later. The film forming conditions are the same as those of the silicon nitride film (15) formed in the first embodiment.

The etching mask 43 is formed by a lithographic technique (for example, resist coating, exposure, development, baking, etc.). Then, the etching mask 4
3 is used to etch the silicon nitride film 42.
As the etching conditions for the silicon nitride film 42, for example, a single-wafer type magnetron reactive ion etching apparatus is used, the etching gas is octafluorocyclobutane (C ₄ F ₈ ) with a flow rate of ₈ sccm, and the flow rate is 4 sccm.
Oxygen (O ₂ ) and argon (A ₂ ) with a flow rate of 100 sccm
r) and are used. Also, the pressure of the etching atmosphere is 2.7.
Pa, RF power is set to 800 W, and the susceptor temperature of the etching apparatus is set to -30 ° C.

Next, the gate electrode forming film 41 is etched. The gate electrode forming film 41 is polycide composed of, for example, a tungsten silicide (WSix) film and a polycrystalline silicon film. The etching conditions are, for example, electron cyclotron resonance [ECR (El
ectron Cycrotron Resonance)] using an etching apparatus, the etching gas is trichlorotrifluoroethane (C ₂ Cl ₃ F ₃ ) with a flow rate of 60 sccm, and the flow rate is 10
Sccm sulfur hexafluoride (SF ₆ ) is used. The pressure of the etching atmosphere is set to 1.3 Pa, the microwave power is set to 850 W, and the RF power is set to 150 W.

After that, the etching mask 43 is removed by ashing and a cleaning process using sulfuric acid / hydrogen peroxide mixture. As a result, as shown in (2) of FIG. 3, the gate electrode 13 is formed on the silicon substrate 11 with the gate electrode forming film (41) via the gate insulating film 12, and the silicon nitride film (4) is formed.
The offset insulating film 14 is formed in 2).

Next, the second step is performed. In this process, L
By the PCVD method, a silicon nitride film 15 having etching resistance and insulating properties against etching of an interlayer insulating film to be formed later is formed in a state of covering the entire surface on the gate electrode 13 side. The film forming conditions are the same as those described in the first embodiment.

Next, as shown in FIG. 3C, the silicon nitride film (15) is etched back to form sidewalls 16 on the side walls of the gate electrode 13 and the offset insulating film 14. The dry etching conditions at this time are
This is similar to that described in the first embodiment.

Next, as shown in FIG. 3D, the third step is performed. In this step, a silicon oxide film to be the interlayer insulating film 18 is formed on the entire surface on the side of the offset insulating film 14 by the CVD method. The CVD conditions at this time are as follows:
This is similar to that described in the embodiment.

Next, the fourth step is performed. In this process, lithography technology (for example, resist coating, exposure, development,
A resist pattern 19 serving as an etching mask for opening a contact hole is formed on the interlayer insulating film 18 by baking or the like). Then, using the resist pattern 19 as an etching mask, the interlayer insulating film 18 is etched to form a contact hole 20. In the etching at this time, a condition that the etching selection ratio is high with respect to the offset insulating film 14 made of the silicon nitride film and the sidewall 16 is used. The etching conditions are the same as those described in the first embodiment.

Although not shown, the resist pattern 19 is then removed by ashing and a cleaning process using sulfuric acid / hydrogen peroxide mixture.

In the second embodiment, the contact hole 20 is formed because the offset insulating film 14 and the side wall 16 which have etching resistance and insulating properties against the etching of the interlayer insulating film 18 are formed. By the etching, the offset insulating film 14 and the sidewalls 16 are hardly etched. Further, since the conventional insulating protective film is not used, even if the distance between the gate electrodes 13 is narrowed, the space between the gate electrodes 13 is not filled with the insulating protective film.

Next, a method of forming a stress relaxation film for relaxing the stress from the silicon nitride film in a part of or around the gate electrode in the first embodiment will be described with reference to FIG.

As shown in FIG. 4A, in the first step of the second embodiment, the CVD method is performed after the gate electrode forming film 41 is formed and before the silicon nitride film (42) is formed. Thus, the silicon oxide film 51 is formed.

In the subsequent etching, as shown in FIG. 4B, the stress relaxation film 5 is formed by leaving the silicon oxide film (51) between the gate electrode 13 and the offset insulating film 14.
Form 2

Further, as shown in (3) of FIG. 4, after forming the offset insulating film 14, the silicon nitride film (15) is formed.
Before forming the film, the gate electrode 13, the stress relaxation film 52 and the offset insulating film 1 are formed by, for example, a CVD method.
A silicon oxide film 53 is formed so as to cover the film 4. Thereafter, as shown in FIG. 2D, the silicon oxide film (53) may be etched back to form the stress relaxation film 54 on the side wall of the gate electrode 13. By doing so, the gate electrode 13 is covered by the stress relaxation film 52 and the stress relaxation film 54. After that, the steps after the formation of the silicon nitride film (15) may be performed in the same manner as described in the first embodiment.

[0040]

As described above, according to the present invention,
Since the sidewall and the insulating protective film are formed using a material having etching resistance against etching of the insulating film, the sidewall and the offset insulating film are hardly etched when the contact hole is formed. In addition, in the method of forming the offset insulating film and the sidewall having etching resistance and insulating properties against the etching of the insulating film, the offset insulating film and the sidewall are hardly etched when the contact hole is formed. . Therefore, it is possible to prevent a short circuit between the wiring formed in the contact hole and the conductive pattern, and to secure the breakdown voltage between the wiring and the conductive pattern.

[Brief description of drawings]

FIG. 1 is a process drawing of a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of a method for forming a stress relaxation film.

FIG. 3 is a process drawing of a second embodiment of the present invention.

FIG. 4 is an explanatory diagram of a method for forming a stress relaxation film.

FIG. 5 is an explanatory diagram of a conventional technique.

FIG. 6 is an explanatory diagram of a problem.

FIG. 7 is an explanatory diagram of a problem.

[Explanation of symbols]

 11 Silicon Substrate 13 Gate Electrode 14 Offset Insulating Film 16 Sidewall 17 Insulating Protective Film 18 Interlayer Insulating Film 20 Contact Hole

Claims (6)

[Claims] 1. A contact hole is formed in an insulating film between the conductive patterns after forming the insulating film on the substrate so as to cover a plurality of conductive patterns having an offset insulating film formed thereon. A method of forming a contact hole, wherein after forming the conductive pattern on the substrate, a sidewall having etching resistance and insulating property against etching of the insulating film is formed on a sidewall of the conductive pattern. A first step; a second step of forming an insulating protective film having etching resistance against etching of the insulating film in a state of covering the conductive pattern and the sidewall; and an insulating film on the insulating protective film. And forming a contact hole in the insulating film between the conductive patterns, and then forming the insulating protective film on the bottom of the contact hole. The fourth step and the method for forming a contact hole, comprising the removal. 2. The method for forming a contact hole according to claim 1, wherein in the first step, after forming the conductive pattern and before forming the sidewall, a stress relaxation film is formed on at least a sidewall of the conductive pattern. Forming a contact hole. 3. The method of forming a contact hole according to claim 2, wherein the stress relaxation film is formed in a state of covering the conductive pattern. 4. A method of forming a contact hole, wherein a contact hole is formed in an insulating film formed in a state of covering a plurality of conductive patterns formed on a substrate, the contact hole being formed between the conductive patterns. A first step of forming each of the conductive patterns in a state in which an offset insulating film having etching resistance against the film etching and having an insulating property is provided on the upper surface; and each sidewall of each of the conductive patterns and each of the offset insulating films A second step of forming a sidewall having etching resistance and insulation against the etching of the insulating film, and a third step of forming the insulating film so as to cover the offset insulating film and the sidewall And a fourth step of forming a contact hole in the insulating film between the conductive patterns. The method of forming the Le. 5. The method of forming a contact hole according to claim 4, wherein in the first step, a stress relaxation film is formed between the conductive pattern and the offset insulating film. Method. 6. The method of forming a contact hole according to claim 5, wherein in the first step, a stress relaxation film is formed on at least a sidewall of the conductive pattern.