JPH11339468A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory having novel refresh input specifications, thereby lessening a burden on a logic circuit for controlling accessing by the memory. SOLUTION: A part from a pulse train of refresh requirement signals (RRQ) requiring a refresh operation for each row of a memory, a self refresh mode (SRMOD) signal is fed to a refresh control circuit. When the SRMOD signal shifts from 'L' to 'H', an oscillation circuit 10 immediately starts the generation of a clock pulse train. A set pulse is generated in response to the clock pulse train, which sets a flip flop circuit 30. As a result, a front edge of the pulse of a periodic refresh requirement (PRRQ) signal is generated. Every time the PRRQ signal becomes an 'H' level, a reset pulse is generated, which resets the flip flop circuit 30, and a rear edge of the pulse of the PRRQ signal is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory having a memory cell array requiring a refresh operation, and more particularly to an improvement in a refresh control circuit.

[0002]

2. Description of the Related Art As is well known, a refresh operation is indispensable in a dynamic random access memory (DRAM) in which memory cells are formed by capacitors. Conventional DRAM refresh control circuits use a row address strobe (RAS) signal and a column address strobe (CAS) signal. More specifically, the RAS only refresh method, CBR (C
AS before RAS) refresh method.

In a power down mode in which a DRAM is backed up by a battery, a self refresh operation is preferable. A built-in timer of the DRAM automatically generates a refresh request signal at a fixed cycle, and a built-in counter automatically generates a refresh address. RAS signal and CAS in CBR refresh
Both signals remain active ("L" level).
The CBR self-refresh is entered into the self-refresh mode by keeping it for 0 μs or longer, and the current standard specification is used.

[0004]

A conventional semiconductor memory has a configuration in which a refresh operation is performed based on a RAS signal and a CAS signal received from a logic circuit for controlling access to the semiconductor memory. Therefore, the logic circuit determines the first signal to be given as the CAS signal.
It is necessary to perform complicated control such as controlling the generation timing of each of the leading edge of the pulse, the leading edge of the second pulse to be given as the RAS signal, and the trailing edge of the second pulse.

[0005] A main object of the present invention is to provide a semiconductor memory having a new refresh input specification, thereby reducing the load on a logic circuit for controlling access to the semiconductor memory.

Another object of the present invention is to enable the first refresh operation in the self-refresh mode to be started earlier.

Another object of the present invention is to prevent reset errors of individual refresh request signals in a self-refresh mode.

[0008]

In order to achieve the above main object, the present invention provides a first terminal for receiving an individual pulse of a refresh request signal, and a self terminal independent of the first terminal. A refresh input specification of a semiconductor memory having a second terminal for receiving a refresh mode signal is adopted. The refresh control circuit in the semiconductor memory controls the refresh operation of one row of the memory cell array every time one pulse of the refresh request signal is applied to the first terminal. The refresh control circuit controls a refresh operation of a plurality of rows of the memory cell array in response to a transition from a first logic level to a second logic level of a self-refresh mode signal applied to a second terminal. I do. A semiconductor memory according to the present invention is provided on a single semiconductor chip together with a logic circuit for supplying a respective pulse of a refresh request signal to a first terminal and a self-refresh mode signal to a second terminal. It may be a memory.

The refresh control circuit includes an address counter for holding a row address designating one row to be refreshed in the memory cell array, and an address counter from a plurality of word lines of the memory cell array. And a row decoder for selecting one word line according to the row address held in the row. According to the present invention, the row address held in the address counter is updated in response to the end of the refresh operation for the one row and after the time required to deselect the selected word line has elapsed. Is done. This is because the next row address is quickly determined before the start of the refresh operation of the next row while avoiding multiple selection of word lines.

The refresh control circuit includes a flip-flop circuit for setting and resetting a timing signal for controlling a refresh operation of one row of the memory cell array in response to a set pulse and a reset pulse, respectively, and a self-refresh mode. An oscillation circuit for generating a clock pulse train while the signal holds the second logic level, and a set pulse to be applied to the flip-flop circuit based on the clock pulse train generated by the oscillation circuit. And a reset pulse generating circuit for generating a reset pulse to be applied to the flip-flop circuit based on the timing signal set by the flip-flop circuit.

According to the present invention, the oscillation circuit changes the self-refresh mode signal from the first logic level to the second logic level so that the first refresh operation in the self-refresh mode can be started earlier. Means for generating the leading edge of the first clock pulse in the clock pulse train at the point of transition to. Specifically, the oscillation circuit includes an even number of cascaded inverters, a capacitor having a first terminal coupled to the output of the last one of the even number of inverters, and a self-refresh mode. While the signal holds the first logic level, a constant logic level is output, and while the self-refresh mode signal holds the second logic level, the output of the last-stage inverter is inverted. A logic gate for outputting a signal, a first resistor for coupling the output of the logic gate to a second terminal of the capacitor, and a second terminal of the capacitor connected to a first stage of the even number of inverters. A second resistor for coupling to the input of the inverter, and the same logic level as the constant level only while the self-refresh mode signal holds the first logic level. And a transistor for providing a logic level to the input of said first stage inverter. According to such a configuration, when the self-refresh mode signal transitions from the first logic level to the second logic level, the operation of the oscillation circuit always starts from an initial state in which the voltage between both terminals of the capacitor is zero. Is convenient.

The set pulse generation circuit includes a one-shot pulse generation circuit for generating a plurality of pulses each having a fixed pulse width as the set pulse from the clock pulse train generated by the oscillation circuit. The set pulse generation circuit may reduce the repetition frequency of the clock pulse train generated by the oscillation circuit while the self-refresh mode signal holds the second logic level, if necessary. A frequency dividing circuit for outputting the frequency-divided clock pulse train to the one-shot pulse generation circuit and resetting the output of the frequency-divided clock pulse train while the self-refresh mode signal holds the first logical level; .

According to the present invention, the flip-flop circuit is defined by a pulse width of a reset pulse in order to prevent reset errors of individual refresh request signals in the self-refresh mode, that is, reset errors of the timing signal. In the period, a reset priority circuit is provided for resetting the timing signal even when a set pulse is given. In this case, the reset pulse generation circuit generates a front edge of the reset pulse by delaying a front edge of the pulse of the timing signal by a first delay time, and responds to the reset pulse by the flip-flop circuit. Means for generating a trailing edge of the reset signal by delaying the trailing edge of the pulse of the timing signal by a second delay time shorter than the first delay time when the trailing edge of the pulse of the timing signal is generated It is preferable to provide This is because the first refresh operation in the next self-refresh mode can be started earlier.

[0014]

Embodiments of a semiconductor memory according to the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a microcontroller incorporating a DRAM according to the present invention. The illustrated system controller 100 and the microcontroller 20
0 is a controller mounted on one semiconductor chip, respectively, and both are incorporated in, for example, video equipment. According to this example, the system controller 1
00 controls the overall control of the video equipment. The microcontroller 200 controls the motor, for example,
PU (central processing unit) 210, DRAM2
20, DRAM & bus controller 230, clock generator 240, interrupt controller 250, system controller interface (sys-con IF) 2
A large number of circuit blocks such as the peripheral circuit 270 and the peripheral circuit 270 are provided on one semiconductor chip. Thick lines in the figure represent buses for transferring addresses and data. The DRAM 220 includes a refresh control circuit 22
1 and a DRAM core 222 having a memory cell array requiring a refresh operation.

In the normal mode of the microcontroller 200, the clock generator 240
20. A clock (CLK) pulse train is supplied to each circuit block including 20. The CPU 210 can exchange data with the system controller 100 via the DRAM & bus controller 230 and the system controller IF 260. Further, the CPU 210 can access the DRAM 220 via the DRAM & bus controller 230. At this time, a DRAM having a function as a logic circuit for controlling memory access is used.
The bus controller 230 outputs a RAS signal, a CAS signal,
Control signals such as a write enable (WE) signal and a refresh request (RRQ) signal for auto refresh control are supplied to the DRAM 220. In the normal mode, a self-refresh mode (SRMOD) signal set to “L” level is supplied to the DRAM 220. The bus between the DRAM 220 and the DRAM & bus controller 230 is used for transferring addresses and data.

When the microcontroller 200 receives a sleep (SLEEP) signal from the system controller 100, it enters a power down mode. Upon receiving the SLEEP signal, the interrupt controller 250 provides an interrupt request (IRQ) signal to the CPU 210. In response to this IRQ signal, CPU 210 provides a clock stop request (RQ) signal to DRAM & bus controller 230. In response to the RQ signal, the DRAM
The & bus controller 230 applies a plurality of pulses of the RRQ signal to the DRAM 220 only for a transition period of a fixed length, and then sets the SRMOD signal to the “H” level to cause the DRAM 220 to enter the self-refresh mode. A clock stop command (CMD) signal is applied to clock generator 240. In response to the CMD signal, the clock generator 240 stops supplying the CLK pulse train. Therefore, DRAM 220 is no longer accessed.

When the microcontroller 200 in the power down mode receives the resume (RESUME) signal from the system controller 100, it returns to the normal mode. At this time, the DRAM & bus controller 230 releases the self-refresh mode of the DRAM 220 by setting the SRMOD signal to “L” level, and then supplies the clock generator 240 with a CMD signal for starting clock supply.

FIG. 2 shows an example of the internal configuration of the refresh control circuit 221. Refresh control circuit 221
Are three independent terminals for receiving the RAS signal, the RRQ signal, and the SRMOD signal from the DRAM & bus controller 230, and the clock generator 24.
0 to one terminal for receiving a CLK pulse train. Further, the refresh control circuit 221 includes the self-refresh control circuit 5, two D flip-flops 50 and 51, one OR gate 52, and a row address generation circuit 60. The self-refresh control circuit 5 is a timer for automatically generating a periodic refresh request (PRRQ) signal in response to the SRMOD signal. (SET) a set pulse generation circuit 20 for generating a pulse;
The circuit includes a flip-flop circuit 30 for generating a signal and a reset pulse generation circuit 40 for generating a reset (RESET) pulse. D flip-flop 50 outputs the RAS signal, and D flip-flop 51 outputs the RR signal.
This is means for synchronizing the Q signal with the CLK pulse train. The RASS signal in FIG.
The SRQ signal is an RRQS signal, and the RRQS signal is a synchronized RRQ signal. The OR gate 52 has an internal RAS (I signal) which is a logical sum signal of the RAS signal, the RRQS signal, and the PRRQ signal.
RAS) signal to the DRAM core 222. The row address generation circuit 60 generates a row address (RAD) representing a refresh address from the RRQS signal or the PRRQ signal.
This is a circuit for automatically generating a signal. Generated RA
D signal and a row clock (RC
The K) pulse is supplied to the DRAM core 222. The row address generation circuit 60 is composed of two delay circuits 6
1, 62, one NOR gate 63, and one address counter 64. The RRQD signal in the figure is a signal obtained by delaying the RRQS signal by the delay circuit 61.
The PRRQD signal is a signal obtained by delaying the PRRQ signal by the delay circuit 62. The NOR gate 63 generates an RCK pulse from the RRQD signal and the PRRQD signal. The address counter 64 is a refresh address, that is, 1 which is a target of a refresh operation in the memory cell array.
Holds the row address for specifying the row. This row address is updated in synchronization with the rising edge of the RCK pulse.

Hereinafter, a detailed configuration of each of the four circuits 10, 20, 30, 40 constituting the self-refresh control circuit 5 will be described.

In the oscillation circuit 10, the SRMOD signal is "H".
A circuit for generating a CLKA pulse train while the level is held. When the SRMOD signal transits from the “L” level to the “H” level, the circuit before the first clock pulse in the CLKA pulse train is generated. An edge can be generated. To explain in detail, the oscillation circuit 1
0 indicates that the first and second inverters 11 and 12 cascade-connected to each other, the capacitor C1 having a first terminal coupled to the output of the second inverter 12, and that the SRMOD signal holds the "L" level. And a NAND gate 13 for inverting and outputting the output of the second inverter 12 while the SRMOD signal holds the "H" level. NAND gate 1
3 to generate a CLKA pulse train by inverting the output of the third inverter 3 and the NAND gate 1
3 is coupled to the second terminal of the capacitor C1 and a second resistor R2 is coupled to couple the second terminal of the capacitor C1 to the input of the first inverter 11.
And a P-channel MOS transistor (P) for applying a constant “H” level to the input of the first inverter 11 only while the SRMOD signal holds the “L” level.
(MOS transistor) Q1 and diodes D1 and D2 for clamping the input of the first inverter 11. Vdd in the figure represents a power supply voltage. S0
Is the signal at the second terminal of the capacitor C1, S1 is the input signal of the first inverter 11, S2 is the input signal of the second inverter 12, S3 is the signal at the first terminal of the capacitor C1, and S4 is the signal at the first terminal of the capacitor C1. 3 shows the input signals of the three inverters 14, respectively.

The set pulse generation circuit 20 includes the oscillation circuit 1
This is a circuit for generating a SET pulse to be given to the flip-flop circuit 30 based on the CLKA pulse train generated by the “0”. More specifically, the set pulse generation circuit 20 generates the divided clock (CLKC) obtained by reducing the repetition frequency of the CLKA pulse train to に while the SRMOD signal holds the “H” level.
While the pulse train is output and the SRMOD signal is held at the “L” level, a frequency divider circuit composed of two frequency dividers 21 and 22 resets the output of the CLKC pulse train, and a CLKC pulse train And a one-shot pulse generation circuit 23 for generating a plurality of pulses each having a fixed pulse width as a SET pulse. The intermediate frequency-divided clock (CLKB) pulse train supplied from the former frequency divider 21 to the latter frequency divider 22 is obtained by reducing the repetition frequency of the CLKA pulse train to half.

The flip-flop circuit 30 is a circuit for setting and resetting a timing signal for controlling a refresh operation of one row of the memory cell array, that is, a PRRQ signal, in response to a given SET pulse and a RESET pulse, respectively. In the period defined by the pulse width of the RESET pulse, a reset priority circuit for resetting the PRRQ signal is provided even if the SET pulse is given. More specifically, the flip-flop circuit 30 includes first and second NOR gates 3.
1, 32. The first NOR gate 31 is connected to S
The ET pulse and the output of the second NOR gate 32 are input. The second NOR gate 32 receives the RESET pulse and the output of the first NOR gate 31. Second
The output of the NOR gate 32 is the PRRQ signal.

The reset pulse generation circuit 40 generates an R signal to be applied to the flip-flop circuit 30 based on the PRRQ signal set by the flip-flop circuit 30.
A circuit for generating an ESET pulse;
A front edge of the RESET pulse is generated by delaying a front edge of the pulse of the Q signal by a first delay time.
In response to the T pulse, the flip-flop circuit 30
When the trailing edge of the pulse of the RRQ signal is generated, the PR
There is provided means for generating a trailing edge of the RESET pulse by delaying a trailing edge of the pulse of the RQ signal by a second delay time shorter than the first delay time. More specifically, the reset pulse generation circuit 40
A first inverter 41 for inverting the RQ signal, a resistor R3 having a first terminal coupled to the output of the first inverter 41, and a first terminal coupled to a second terminal of the resistor R3. A capacitor C2 having a grounded second terminal and a constant "H" level applied to the first capacitor C2 only while the PRRQ signal holds the "L" level.
By inverting the signal of the PMOS transistor Q2 to be applied to the terminal and the signal of the first terminal of the capacitor C2,
A second inverter 42 for generating a SET pulse. Vdd in the figure represents a power supply voltage.
DS1 represents an output signal of the first inverter 41, and DS2 represents an input signal of the second inverter 42.

FIG. 3 shows an example of the internal configuration of the DRAM core 222. The DRAM core 222 includes a memory cell array 81 having dynamic memory cells forming a matrix of n rows × m columns (n and m are integers). One dynamic memory cell 80 illustrated in FIG. 3 is connected to one of a pair of bit lines BL and / BL, and one word line together with other dynamic memory cells belonging to the same row. It can be selected through WL. The same applies to dynamic memory cells in other rows. Further, the DRAM core 222 includes an address latch 82, an inverter 83, an address multiplexer 84, a row decoder 85, and bit lines BL and / B, respectively.
And a differential amplifier block 87 including a plurality of sense amplifiers 86 for amplifying a small voltage difference between L. The address latch 82 and the inverter 83
While the S signal holds the “L” level, the external row address (ERAD) signal given from the DRAM & bus controller 230 for normal access is applied to the CLK signal.
It is configured to be latched in synchronization with the rising edge of the pulse train. The address multiplexer 84
While the RCK pulse holds the “L” level, the RAD signal given from the address counter 64 is given, and while the RCK pulse holds the “H” level, the ERAD signal latched by the address latch 82 is given. It is a circuit for selecting. The row decoder 85 selects one word line from the n word lines of the memory cell array 81 in response to the RAD signal or the ERAD signal supplied from the address multiplexer 84 in response to the IRAS signal. Circuit. Further, the PMOS transistors Q3 and Q3 are precharged so that the bit lines BL and / BL are precharged while the IRAS signal is at the "L" level.
Q4 is provided. Vpc in the figure represents a precharge voltage. The CAS signal, the WE signal, and the data bus are not shown.

FIG. 4 shows an operation example of the refresh control circuit 221. In this example, during the transition period of the microcontroller 200 from the normal mode to the power down mode, a plurality of pulses of the RRQ signal
The refresh control circuit 221 is provided together with the pulse train. The SRMOD signal is fixed at “L” level. In this case, the RRQS signal becomes the IRAS signal as it is, and the refresh operation for each row of the memory cell array 81 is performed. Moreover, the address represented by the RAD signal is sequentially updated as A, A + 1, A + 2,... In synchronization with the falling edge of the RRQD signal, that is, in synchronization with the rising edge of the RCK pulse. FIG.
In the period in which the IRAS signal holds the “L” level, the PMOS transistors Q3 and Q3
4 is turned on, the bit lines BL and / BL are precharged (equalized). When the IRAS signal transitions from "L" to "H", the PMOS transistors Q3 and Q4 are turned off, and the row
Decode the signal. As a result, one word line WL is selected, and the storage bit of the dynamic memory cell 80 connected to the word line WL is read onto the bit line BL. At this time, a small voltage difference generated between the pair of bit lines BL and / BL is amplified by the sense amplifier 86,
The storage bits are rewritten to the dynamic memory cell 80. The above operation is the refresh operation.
Other dynamic memory cells connected to the same word line WL are also subjected to the refresh operation at the same time. RCK
After the refresh operation of one row is completed in this manner, the rising edge of the pulse is delayed by the delay circuit 61 in FIG.
Are generated at a point in time when a certain time determined by the above characteristic has elapsed. Note that the memory cell array 81
Normal access of ERAD signal, RAS signal, CA
This is performed using the S signal, the WE signal, and the like, but the description thereof is omitted.

FIG. 5 shows another example of the operation of the refresh control circuit 221. In this example, in the power down mode of the microcontroller 200, the DRAM 2
It is assumed that the setting of the self-refresh mode 20 is instantaneously released. Even in such a case, the SRMO
In response to the transition of the D signal from “L” to “H”, the refresh operation of a plurality of rows of the memory cell array 81 starts immediately. The RRQ signal is fixed at “L” level,
The supply of the CLK pulse train is stopped. By the way, time T0
When the SRMOD signal transitions from "H" to "L" at the time, the PMOS transistor Q1 in the oscillation circuit 10 is turned on. Therefore, the oscillation circuit 1 before time T0
S0 = S1 = S3 = S4 =
The state shifts to the state of “H” (= Vdd) and S2 = “L”. In this state, the voltage between both terminals of the capacitor C1 is zero, and the oscillation stops. CLKA = C
LKB = CLKC = "L". Thereafter, when the SRMOD signal transitions from "L" to "H" at time T1, the S4 signal falls, so that the leading edge (rising edge) of each pulse of CLKA, CLKB and CLKC.
Is generated, a SET pulse having a constant pulse width is generated. Therefore, at time T1, PRR
The Q signal changes from “L” to “H”. This PRRQ signal is reset after a certain time. On the other hand, at time T1
, The PMOS transistor Q1 is turned off in response to the transition of the SRMOD signal from “L” to “H” at the time point “1”. Therefore, the levels of the S0 signal and the S1 signal gradually decrease according to the discharge from the second terminal of the capacitor C1. The time constant of this discharge depends on the resistance R1 and the capacitor C1.
It is determined by Then, at time T2, the level of the S1 signal is changed to the threshold voltage Vth of the first inverter 11.
, The S2 signal is inverted from “L” to “H”. As a result, the S3 signal changes from “H” to “L”,
4 signal changes from “L” to “H”, CLKA pulse changes to “H”
Respectively to “L”. The level of the S0 signal changes to -Vth. Therefore, after the time T2, the second terminal of the capacitor C1 is charged, and the level of the S0 signal gradually increases according to the time constant. And
When the level of the S1 signal becomes equal to the threshold voltage Vth until time T3, the S2 signal is inverted from "H" to "L". As a result, the S3 signal changes from “L” to “H”, the S4 signal changes from “H” to “L”,
The pulse changes from “L” to “H”, and the CLKB pulse changes to “H”.
Respectively to “L”. The level of the S0 signal changes to Vdd + Vth. Therefore, after the time T3, discharge from the second terminal of the capacitor C1 is performed, and S2
The level of the 0 signal gradually decreases according to the time constant and returns to the same state as at time T2. Similarly, a CLKA pulse train having a constant repetition frequency 1 / T is generated. Then, at time T4, each pulse of CLKA, CLKB, and CLKC rises, and a SET pulse is generated. Therefore, at time T4, the PRRQ signal transitions from "L" to "H". Similarly, 1 /
A pulse train of the PRRQ signal having a repetition frequency of ４ of T is generated. Note that, as shown in FIG.
The upper limit level of the signal is clamped to Vdd + Vf, and the lower limit level of the S1 signal is clamped to -Vf. Where V
f is a forward voltage of each of the diodes D1 and D2.

As described above, according to the refresh control circuit 221 in FIG. 2, the rising edge of the PRRQ signal is immediately generated in response to the transition of the SRMOD signal from "L" to "H" at the time T1. , The first refresh operation starts immediately. Thereafter, a periodic refresh request (PR
RQ) signal is automatically generated. The refresh interval 4T is determined in consideration of the data holding characteristics of the dynamic memory cell.

FIG. 6 shows still another operation example of the refresh control circuit 221. In this example, in the normal mode of the microcontroller 200, the DRAM 2
It is assumed that the setting of the self-refresh mode 20 is made instantaneously. Even in such a case, destruction of data stored in the memory cell array 81 is avoided. Now, for a short time from time t0 to time t1, the SRMO
The level of the D signal is set to “H”. Such a situation may occur, for example, when the RESUME signal is supplied immediately after the microcontroller 200 attempts to enter the power down mode in response to the SLEEP signal. When the SRMOD signal transitions from "L" to "H" at time t0, the S4 signal falls and the leading edge (rising edge) of each pulse of CLKA, CLKB and CLKC, as in the case of time T1 in FIG. Is generated, a SET pulse having a constant pulse width is generated. Therefore, at time t0, the PRRQ signal changes from “L” to “H”, and the IRAS signal changes from “L” to “H”. When the level of the PRRQ signal becomes "H", the PMOS transistor Q in the reset pulse generation circuit 40
2 turns off. Therefore, the pulse delay time in the reset pulse generation circuit 40 is a time DLY1 determined by a time constant based on the resistance R3 and the capacitor C2. That is, the reset pulse generation circuit 40 operates at time t0.
, The leading edge (rising edge) of the pulse of the PRRQ signal is delayed by DLY1 to generate the leading edge (rising edge) of the RESET pulse at time t2. The RE thus set to the “H” level
In response to the SET pulse, the flip-flop circuit 30
Generates the trailing edge (falling edge) of the pulse of the PRRQ signal. Therefore, no matter how short the period from time t0 to time t1, the IRAS signal is
"H" level is maintained only for a period of the same length as. PRR
When the level of the Q signal becomes “L”, the PMOS transistor Q2 in the reset pulse generation circuit 40 turns on. Therefore, the pulse delay time in the reset pulse generation circuit 40 is the time DLY independent of the resistance R3.
2 (<DLY1). That is, the reset pulse generation circuit 40 sets the falling edge of the PRRQ signal to DLY.
Delay by 2 to generate the trailing edge (falling edge) of the RESET pulse. DLY1 is set to be equal to or longer than the time required for the refresh operation of all the dynamic memory cells belonging to the specified one row of the memory cell array 81. DLY2 is set to a time longer than the time required for precharging the bit lines BL and / BL. The address represented by the RAD signal is updated from A to A + 1 in synchronization with the falling edge of the PRRQD signal. The updating of the RAD signal is delayed from the time t2 by the pulse delay time DLY3 of the delay circuit 62. D
LY3 is set to be equal to or longer than the time required to bring one selected word line into a non-selected state in order to avoid multiple selection of word lines in the memory cell array 81.

As described above, the trailing edge of the RESET pulse is generated early when the time equal to DLY2 has elapsed from time t2, so that the flip-flop circuit 30 can accept the SET pulse immediately after that.
According to the example of FIG. 6, at time t3, the SRMOD signal changes from “L” to “H”, the SET pulse is received by the flip-flop circuit 30, and the DRAM 220 enters the self-refresh mode. Further, the example of FIG.
Time t corresponding to the end of the self-refresh mode
4, corresponding to the last SET pulse generated in
It is assumed that the SRMOD signal is erroneously changed from “L” to “H” at time t6 while the RESET pulse holds the “H” level from time t5. At the subsequent time t7, this SRMOD signal becomes “H”.
To “L”. In this case, at time t6, S
Although the ET pulse is generated, the SET pulse is ignored because the flip-flop circuit 30 has a reset-priority circuit configuration. Note that S at time t4
1 related to address E activated based on the ET pulse
The row refresh operation ends by time t5. The address represented by the RAD signal is from E to E +
It is updated to 1.

The refresh input specification using the RRQ signal and the SRMOD signal, which are independent signals, has been described above. Such a refresh input specification is suitable for a built-in DRAM provided together with another logic circuit such as a CPU on one semiconductor chip as in the above example. This is because the restriction on the number of input pins is eased in a built-in DRAM. However, as long as the number of pins permits, a similar refresh input specification can be adopted for a general-purpose DRAM.

[0032]

As described above, according to the present invention, the first terminal for receiving the individual pulse of the refresh request signal and the self-refresh mode signal for receiving the self-refresh mode signal independently from the first terminal are provided. Since the refresh input specification of the semiconductor memory having the second terminal is adopted, the load on the logic circuit for controlling access to the semiconductor memory is reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a microcontroller incorporating a DRAM according to the present invention.

FIG. 2 is a block diagram showing an example of an internal configuration of a refresh control circuit in FIG. 1;

FIG. 3 is a block diagram showing an example of an internal configuration of a DRAM core in FIG. 1;

FIG. 4 is a timing chart illustrating an operation example of the refresh control circuit of FIG. 2;

FIG. 5 is a timing chart illustrating another operation example of the refresh control circuit in FIG. 2;

FIG. 6 is a timing chart showing still another operation example of the refresh control circuit of FIG. 2;

[Explanation of symbols]

 Reference Signs List 5 self-refresh control circuit 10 oscillation circuit 20 set pulse generation circuit 30 flip-flop circuit 40 reset pulse generation circuit 60 row address generation circuit 80 dynamic memory cell 81 memory cell array 100 system controller 200 microcontroller 210 CPU 220 DRAM 221 refresh control circuit 222 DRAM Core 230 DRAM & bus controller

Claims (14)

[Claims] 1. A memory cell array requiring a refresh operation, first and second terminals independent of each other, and one row of the memory cell array each time one pulse of a refresh request signal is applied to the first terminal. Of the memory cell array in response to a transition from a first logic level to a second logic level of a self-refresh mode signal applied to the second terminal. And a refresh control circuit for controlling the operation of the semiconductor memory. 2. The semiconductor memory according to claim 1, wherein said semiconductor memory includes a logic circuit for supplying said refresh request signal to said first terminal and said self-refresh mode signal to said second terminal. And a memory provided on one semiconductor chip. 3. The semiconductor memory according to claim 1, wherein said refresh control circuit comprises: an address counter for holding a row address designating one row to be refreshed in said memory cell array; A row decoder for selecting one word line from a plurality of word lines included in the cell array in accordance with the row address held in the address counter, wherein the row held in the address counter is provided. The address is
A semiconductor memory, which is updated in response to the end of the refresh operation of the one row and after a lapse of time required for setting the selected word line in a non-selected state. 4. The semiconductor memory according to claim 1, wherein said refresh control circuit sets a timing signal for controlling a refresh operation of one row of said memory cell array in response to a given set pulse and a reset pulse, respectively. A flip-flop circuit for resetting and resetting; an oscillation circuit for generating a clock pulse train while the self-refresh mode signal holds the second logic level; and the clock generated by the oscillation circuit. A set pulse generating circuit for generating the set pulse to be applied to the flip-flop circuit based on a pulse train; and the reset to be applied to the flip-flop circuit based on the timing signal set by the flip-flop circuit To generate a pulse Semiconductor memory is characterized in that a reset pulse generating circuit. 5. The semiconductor memory according to claim 4, wherein said oscillating circuit outputs a signal of said clock pulse train when said self-refresh mode signal transitions from said first logic level to said second logic level. A semiconductor memory comprising means for generating a leading edge of a first clock pulse. 6. The semiconductor memory according to claim 5, wherein said oscillation circuit comprises: an even number of inverters connected in cascade with each other; and a first circuit coupled to an output of a last one of the even number of inverters. A capacitor having a terminal, a constant logic level is output while the self-refresh mode signal holds the first logic level, and the self-refresh mode signal holds the second logic level. A logic gate for inverting and outputting the output of the last-stage inverter; a first resistor for coupling the output of the logic gate to a second terminal of the capacitor; A second resistor for coupling two terminals to an input of a first one of the even number of inverters; And a transistor for applying the same logic level to the input of the first-stage inverter as long as the signal holds the first logic level. memory. 7. The semiconductor memory according to claim 4, wherein said set pulse generation circuit generates a plurality of pulses each having a fixed pulse width as said set pulse from said clock pulse train generated by said oscillation circuit. A one-shot pulse generation circuit for performing the operation. 8. The semiconductor memory according to claim 7, wherein said set pulse generation circuit generates said clock generated by said oscillation circuit while said self-refresh mode signal holds said second logic level. The divided clock pulse train obtained by reducing the repetition frequency of the pulse train is output to the one-shot pulse generation circuit, and the frequency division is performed while the self-refresh mode signal holds the first logic level. A semiconductor memory further comprising a frequency dividing circuit for resetting an output of a clock pulse train. 9. The semiconductor memory according to claim 4, wherein the flip-flop circuit resets the timing signal during a period defined by a pulse width of the reset pulse even if the set pulse is given. A semiconductor memory comprising a reset priority circuit. 10. The semiconductor memory according to claim 9, wherein said reset pulse generation circuit generates a front edge of said reset pulse by delaying a front edge of said timing signal pulse by a first delay time. When a trailing edge of the timing signal pulse is generated by the flip-flop circuit in response to a reset pulse, the trailing edge of the timing signal pulse is delayed by a second delay time shorter than the first delay time. A means for generating a trailing edge of the reset pulse. 11. When a memory cell array requiring a refresh operation and a self-refresh mode signal are applied,
A refresh control circuit for controlling a refresh operation of a plurality of rows of the memory cell array in response to a transition of the self-refresh mode signal from a first logic level to a second logic level; Comprises an oscillating circuit for generating a clock pulse train while the self-refresh mode signal holds the second logical level, the oscillating circuit comprising: A means for generating a leading edge of a first clock pulse in the clock pulse train at the time of transition from the first logic level to the second logic level. 12. The semiconductor memory according to claim 11, wherein said oscillation circuit comprises: an even number of inverters connected in cascade with each other; and a first circuit coupled to an output of a last one of the even number of inverters. A capacitor having a terminal, a constant logic level is output while the self-refresh mode signal holds the first logic level, and the self-refresh mode signal holds the second logic level. A logic gate for inverting and outputting the output of the last-stage inverter; a first resistor for coupling the output of the logic gate to a second terminal of the capacitor; A second resistor for coupling two terminals to an input of a first one of the even number of inverters; And a transistor for applying the same logic level as the constant logic level to the input of the first stage inverter only while the load signal holds the first logic level. Semiconductor memory. 13. When a memory cell array requiring a refresh operation and a self-refresh mode signal are applied,
A refresh control circuit for controlling a refresh operation of a plurality of rows of the memory cell array in response to a transition of the self-refresh mode signal from a first logic level to a second logic level; A flip-flop circuit for setting and resetting a timing signal for controlling a refresh operation of one row of the memory cell array in response to a given set pulse and a reset pulse, respectively, wherein the self-refresh mode signal is An oscillation circuit for generating a clock pulse train while holding the second logic level; and generating the set pulse to be applied to the flip-flop circuit based on the clock pulse train generated by the oscillation circuit. A set pulse generation circuit for A reset pulse generation circuit for generating the reset pulse to be applied to the flip-flop circuit based on the timing signal set by the flip-flop circuit, wherein the flip-flop circuit is defined by a pulse width of the reset pulse A reset priority circuit for resetting the timing signal even when the set pulse is applied during a period of time. 14. The semiconductor memory according to claim 13, wherein said reset pulse generation circuit generates a front edge of said reset pulse by delaying a front edge of said timing signal pulse by a first delay time. When a trailing edge of the timing signal pulse is generated by the flip-flop circuit in response to a reset pulse, the trailing edge of the timing signal pulse is delayed by a second delay time shorter than the first delay time. A means for generating a trailing edge of the reset pulse.