JPH11337908A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform an excellent display without being affected by source voltage fluctuation in a shift register. SOLUTION: A liquid crystal display device provided with a scanning line drive circuit 20 having plural first buffers 23a-23d provided in every scanning line and respectively consisting of plural stages of inverters and first shift registers 21 successively sending out shift passes in corresponding scanning lines through plural first buffers and a signal line drive circuit 10 is constituted so as to make the drive source of plural first buffers and the drive source of the first shift register separate systems.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit integrated type active matrix type liquid crystal display device.

[0002]

2. Description of the Related Art In general, an active matrix type liquid crystal display device has a structure in which a liquid crystal layer is sandwiched between an array substrate and a counter substrate having a counter electrode.

As shown in FIG. 5, a conventional drive circuit integrated type active matrix type liquid crystal display device array substrate includes a display section 1, a signal line drive circuit 10, and a scan line drive circuit 2 as shown in FIG.
0. The display unit 1 includes a plurality of intersecting scanning lines 5 and signal lines 3 and a T formed at each intersection thereof.
An FT (Thin Film Transistor) element 7 and a pixel electrode 8 connected to the TFT element 7 are provided.

Each TFT element 7 has a configuration in which the gate is connected to the corresponding scanning line 5, the drain is connected to the corresponding signal line 3, and the source is connected to the corresponding pixel electrode 8.

A plurality of scanning lines 5 are sequentially driven by a scanning line driving circuit 20. The plurality of signal lines 3 are driven by the signal line driving circuit 10. The scanning line driving circuit 20 includes a shift register 21 and a buffer circuit 23,
Output signal from this shift register 21 (shift path)
Are sequentially applied to the scanning lines 5 via the buffer circuit 23,
Thus, the scanning lines 5 are sequentially selected and activated. The signal line drive circuit 10 includes a shift register 11, a buffer circuit 13, a video bus line 17, and a transmission gate 18 provided for each signal line 3. Output signals (shift paths) of the shift register 11 are sequentially sent to the transmission gate 18 via the buffer circuit 13. Then, the transmission gates are sequentially turned on, a video signal transmitted via the video bus line 17 is captured, and the captured video signal is transmitted to the corresponding signal line 3 and displayed.

[0006]

The scanning line driving circuit 20 of the conventional active matrix type liquid crystal display device has a driving power supply line for the shift register 21 and a buffer 23 for reducing the number of input power supplies to the liquid crystal display device. Drive power supply line 25
a and 25b were common. Note that the same applies to the signal line driving circuit 10. In this structure, the T
When examining the write characteristics of the FT element 7 by lowering the high level of the gate voltage, or when examining the holding characteristics by increasing the low level of the gate voltage and changing the luminance of the liquid crystal display unit 1, the power supply voltage for driving the shift register 21 is used. , The operation is hindered, and the TF
There is a problem that the characteristics of the T element 7 cannot be measured. In addition, even in the normal driving, when a slight power supply voltage fluctuation occurs in the shift register 21, the voltage of the scanning line 5 also slightly changes, which causes a problem that the screen quality is hindered.

As described above, in the conventional liquid crystal display device, since the power supply for driving the shift register and the power supply for driving the buffer circuit are shared, it is difficult to separately evaluate the display unit 1 and the driving unit 20. In addition, there is a problem that the fluctuation of the power supply voltage in the shift register directly affects the screen quality.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and it is possible to obtain a good display which is not affected by power supply voltage fluctuations in a shift register. It is an object of the present invention to provide a liquid crystal display device that can perform the operation.

[0009]

A liquid crystal display device according to the present invention comprises a plurality of scanning lines, a plurality of signal lines provided so as to intersect these scanning lines, and each intersection of the scanning lines and the signal lines. A switching element for transmitting a signal from a corresponding signal line to the pixel electrode based on a voltage of a corresponding scanning line provided for each pixel electrode, and the plurality of scanning lines. A scanning line driving circuit for driving,
And an array substrate having a signal line driving circuit for driving the plurality of signal lines, and a counter substrate having a counter electrode, wherein the counter electrode and the pixel electrode are disposed so as to face each other,
A liquid crystal layer sandwiched between the array substrate and the opposing substrate, wherein the scanning line driving circuit is provided for each scanning line, and each of the first buffers includes a plurality of stages of inverters; A first shift register for sequentially transmitting a shift path to a corresponding scanning line via a plurality of first buffers, a driving power supply for the plurality of first buffers and a first power supply for the first buffers. And a drive power supply for the shift register and a drive power supply for the shift register.

In the liquid crystal display device configured as described above, the driving power source for the buffer and the driving power source for the shift register are provided in separate systems in the scanning line driving circuit. The writing characteristics of writing a video signal to the electrode and the holding characteristics of the video signal can be measured without deteriorating the operation characteristics of the shift register. Also, even if the power supply voltage fluctuates in the shift register, the scanning line voltage and the buffer output for opening and closing the switch element are not affected, so that a good image quality free from uneven writing and uneven holding can be obtained. Can be.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the active matrix type liquid crystal display device according to the present invention will be described with reference to FIGS. FIG. 1 shows the configuration of the liquid crystal display device according to the first embodiment, and FIG. 2 shows the configuration of the scanning line driving circuit 20 according to the first embodiment. FIG. 3 shows the configuration of the signal line driving circuit 10.

The liquid crystal display device according to the first embodiment has
In the conventional liquid crystal display device illustrated in FIG. The configuration is as follows.

[0013] That is, the shift register 11 are respectively supplied through the driving voltage V _DDX1, V _SSX1 power line 12a, 12b, the buffer circuit 13 drive voltage V _DDX2, V
_SSX2 is supplied via power lines 14a and 14b, respectively. Further, the shift register 21 driving voltage V _DDY1, V _SSY1 are respectively supplied through the power line 22a, a 22b, the buffer circuit 23 drive voltage V _DDY2, V
_SSY2 is supplied via power supply lines 24a and 24b, respectively.

FIG. 2 shows a detailed configuration of the scanning line driving circuit 20 according to the first embodiment. Shift register 2
1 has a D-type flip-flop using a clocked inverter for each scanning line 5. This flip-flop is connected to clock inverters 21a, 21b, 23d, 21e.
And inverters 21c and 21f. These clocked inverters and inverters are composed of p-type transistors and n-type transistors, and are driven by driving voltages V _DDY1 and V _SSY1 supplied via power supply lines 22a and 22b. A clock signal φ is input to the clocked inverters 21a and 21e, and a clock signal φ is input to the clocked inverters 21b and 21d.
Is input.

The buffer circuit 23 comprises four cascaded inverters 23a, 23b, 23
c, and 23d. Each of these inverters 23a, 23b, 23c, 23d is composed of a p-type transistor and an n-type transistor, and is driven by driving voltages V _DDY2 , V _SSY2 supplied via power supply lines 24a, 24b. The clocked inverter 21a is configured to transmit the shift path supplied from the preceding flip-flop to the corresponding buffer and to the next flip-flop via the clocked inverter 21d.

In the scanning line drive circuit 20 having such a configuration, if an off-leak current occurs in the transistors constituting the inverters 21a to 21f in the shift register 21 during driving, for example, a steady state is established between the power supply lines 22a and 22b. Current flows in a specific manner, and the potential difference between the power supply line 22a and the power supply line 22b decreases. Then, the potential difference between the power supply line 22a and the power supply line 24a, and the power supply line 22b and the power supply line 24b
And a four-stage inverter 2 connected in cascade.
3a to _23d , the threshold voltage V _thp of the p-type transistor and the threshold voltage V of the n-type transistor
_{Within the} range smaller than _thn , the buffer circuit 23 is not affected by the voltage fluctuation of the power supply lines 22a and 22b,
It outputs the voltage supplied to 4a, 24b. For this reason,
Writing to the pixel unit via the TFT element 7 of the display unit 1,
The retention of the pixel signal is not affected, and as a result, the display quality can be prevented from deteriorating as much as possible even if the power supply voltage fluctuates in the shift register.

In the scanning line driving circuit 20,
The writing characteristic of the TFT element in the display unit 1 to the pixel electrode is
The power supply line is used when the high level of the scanning line voltage is lowered to check the luminance of the display unit 1 or the characteristic of holding the video signal of the pixel electrode is checked by raising the low level of the scanning line and the luminance change of the display unit 1. If the voltage supplied to the power supply line 24a is reduced or the voltage supplied to the power supply line 24b is increased while the voltage supplied to the power supply lines 22a and 22b is fixed at a constant voltage, the operation of the shift register 21 is performed. Characteristics can be examined without affecting the characteristics. As a result, the image quality evaluation in the display unit 1 can be evaluated separately from the operation characteristics of the drive circuit 20.

FIG. 3 shows a detailed configuration of the signal line driving circuit 10 according to the first embodiment. The shift register 21 has a D-type flip-flop using a clocked inverter for each signal line 3. This flip-flop is connected to clocked inverters 11a, 11b, 11d,
11e and inverters 11c and 11f. These clocked inverters and inverters are composed of p-type transistors and n-type transistors, and are driven by driving voltages V _DDX1 and V _SSX1 supplied via power supply lines 12a and 12b. A clock signal φ is input to the clocked inverters 11a and 11e, and an inverted signal φ bar of the clock signal φ is input to the clocked inverters 11b and 11d.

The buffer circuit 13 includes four cascaded inverters 13a, 13b, 13b for each signal line 3.
It has a buffer composed of c and 13d. Each of these inverters 13a, 13b, 13c, 13d is composed of a p-type transistor and an n-type transistor, and is driven by driving voltages V _DDX2 , V _SSX2 supplied via power supply lines 14a, 14b.

The clocked inverter 11a transmits the shift path supplied from the preceding flip-flop to the corresponding buffer via the clocked inverter 11d and to the next flip-flop.

The signal line driving circuit 10 thus configured
, Even if the drive voltage in the shift register 11 fluctuates, the buffer circuit 1
No. 3 is not affected, and the voltage supplied to the power supply lines 14a and 14b is supplied to the gate of each transmission gate 18. As a result, even if the power supply voltage fluctuates in the shift register, it is possible to prevent display quality from deteriorating as much as possible.

Next, a second embodiment of the liquid crystal display device according to the present invention will be described with reference to FIG. FIG. 4 shows the configuration of the scanning line driving circuit 20 of the liquid crystal display device according to the second embodiment.
Shown in The liquid crystal display device according to the second embodiment has the first
The configuration is such that the scanning line driving circuit of the liquid crystal display device of the embodiment is replaced with the scanning line driving circuit shown in FIG.

In the second embodiment, four cascaded inverters 23a,
The inverter 23d closest to the scanning line 5 among the inverters 23b, 23c and 23d is driven by the driving voltage supplied via the power supply lines 24a and 24b, and the other inverters 23a and 23d
23 b and 23 c are configured to be driven by the drive voltage of the shift register 21.

It is needless to say that the same effect as that of the first embodiment can be obtained even with this configuration.

The signal line drive circuit 10 may also drive only the inverter 13d closest to the signal line 3 of the buffer circuit 13 with the drive voltage supplied via the power lines 24a and 24b.

In the first or second embodiment, the signal line drive circuit 10 has the buffer circuit 13, but the present invention is applied to a liquid crystal display device having a signal line drive circuit without a buffer circuit. It goes without saying that the invention can be applied.

[0027]

As described above, according to the present invention, it is possible to obtain a good display which is not affected by the power supply voltage fluctuation in the shift register of the scanning line driving circuit.
The evaluation of the display unit and the scanning line driving circuit can be performed separately.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a first embodiment of a liquid crystal display device according to the present invention.

FIG. 2 is a diagram illustrating a configuration of a scanning line driving circuit according to the first embodiment.

FIG. 3 is a diagram illustrating a configuration of a signal line driving circuit according to the first embodiment;

FIG. 4 is a diagram showing a configuration of a scanning line driving circuit according to a second embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a conventional liquid crystal display device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Display part 3 Signal line 5 Scan line 7 TFT element 8 Pixel electrode 10 Signal line drive circuit 11 Shift register 12a, 12b Power supply line 13 Buffer circuit 14a, 14b Power supply line 15a, 15b Power supply line 17 Video bus line 18 Transmission gate 20 Scan Line drive circuit 21 Shift register 22a, 22b Power supply line 23 Buffer circuit 24a, 24b Power supply line 25a, 25b Power supply line

Claims (4)

[Claims] A plurality of scanning lines, a plurality of signal lines provided to intersect these scanning lines, a pixel electrode formed at each intersection of the scanning line and the signal line, and a plurality of scanning lines. A switching element for transmitting a signal from a corresponding signal line to the pixel electrode based on a voltage of a corresponding scanning line, a scanning line driving circuit for driving the plurality of scanning lines, and the plurality of scanning lines; An array substrate having a signal line driving circuit for driving a signal line; a counter substrate having a counter electrode, wherein the counter electrode and the pixel electrode are arranged so as to face each other; and between the array substrate and the counter substrate. A plurality of first buffers provided for each scanning line and each including a plurality of stages of inverters, and the plurality of first buffers. Corresponding run through In a liquid crystal display device having a first shift register for sequentially transmitting a shift path to a line, a drive power supply for the plurality of first buffers and a drive power supply for the first shift register are separated. A liquid crystal display device characterized by being configured as described above. 2. A method according to claim 1, wherein each of said plurality of first buffers is such that the last one of the plurality of inverters is driven by a drive power supply different from a drive power supply of said first shift register. Item 2. The liquid crystal display device according to item 1. 3. The signal line drive circuit is provided for each signal line, receives a video signal, and transmits the captured video signal to a corresponding signal line. A plurality of second buffers each comprising a plurality of inverters, and a second shift register for sequentially transmitting a shift path to a corresponding switch element via the plurality of second buffers. 3. The liquid crystal display device according to claim 1, wherein a driving power supply for the second buffer and a driving power supply for the second shift register are provided in different systems. 4. The apparatus according to claim 3, wherein each of said plurality of second buffers is such that the last one of the plurality of inverters is driven by a drive power source different from that of said second shift register. Liquid crystal display.