JPH11331485A - Solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the aperture effect in the case of read for reducing pixel data and to prevent the decline of image quality by generating reset signals to a reset means and control signals to a clamp means and varying the cycles of the reset signals and the control signals respectively. SOLUTION: A pulse RS is tentatively inputted first, the potential of a floating diffusion area FD is reset to the potential of a reset drain RD, then an electric charge Q1 is transferred to the floating diffusion area FD and signals V1 are obtained as output OS. In this case, the pulse RS of one time is generated by the pulses ϕ1 and ϕ2 of two times. Thus, the total of the previous electric charge Q1 and the electric charge Q2 transferred next is transferred to the floating diffusion area FD and V1+V2 for which both are totaled is obtained as output signals OS. It becomes equivalent to obtaining the output for which the output of the two picture elements of the picture element which generates Q1 and the picture element which generates Q2 are mixed as OS as a result and the aperture effect is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a solid-state imaging device for converting optical information into an electric signal, and more particularly to a solid-state imaging device that can be used in an image scanner.

[0002]

2. Description of the Related Art A line sensor is used as a scanner for capturing a film image. The scanner performs a preliminary operation, which is generally called prescan, on the film image to obtain a thumbnail image serving as an index of all cuts of the film image. Then, this thumbnail image is displayed on a television monitor screen or a display of a personal computer.

At this time, it is difficult to capture the data of all the pixels for all the cuts because the memory capacity is enormous, and when this is used as a thumbnail image, it is overspecified in terms of resolution. I will. For this purpose, pixel data is generally thinned out appropriately,
The number of pixels is reduced to the required resolution and stored in the memory.

[0004]

In this conventional system,
Since the pixels are thinned, the aperture effect at the time of sampling the image data becomes remarkable, which is not preferable in terms of image.

An object of the present invention is to provide a solid-state imaging device that suppresses the aperture effect in the case of data reading in which pixel data is reduced, and obtains image scanning data without deteriorating image quality.

[0006]

According to the present invention, there is provided a solid-state imaging device comprising: a photoelectric conversion element array in which a plurality of photoelectric conversion elements for generating electric charges according to an amount of incident light are arranged; A transfer register for sequentially transferring and outputting the transferred charges, a floating diffusion region disposed adjacent to an output stage of the transfer register for detecting the transferred charges, and a potential of the floating diffusion region as a reset signal. Reset means for periodically resetting to a predetermined voltage level in response thereto, potential detecting means for coupling to the floating diffusion region and detecting the potential of the floating diffusion region to generate an output signal, and reset by the reset means. Clamping means for periodically clamping the output signal of the potential detecting means to a predetermined reference voltage level in accordance with a control signal; and Generating a clamp signal output unit that outputs a change in the output signal of the position detection unit as a change from the reference voltage level, the reset signal to the reset unit, and the control signal to the clamp unit; The reset signal and the control means, each of which has a variable period, are formed on a common semiconductor substrate.

Since the cycle of the reset signal to the reset means and the cycle of the control signal to the clamp means are variable, when the number of image data is reduced, the cycle is increased to, for example, n pixels (n is 2 or more). , A reset signal and a control signal are generated in one cycle, so that n pixel signals are added and output.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 3 illustrates a solid-state imaging device according to an embodiment of the present invention, that is, a cross-sectional structure of a CCD (charge transfer unit) of a line sensor, a signal output circuit, and a normal transfer output operation of the line sensor. FIG. FIG. 4 is a signal waveform diagram for explaining the normal operation timing of the line sensor.

In FIG. 3, the silicon substrate has a p ^- type region 11 and n-type regions FD and RD. Forming a first insulating film (for example, SiO ₂ film) on a silicon substrate;
A first pattern of a first polysilicon layer P1 is formed thereon. Then, a second insulating film (for example, an SiO ₂ film) is formed on the first polysilicon layer P1, and a second pattern of the second polysilicon layer P2 is formed thereon. CCD2
In the first embodiment, the first polysilicon layers P1 and the second polysilicon layers P2 are alternately arranged in the horizontal direction.

The transfer pulse φ1 is composed of one first polysilicon layer P1 and one adjacent second polysilicon layer P1.
Two sets are applied. The transfer pulse φ2 is also applied to a set of one first polysilicon layer P1 adjacent to the above set and one second polysilicon layer P2 adjacent thereto.

Note that a p ^- type region is formed on the surface of the silicon substrate below the first polysilicon layer P1, while a p-type region is formed on the surface of the silicon substrate below the second polysilicon layer P2. Thus, even if the same potential is applied to the first polysilicon layer P1 and the second polysilicon layer P2, the potential of the silicon region below the first polysilicon layer P1 becomes the second potential.
It is lower than that below the polysilicon layer P2 and is configured to operate by two-phase driving.

The n-type region FD is a floating diffusion region, and is connected to the input terminal of the source follower amplifier SFA. n
The type region RD is a reset drain, and the n-type region RD
Is supplied with a potential φRD. The reset gate RG is
A polysilicon layer is provided on the silicon region 11 via an insulating film. A reset signal RS is supplied to the polysilicon layer.

The signal charges generated and accumulated in the photoelectric conversion unit (sensor) 1 shown in FIG. 3 are transferred to a CCD (transfer register) 2, and the transferred signal charges are converted into two-phase signals applied to transfer electrodes of the CCD 2. The pixels are sequentially transferred from left to right in the drawing for each pixel by the transfer pulses φ1 and φ2 to reach the final stage. In the drawings, a four-stage CCD is used for the purpose of making the description easy to understand.
, But actually there are more.

A floating diffusion area connected to the last stage of the CCD 2
The signal charge is converted into a voltage signal by the unit 3 and the signal processing circuit 4 coupled to the unit 3 and output. Floating diffusion region 3
Is a floating diffusion region FD and a reset gate (RG) adjacent to the FD for periodically resetting the potential of the FD to the potential of the reset drain (RD) by the reset signal RS.
And a source follower amplifier S for buffering the potential of the FD to a high input impedance / low output impedance
And an FA.

The signal processing circuit 4 includes a source follower amplifier SFA for generating an output signal corresponding to the signal charge of the CCD 2.
An output OS, a capacitor C1 coupled to the SFA, a buffer amplifier FTC coupled to the capacitor C1, an analog switch S1 for clamping coupled to a reference potential,
Switch S2 and capacitor C of sample and hold circuit
2, and a buffer amplifier CDS. The analog switch S1 is driven by a clamp pulse φFTC, and the switch S2 is driven by a sample and hold pulse φSAH.

The normal operation of transferring and outputting data of all pixels will be described with reference to the potential diagram of FIG. 3 and the operation timing waveform diagram of FIG.

At the time when the electric charge from the sensor 1 is transferred from the packet under the electrode φ1 to the packet under the electrode φ2 (fall of the φ1 pulse = rising of the φ2 pulse), the reset gate RG outputs a high level as a reset signal RS. To reset the potential of the floating diffusion region FD to the potential of the reset drain RD. Thereafter, when the potential of the reset signal RS is returned to a low level, the floating diffusion region FD is separated from the reset drain RD,
It becomes a floating state (FIG. 3A). The level of the signal OS at this time is a so-called feed-through level (F
edgethrough Level), which is the reference level of the CCD signal.

Thereafter, when φ1 rises and φ2 falls, the signal charge is transferred from the packet under the electrode φ2 to the packet under the electrode φ1, and the signal charge Q1 in the packet under the electrode φ2 at the final stage is It flows under the electrode OG into the floating diffusion region FD (FIG. 3B). In the floating diffusion region FD, the potential drops by the amount of the charge of Q1, which is the potential drop amount V from the feedthrough level of the output OS.
1 (FIG. 4).

In FIG. 3C, charges are transferred from the packet under the electrode φ1 to the packet under the electrode φ2.

Thereafter, when a high-level pulse is applied again to the reset signal RS, the potential of the floating diffusion region FD is reset to the level of the reset drain RD (FIG. 3).
(D)) Thereafter, this operation is repeated, and eventually the signal OS
, The operation of reset drain RD level → feedthrough level → signal level → RD level is repeated by the number of all pixels.

On the other hand, the effective signal component of the CCD 2 is the voltage of the difference between the feedthrough level and the signal level, and the CDS circuit 24 is mounted on the same chip to extract this difference component.
Is provided. The pulse φFTC maintains the low level during the period when the rising signal OS outputs the feedthrough level at the rising timing of the pulse RS.
The FTC circuit 23 conducts the analog switch S1 during the period when the pulse φFTC is at the high level, and clamps the output VFTC of the amplifier 21 at the time of feedthrough level output to the reference level.

When the signal OS drops from the feedthrough level by V1 corresponding to the signal potential, the output VFT of the amplifier 21
C will drop from the reference level by V1. While the signal OS is outputting the signal level, the pulse φSA
When the high level of H is input to the switch S2, the amplifier 21
The output voltage VFTC of the sample-hold circuit (S
2, C2) is sampled and held. As a result, an output obtained by holding the pixel output of the CCD for each pixel from the output VCDS of the amplifier 22 is obtained in a time series with reference to the analog reference voltage.

Next, a pixel mixing output for reducing image data according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows a solid-state imaging device according to an embodiment of the present invention, that is, a cross-sectional structure of a CCD of a line sensor, a signal output circuit, and a potential diagram for explaining a normal transfer output operation of the line sensor. FIG. 2 is a signal waveform diagram for explaining the operation timing of the pixel mixed output of the line sensor. The sectional structure and the circuit diagram of FIG. 1 are the same as those of FIG.

1 and 2 show a case where signals for two pixels are mixed to form one output signal. FIG.
In the operation sequence of (A) to (C), once the pulse RS
To reset the potential of the floating diffusion region FD to the potential of the reset drain RD. Subsequently, the charge Q1 is transferred to the floating diffusion region FD and the signal V1 is obtained as the output OS. This is exactly the same as the normal operation of C).

However, the pulse RS in FIG. 2 is obtained by thinning out the pulse RS in FIG. That is, one pulse RS is generated by two pulses φ2. This allows
In the floating diffusion region FD, the previous charge Q1 is transferred and the signal OS
And the state of outputting V1 is maintained. Therefore, the sum of the previous charge Q1 and the next transferred charge Q2 is transferred to the floating diffusion region FD (FIG. 1D), and V1 + V2, which is the sum of the two, is obtained as the output signal OS. As a result, this is equivalent to that an output obtained by mixing outputs of two pixels, that is, a pixel generating Q1 and a pixel generating Q2, is obtained as the OS.

Although the above is an example of two-pixel mixing, three or more pixels can be mixed in a similar manner. That is, by inputting the pulse RS every n pixels (n is a positive integer of 2 or more), an output in which n pixels are mixed is obtained. Accordingly, in the n-pixel mixing operation, an addition output of n pixels is obtained, so that the image data is simply sampled by a sensor having a coarse pixel pitch n times as large as that of the normal driving (FIGS. 3 and 4). Thus, the aperture effect can be reduced as compared with the case where data is sampled every n pixels.

The above description has been made with a focus on the CCD.
In the embodiment of the present invention, the processing of the CDS circuit 24 for this CCD output is also performed on the same semiconductor chip.
It is necessary to output pixel-mixed data as the output of the CDS circuit 24. That is, since the feedthrough level immediately after the pulse RS is clamped in the FTC circuit 23, it is necessary to thin out the pulse φFTC at the same time as thinning out the pulse RS. Otherwise, the pixel is reclamped during the V1 output period and a normal pixel mixed output cannot be obtained.

On the other hand, for the sample and hold circuit,
Pulse φSA only during the period when V1 + V2 is being output
H needs to be input to the switch S2. For this,
As is clear from FIG. 2, only the pulse φSAH just before the pulse RS is input needs to be left.

The pulse RS described above and the pulse φFT
FIG. 5 shows an example of a control circuit for variably controlling and outputting the cycle (thinning) of C and the pulse φSAH, and FIG. 6 shows an operation timing chart thereof.

The mode signals -MB0, -MB1,-in FIG.
MB2 represents the following operation modes.

[0031]

[Table 1]

FIG. 6A shows the AND circuit on the right side of FIG.
The signals RS0, φFTC0, and φSAH0 are input at the timings shown in FIGS. 6B to 6D, and the signals RS0, φFTC,
φSAH is output.

FIG. 6B shows output signals RS, φFTC, and φSAH in the two-pixel mixed mode.
The period is twice as long as the transfer pulses φ1 and φ2,
The charge of the pixel is mixed and output. The number of pixels is halved.

FIG. 6C shows output signals RS, .phi.FTC, and .phi.SAH in the four-pixel mixed mode.
The period is four times as long as the transfer pulses φ1 and φ2,
The charge of the pixel is mixed and output. The number of pixels is reduced to 1/4.

FIG. 6D shows output signals RS, .phi.FTC, and .phi.SAH in the eight-pixel mixed mode.
The period of the transfer pulses φ1 and φ2 is eight times,
The charge of the pixel is mixed and output. The number of pixels is reduced to 1/8.

The present embodiment is not limited to a line sensor, and can be applied to an area sensor in which photodiodes and CCDs are two-dimensionally arranged.

The present invention is not limited to the embodiments described above, and it will be apparent to those skilled in the art that various modifications and improvements can be made based on the disclosure of the embodiments.

[0038]

According to the present invention, it is possible to obtain a solid-state imaging device that suppresses the aperture effect in the case of data reading in which pixel data is reduced, and obtains image scanning data without deteriorating image quality. In addition, the pixel mixture substantially improves the sensitivity, and the sub-scanning time can be reduced. Also,
If the sampling pulse of the CDS circuit is thinned out in response to the thinning of the pulse RS, the processing of the CDS circuit can be performed even in the pixel mixing mode to ensure a high S / N.

[Brief description of the drawings]

FIG. 1 is a cross-sectional structure, a signal processing circuit diagram, and a potential diagram of a CCD unit of a line sensor according to an embodiment of the present invention.

FIG. 2 is a signal timing chart for explaining a pixel mixing operation of the line sensor according to the embodiment of FIG. 1;

FIG. 3 is a cross-sectional structure, a signal processing circuit diagram, and a potential diagram of a normal operation of the CCD unit of the line sensor according to the embodiment of the present invention.

FIG. 4 is a signal timing chart for explaining the operation of the line sensor of FIG. 3;

FIG. 5 is a circuit diagram of a control circuit according to the embodiment of the present invention.

FIG. 6 is an operation timing chart of the control circuit of FIG. 5; .

[Brief description of reference numerals]

 DESCRIPTION OF SYMBOLS 1 Photoelectric conversion part (sensor) 2 CCD (transfer register part) 3 Floating diffusion area part 4 Signal processing circuit

Claims (3)

[Claims] 1. A solid-state imaging device having a photoelectric conversion element array in which a plurality of photoelectric conversion elements that generate electric charges according to the amount of incident light are arranged, wherein the charge read from the photoelectric conversion element array is A transfer register for sequentially transferring and outputting; a floating diffusion region arranged adjacent to an output stage of the transfer register for detecting the transferred electric charge; and a potential of the floating diffusion region which is periodically changed according to a reset signal. Reset means for resetting to a predetermined voltage level; potential detecting means for coupling with the floating diffusion region to detect a potential of the floating diffusion region to generate an output signal; and the potential after being reset by the reset means. Clamping means for periodically clamping the output signal of the detecting means to a predetermined reference voltage level in accordance with a control signal; and the potential detecting means after being clamped by the clamping means. A clamp signal output means for outputting a change in the output signal of the stage as a change from the reference voltage level; a reset signal to the reset means; and a control signal to the clamp means, and A solid-state imaging device, wherein a signal and control means in which the period of the control signal is variable are formed on a common semiconductor substrate. 2. The sample and hold circuit further comprising: a sample and hold circuit for periodically sampling and holding an output of the clamp signal output means; and a sampling control circuit for changing a sampling cycle of the sample and hold circuit. 2. The solid-state imaging device according to claim 1, wherein the sampling control circuit and the sampling control circuit are formed on the common semiconductor substrate. 3. The method according to claim 2, wherein the reset signal, the control signal, and the sampling period are n times (n is a positive integer of 2 or more) a period of a transfer signal of the photoelectric conversion element array. 3. The solid-state imaging device according to 2.