JPH11331107A - Derandomizer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a derandomizer which is able to accelerate processing operation and can be inexpensively constituted. SOLUTION: For an 8-bit parallel M sequence generating circuit used for this derandomizer for generating M sequences (M is a natural number >=2) in parallel for 8 bits, since a generated polynomial h(x) is an 8th-order expression, shift registers 8-1 to 8-8 of eight stages are respectively provided corresponding to values u0 -u7 of ground vectors, and each time a clock is inputted, step operation is performed with α<8> as the 8th power of α so that M sequences can be generated in parallel for 8 bits. This 8-bit parallel derandomizer, composed of the 8-bit parallel M sequence generating circuit, is constituted as a symbol synchronizing circuit and inside a data receiver, after output signals (received signals) are in parallel/serially converted into 8-bit data, this device functions to perform EX-OR operation for each bit with respect to the 8-bit parallel M sequence output.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
Used for decoding error correction code (Reed-Solomon code) data with interleaving in a space communication system employing S, and a command signal receiving device mounted on an artificial satellite and a ground facility for receiving data from the artificial satellite The present invention relates to a derandomizer used for an observation data receiving device or the like.

[0002]

2. Description of the Related Art Conventionally, a data transmission system for space communication for transmitting observation data from an artificial satellite to a ground station by digital data has a configuration as shown in FIG. 5, and the data format used here is as follows. It follows certain rules according to the CCSDS AOS code format as shown in FIG.

[0003] This data transmission system comprises a transmission system mounted on an artificial satellite and a reception system installed on the ground. The transmission system includes an observation device 1 that performs required observations on celestial bodies and the surface of the earth and outputs the observation data as digital data, and a CCSDS
A data encoding device 2 that mod2 adds a coded signal coded according to an AOS code format and a pseudo-noise sequence and randomizes and outputs the same, and a data transmitter that converts a randomized signal into a transmission signal by radio wave and transmits the signal. 3 The receiving apparatus performs de-randomization to reproduce the original data packet by mod2 adding a received data sequence that has received a transmission signal by radio waves and a pseudo-noise sequence generated in the same phase as the pseudo-noise sequence. A data receiver 4 that outputs data according to the CCSDS AOS code format included in the received signal, and outputs the decoded observation data as digital data; And an observation data display device 6 for displaying.

In the CCSDS AOS code format, a set of a synchronization marker which is a synchronization word and encoded data is repeated. In the case of FIG. 6, the first part is a synchronization marker SYNC indicating the start of the code format. The subsequent portion is a Reed-Solomon encoded transfer frame and Reed-Solomon check symbol, which are Reed-Solomon encoded data of a transmission code block. Note that a pattern having a sharp autocorrelation is usually used for the synchronization word, but the data pattern may change randomly, and consecutive 1s and 0s also occur.

FIG. 7 illustrates a basic configuration of a symbol synchronization circuit (parallel de-randomizer) used in the data receiver 4. This symbol synchronization circuit is connected to an initialization terminal and a clock terminal, is given an initial value of 1, and generates an 8-bit parallel M-sequence (where M is a natural number of 2 or more) 8-bit parallel M-sequence generation circuit. 7-1 and an initial value of 2 connected to the clock terminal.
An 8-bit parallel M-sequence generating circuit 7-2 to 7-5 for generating an M-sequence (where M is a natural number of 2 or more) given an initial value of 5 and 8-bit parallel, and A data transition point from 1 to 0 or from 0 to 1 is detected from the data sequence of the received signal output from the, and works to synchronize with this. Each of the 8-bit parallel M-sequence generation circuits 7-1 to 7-5 has eight output terminals.

Here, when 1s and 0s continue, it is easy to imagine that the symbol error rate deteriorates due to a decrease in S / N in the loop of the symbol synchronization circuit. On the other hand, a randomizer is used in the data encoding device 2 of the transmission system in order to secure a constant data transition rate. The randomizer mod2 adds the data and the pseudo noise sequence. The pseudo-noise sequence includes an M-sequence that is easily generated (maximum long-period sequence / Maximum le).
nth shift register sequence
nce) is generally used. Incidentally, the CCSDS also employs the M-sequence, but the randomization is performed only on the data and not on the synchronization word.

Therefore, a case where randomization is performed on data will be described. For example, it is assumed that n-bit data d (vector) is represented by the following equation (1).

[0008]

(Equation 1) An initial value is determined for the M-sequence used for randomization, and the M-sequence starts from the initial value with the next data of the synchronization word. If the M sequence used for randomization is m (vector),
This m (vector) is represented by the following equation (2).

[0009]

(Equation 2) The d (vector) is randomized by adding m (vector) and mod2, and transmitted as r (vector). This r (vector) is represented by the following equation (3).

[0010]

(Equation 3) On the receiving side, an M-sequence is generated from the data following the detection of the synchronization word with the same initial value as on the transmitting side, and the received data and the M-sequence generated on the receiving side are mod2 added to perform randomization on the transmitting side. And the original data is obtained as r (vector) + m (vector) = (r ₀ + m
_{0 r 1 + m 1 r 2} + m 2 r 3 + m 3 ... r n- 1 + m n-1)
= (D ₀ + m ₀ + m ₀ d ₁ + m ₁ + m ₁ d ₂ + m ₂ + m
₂ d ₃ + m ₃ + m ₃ ... D _n-1 + m _n-1 ) = (d ₀ d ₁ d
_{2 d 3 ... d n-1} ) = obtain d (vector). Incidentally, the operation of returning the randomized data to the original data (that is, reproduction to the original data) is called derandomization.

The characteristics of the M-sequence can be represented by a generator polynomial h (x). The generator polynomial h (x) that generates the M-sequence is a primitive polynomial.
Assuming that the root is α, h (x) = h _i x ⁱ + h _i−1 x ⁱ⁻¹
+ H _i-2 x ^i-2 + h _i-3 x ^i-3 + ... + h ₂ x ² + h ₁
In the relationship x + h _0, the period of the M sequence of α (2 ⁱ −
1) The zeroth power of the root α is equal to the power. When the initial value is α ^k , the generation of the M sequence is performed by sequentially multiplying the root α. When the initial value α ^k is multiplied by the root α 2 ⁱ −1 times, the value returns to the initial value α ^k again. For the power α ^{j of the} root α, a basis vector expression is often used. That is, the power α ^{j of the} root α is expressed as in the following Expression 4.

[0012]

(Equation 4) The circuit for multiplying the power α ^j of the root α by the root α is usually I
It is composed of a stage shift register and several EX-OR circuits.
c Coding Theory "ElwynR. B
erlekamp 1968 McGraw-Hill
The details are described in, for example.

Next, the CCSDS randomizer will be described. The generator polynomial h (x) of the CCSDS randomizer is given by:
h (x) = is represented by ^{x 8 + x 7 + x 5} + x 3 +1 becomes relevant. Since the generator polynomial h (x) is an eighth-order equation of x, the period of the M sequence is 255. Generator polynomial h (x)
FIGS. 8 to 13 show an example in which the root of is represented by α and α ⁰ to α ²⁵⁴ are displayed by base vectors.

FIG. 14 shows an M-sequence generating circuit for multiplying a root α described in a known document or the like. Since the generator polynomial h (x) is an eighth-order equation, the M-sequence generating circuit The circuit requires eight stages of shift registers 8-1 to 8-8, and the root α can be multiplied every time a clock is input.

In contrast to the display by the basis vectors shown in FIGS. 8 to 13, the first shift register 8-1 has u
₀ , the second shift register 8-2 is u ₁ , the third shift register 8-3 is u ₂ , the fourth shift register 8-4 is u ₃ , the fifth shift register 8-5 is u ₄ , The sixth shift register 8-6 is u ₅ , the seventh shift register 8-7
Corresponds to the value of u ₆ , and the eighth shift register 8-8 corresponds to the value of u ₇ . In CCSDS, the first 8 bits are determined to be followed by 1. Since the randomizer output uses the output of the eighth shift register 8-8, the M-sequence output by the randomizer is as shown in FIG.

Here, since it is convenient to output a specified initial value, M-sequence generation is performed using a circuit as shown in FIG. In this M-sequence generation circuit, the eight-stage shift registers 8-1 to 8-8 are configured to be linear feedback shift registration circuits, but the operation in this case is different from that shown in FIG.

That is, in the case of the circuit shown in FIG. 14, an operation for multiplying the root α is performed, and a value at a certain time is v (vector) = (ν ₇ ν ₆ ν ₅ ν ₄ ν ₃ ν ₂ ν ₁ ν ₀ ), the operation can be expressed as in the following Expression 5.

[0018]

(Equation 5) On the other hand, in the case of the circuit shown in FIG. 16, the operation is represented by the following equation (6).

[0019]

(Equation 6) In CCCDS, a Reed-Solomon code is adopted as an error correction code, and the circuit shown in FIG. 16 is used because an initial value is easily set. The Reed-Solomon code is a strong error correction code against burst errors, but employs interleaving to further improve burst error correction performance.

The interleaving of CCSDS is CCSDS.
The specifications describe the details of the technical contents, and the basic outline is shown in FIG. However, this outline does not show the actual circuit configuration as described in the CCSDS specification, but as a result of interleaving, RS (Reed-Solomon) encoders # 1 to #I are connected between the input side and the output side. Only the functions selected by the switches S1 and S2 are required.

FIG. 18 illustrates the relationship between the result of interleaving at depth 5 and Reed-Solomon encoding.
In FIG. 18, each block in the area E1 in the information data indicates I0 to I6, and each block in the area E2 is I1094 to I1099, and the area E1 in the interleaved Reed-Solomon check symbol is indicated.
3 indicates that the blocks are C0 to C5 and the blocks in the area E4 are C154 to C159.

The transmitting apparatus transmits a randomized transmission signal after the interleaving and Reed-Solomon encoding by the data encoding apparatus 2, while the receiving apparatus demultiplexes the transmission signal received by the data receiver 4. Randomize.

FIG. 19 is a block diagram showing a detailed configuration of the derandomizing decoding circuit provided in the data receiver 4. In this derandomizing decoding circuit, a derandomizer 9 is provided on the input side, and a demultiplexer 10 connected to the derandomizer 9, a multiplexer 12 on the output side, and a demultiplexer 10 and the multiplexer 12 are provided. It is provided with I (where I is a natural number of 5 or more) decoders 11-1 to 11-I.

In this de-randomizing decoding circuit, a de-randomizer 9 performs bit-wise processing on an output (received signal) of the data receiver 4 input from an input terminal, and a demultiplexer 10 serializes / de-randomizes the de-randomized output. Parallel (S / P) conversion and decoding by decoders 11-1 to 11-I
Transmit to The decoders 11-1 to 11-I transmit decoded signals resulting from the decoding to the multiplexer 12, and the multiplexer 12 outputs received signals generated by performing parallel / serial (P / S) conversion of the decoded signals to the output terminal. Output.

By the way, the data transmission system described above,
A case has been described in which de-randomization for receiving and reproducing the digital data (packet), which is randomized and transmitted from the transmitting system device mounted on the satellite to the receiving system device installed on the ground, as the original data has been described. Conversely, de-randomization for receiving and reproducing command digital data (packets), which is randomized from a transmission device installed on the ground to a reception device mounted on a satellite and transmitted, as original data. The same can be applied to a data transmission system in the case of performing.

[0026]

In the case of the data transmission system described above, the Reed-Solomon code of the CCSDS to be subjected to Reed-Solomon coding in the transmission system device is GF (2 ⁸ ).
On the other hand, in the receiving apparatus, the decoding processing speed is interleaved as a pipeline configuration in order to improve the decoding speed by performing a parallel operation for decoding the Reed-Solomon encoded data in 8-bit units. The depth can be improved.

However, in the de-randomizing decoding circuit provided in the data receiver of the receiving system, the de-randomizer performs bit-wise processing, and the other parts perform decoding after serial / parallel conversion of the de-randomizing output. High speed processing is required for the processing operation of the de-randomizer, and there is a problem that high-speed components are required in addition to serial / parallel conversion and parallel / serial conversion, and the data receiver itself becomes expensive.

The present invention has been made in order to solve such a problem, and a technical problem thereof is to provide a derandomizer which can speed up a processing operation and can be configured easily.

[0029]

According to the present invention, in order to ensure a data transition rate from a transmitting system device provided on a satellite and installed on the ground to a receiving system device, the present invention has been made in view of the present invention. In a de-randomizer for performing randomization for receiving and reproducing digital data transmitted after being randomized and transmitted as original data, the randomization includes a pseudo-noise sequence and an encoded digital data.
The data transition rate is secured by adding od2,
In the derandomization, a derandomizer that reproduces the original data in the same phase as the pseudo-noise sequence at the time of reception at the same phase, and mod2 adds the received data sequence to make it suitable for non-binary coding is obtained.

On the other hand, according to the present invention, the transmission system is provided in the reception system installed on the ground, and is transmitted in a randomized manner from the transmission system installed on the satellite to the reception system in order to secure the data transition rate. In a de-randomizer that performs de-randomization for receiving and reproducing the converted digital data as original data, in the randomization, a data transition rate is secured by mod2 adding a pseudo-noise sequence and an encoded digital data. In the derandomization, when the reproduction of the original data is received, the same sequence as the pseudo-noise sequence is generated at the same phase at the time of reception, and the received data sequence is mo.
A de-randomizer is obtained that performs d2 addition and is suitable for non-binary coding.

Further, according to the present invention, in any of the above-mentioned de-randomizers, a de-randomizer in which the non-binary coding is Reed-Solomon coding is obtained.

Further, according to the present invention, in any one of the above-described de-randomizers, the generation of the same sequence as the pseudo-noise sequence is based on the generation of an M sequence (where M is a natural number of 2 or more) in 8-bit parallel. As a result, a de-randomizer including a symbol synchronization circuit including a predetermined number of 8-bit parallel M-sequence generation circuits to be performed by an octuple step operation is obtained.

In addition, according to the present invention, in the above-mentioned de-randomizer, Reed-Solomon encoding involves interleaving at a depth of 5 and generates M sequences (8-bit parallel) to generate the same sequence as the pseudo-noise sequence. However, a de-randomizer including a symbol synchronization circuit including a predetermined number of 8-bit parallel M-sequence generation circuits for performing generation by a step operation with the root raised to the 40th power is obtained.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The following is a description of embodiments of the present invention, with reference to the accompanying drawings. However, the de-randomizer here is also provided as a symbol synchronization circuit in the data receiver 4 of the receiving system device of the data transmission system in the same manner as described in FIG. 7, and is installed on the ground from the transmitting system device mounted on the satellite. It is assumed that digital data that has been randomized and transmitted to the receiving system device to be transmitted is converted into original data and then de-randomized to receive and reproduce the digital data.

This de-randomizer converts a pseudo-noise sequence and digital data encoded by randomization into m
When the data transition rate is secured by the addition of od2, when the reproduction of the original data (packet) by the derandomization is received, the same sequence as the pseudo-noise sequence generated in the same phase and the received data sequence are added by the mod2. This is performed so as to be suitable for non-binary coding. Here, the non-binary coding may be Reed-Solomon coding.

That is, since the Reed-Solomon decoding operation in the data receiver 4 is a parallel operation in units of 8 bits, if an M sequence can be generated in parallel, derandomization can be performed efficiently and at high speed. 1 occurrence of M-sequence
To advance the state bit by bit is to advance the state in steps of the root α. In order to advance the M-sequence generation in 8-bit parallel, an arithmetic operation of α ⁸ steps in which the root α is raised to the eighth power is performed instead of the root α. The value at a certain point is represented by v (vector) = (ν ₇
ν ₆ ν ₅ ν ₄ ν ₃ ν ₂ ν ₁ ν ₀ ), and the calculation of the α ⁸ step is obtained by the same method as the calculation of the above-described equation (6) in the relationship represented by the following equation (7). .

[0037]

(Equation 7) FIG. 1 shows an 8-bit parallel M-sequence generation circuit used in a de-randomizer according to one embodiment of the present invention. Also in this 8-bit parallel M-sequence generation circuit, since the generation polynomial h (x) is an eight-order expression, eight stages of shift registers 8-1 to 8-8 are required. And the root α is raised to the eighth power. A step calculation is performed using α ⁸ to generate an M sequence in 8-bit parallel.

In contrast to the display using the basis vectors shown in FIGS. 8 to 13, the first shift register 8-1 has u
₀ , the second shift register 8-2 is u ₁ , the third shift register 8-3 is u ₂ , the fourth shift register 8-4 is u ₃ , the fifth shift register 8-5 is u ₄ , The sixth shift register 8-6 is u ₅ , the seventh shift register 8-7
Corresponds to the value of u ₆ , and the eighth shift register 8-8 corresponds to the value of u ₇ .

The 8-bit parallel de-randomizer based on the 8-bit parallel M-sequence generation circuit has the same configuration as that of the symbol synchronization circuit shown in FIG.
In the function, the output signal (received signal) is converted into 8-bit data in parallel / serial in the data receiver 4, and then the EX-OR is output for each bit with respect to the 8-bit parallel M-sequence output.
Perform the operation.

Next, de-randomization with interleaving will be described. FIG. 2 illustrates the relationship between the de-randomizer in the data receiver 4 and interleaving at a depth of 5, and FIG. 3 is a block diagram showing a detailed configuration of a de-randomizing decoding circuit provided in the data receiver 4 in this case. It is.

Referring to FIG. 3, the de-randomizing decoding circuit is configured to perform de-randomizing-deinterleaving-Reed-Solomon decoding, and is inputted from an input terminal by a serial / parallel (S / P) converter 13. After the output signal (reception signal) of the data receiver 4 is parallelized by 8 bits by serial / parallel conversion, the demultiplexer 10 sends 1-bit signals to the 8-bit parallel addition circuits 14-1 to 14-5 every 8 bits.
8-bit parallel M-sequence generating circuit 7-to-1 connected
Circulation distribution to the derandomizer 9 comprising 1-7-5.
The data that has been de-randomized by the de-randomizer 9 is subjected to Reed-Solomon decoding by the decoders 11-1 to 11-5, respectively, and then is subjected to parallel / serial (P
/ S) is cyclically selected and output to the output terminal as a reception signal generated by the conversion.

Since the de-randomizer 9 involves interleaving at a depth of 5, the 8-bit parallel M-sequence generating circuits 7-1 to 7-5 perform α ^{8 × I} = α ^{8 × 5} = α ^40- step operations. There is a need to do. Assuming that the value at a certain point in time is v (vector) = (ν ₇ ν ₆ ν ₅ ν ₄ ν ₃ ν ₂ ν ₁ ν ₀ ), the α ⁴⁰ step operation is obtained by the relationship expressed by the following equation (8). .

[0043]

(Equation 8) FIG. 4 exemplifies a corresponding 8-bit parallel M-sequence generation circuit. The initial value of the 8-bit parallel M-sequence generation circuit 7-1 shown in FIG. 3 is "11111111", and the initial value is 811. The initial values of the generation circuit 7-2 are "01001000", 8
The initial value of the bit parallel M-sequence generation circuit 7-3 is “00”.
001110 ", 8-bit parallel M-sequence generator 7-
4 is "11000000", and the initial value of the 8-bit parallel M-sequence generator 7-5 is "10011010".
And each of the 8-bit parallel M-sequence generating circuits 7
In steps -1 to 7-5, every time a clock is input, an α ⁴⁰ step calculation is performed.

That is, after the initial value is set, the value of the 8-bit parallel M-sequence generating circuit 7-1 is "000010110", the value of the 8-bit parallel M-sequence generating circuit 7-2 is "01110000" by the first clock input. The value of the 8-bit parallel M-sequence generation circuit 7-3 is "10111100",
The value of the 8-bit parallel M sequence generation circuit 7-4 is "100
01110 ″, 8-bit parallel M-sequence generation circuit 7-5
Value "00101100", and the value of each 8-bit parallel M-sequence generation circuit 7-1 to 7-5 proceeds by alpha ⁴⁰ step.

Further, the value of the 8-bit parallel M-sequence generation circuit 7-1 is changed to "1001001" by the next clock input.
1 ", the value of the 8-bit parallel M-sequence generator 7-2 is" 10101101 ", the value of the 8-bit parallel M-sequence generator 7-3 is" 10100111 ", and the value of the 8-bit parallel M-sequence generator 7-4 is “10110111”,
The value of the 8-bit parallel M-sequence generation circuit 7-5 is "010
00110 ", and the values of the respective 8-bit parallel M-sequence generating circuits 7-1 to 7-5 further advance by α ⁴⁰ steps.

By the three steps described above, a 120-bit M-sequence was generated. Similarly, this circuit performs an M-sequence generation operation of α ⁴⁰ steps at each clock input, generates an M-sequence by 40 bits, and performs derandomization. By performing such derandomization, the processing operation in the derandomization decoding circuit can be speeded up, and the derandomization decoding circuit and the data receiver 4 can be simply configured.

Note that the data transmission system here also receives and reproduces observation digital data (packets) transmitted by being randomized from a transmission system mounted on a satellite to a reception system installed on the ground as original data. However, in contrast to this, command digital data (packets) randomized and transmitted from a transmitting system installed on the ground to a receiving system mounted on a satellite have been described above. The present invention can be similarly applied to a data transmission system in the case of performing derandomization for receiving and reproducing data.

[0048]

As described above, according to the de-randomizer of the present invention, the pseudo-noise sequence and the digital data encoded by randomization are added by mod2 to obtain the data transition rate under the condition that the data transition rate is secured. Since the reproduction of the original data by de-randomization is the same as the pseudo-noise sequence generated at the time of reception, and the received data sequence is mod2 added and de-randomizing is performed so as to be suitable for non-binary encoding. The processing operation in the de-randomizing decoding circuit can be speeded up, and the de-randomizing decoding circuit and the data receiver can be simplified and configured at low cost.

[Brief description of the drawings]

FIG. 1 shows an 8-bit parallel M-sequence generation circuit used in a de-randomizer according to one embodiment of the present invention.

FIG. 2 illustrates a relationship between the de-randomizer described in FIG. 1 and interleaving at a depth of 5 in the data receiver.

FIG. 3 is a block diagram showing a detailed configuration of a derandomizing decoding circuit provided in the data receiver in the case of FIG. 2;

FIG. 4 shows an 8-bit parallel M-sequence generation circuit used for a de-randomizer in the de-randomization decoding circuit shown in FIG. 3;

FIG. 5 is a block diagram showing a basic configuration of a data transmission system as an example of a conventional space communication system.

FIG. 6 shows C used in the data transmission system shown in FIG.
It illustrates the CSDS AOS code format.

FIG. 7 illustrates a basic configuration of a symbol synchronization circuit (parallel de-randomizer) used in the data receiver of the data transmission system shown in FIG.

FIG. 8 illustrates a first local part in a case where a generator polynomial of an existing CCSDS randomizer is represented by a basis vector having an M-sequence period of 255.

FIG. 9 illustrates a second local area following the case of FIG. 8;

FIG. 10 illustrates a third local area subsequent to FIG. 9 in the case of FIG. 8;

FIG. 11 illustrates a fourth local area following FIG. 10 in the case of FIG. 8;

FIG. 12 illustrates a fifth local area subsequent to FIG. 11 in the case of FIG. 8;

FIG. 13 illustrates a sixth local area subsequent to FIG. 12 in the case of FIG. 8;

FIG. 14 illustrates an example of an M-sequence generation circuit using a shift register used in the operations (multiplications) of FIGS. 8 to 13;

FIG. 15 illustrates an M-sequence of a randomizer output in the M-sequence generation circuit illustrated in FIG. 14;

FIG. 16 shows another example of an M-sequence generation circuit using a shift register used in the calculations (multiplications) of FIGS. 8 to 13.

FIG. 17 shows a basic overview of existing CCSDS interleaving.

FIG. 18 illustrates the relationship between depth 5 interleaving results and Reed-Solomon coding according to the existing basic overview.

19 is a block diagram showing a detailed configuration of a derandomizing decoding circuit provided in the data receiver of the data transmission system shown in FIG.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 observation device 2 data encoding device 3 data transmitter 4 data receiver 5 data decoding device 6 observation data display device 7-1 to 7-5 8-bit parallel M-sequence generation circuit 8-1 to 8-8 shift register 9 data Randomizer 10 Demultiplexer 11-1 to 11-5, 11-I Decoder 12 Multiplexer 13 Serial / Parallel (S / P) Converter 14-1 to 14-5 8-bit parallel addition circuit

Claims (5)

[Claims] 1. A digital signal provided in a receiving system mounted on a satellite, which is randomized in order to secure a data transition rate from a transmitting system installed on the ground to the receiving system and transmitted. In a de-randomizer that performs de-randomization for receiving and reproducing data, the randomization ensures the data transition rate by mod2 adding a pseudo-noise sequence and an encoded version of the digital data, In the derandomizing, the reproduction of the original data is performed at the time of reception by generating the same sequence as the pseudo-noise sequence in the same phase and by mod2 adding the received data sequence to be suitable for non-binary encoding. Derandomizer. 2. The digital data provided in a receiving system installed on the ground and transmitted by randomization in order to secure a data transition rate from a transmitting system mounted on a satellite to the receiving system. In a de-randomizer that performs de-randomization for receiving and reproducing data, the randomization ensures the data transition rate by mod2 adding a pseudo-noise sequence and an encoded version of the digital data, In the derandomizing, the reproduction of the original data is performed at the time of reception by generating the same sequence as the pseudo-noise sequence in the same phase and by mod2 adding the received data sequence to be suitable for non-binary encoding. Derandomizer. 3. The de-randomizer according to claim 1, wherein the non-binary coding is Reed-Solomon coding. 4. The de-randomizer according to claim 1, wherein, as the generation of the same sequence as the pseudo-noise sequence, an M-sequence is generated in 8-bit parallel (where M is a natural number of 2 or more). And a symbol synchronization circuit including a predetermined number of 8-bit parallel M-sequence generation circuits for performing a step operation with a root raised to the eighth power. 5. The de-randomizer according to claim 3, wherein the Reed-Solomon encoding involves interleaving at a depth of 5, and generates M-sequences (8-bit parallel) as the same sequence as the pseudo-noise sequence. , M is a natural number of 2 or more). A de-randomizer comprising a symbol synchronization circuit including a predetermined number of 8-bit parallel M-sequence generation circuits for performing generation by a step operation with a root raised to the 40th power.