JPH11330913A - Digital filter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To actualize a digital filter of a simple constitution which is used suitably for a spread spectrum radio communication device and which removes unnecessary sidebands of a digital signal. SOLUTION: An FIR type digital filter 11 has desired low-pass filter characteristics by oversampling with interpolated data between actual data. The filter has the number of taps limited when a roll-off rate is not 0, namely, when ideal filter characteristics are not obtained while characteristics of impulse response of a roll-off filter are considered, and realizes a coefficient multiplying processing by a shifter S which obtains a partial coefficient by decomposing a coefficient and an adder K which adds the output of the shifter. Thus, a multiplying processing can be realized by the shifter and adder of a relatively simple constitution and the roll-off filter is provided with the minimum number of taps to reduce the circuit scale.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital filter suitably implemented in data communication and the like, and more particularly to a roll-off filter capable of realizing a Nyquist filter capable of eliminating intersymbol interference due to transmission and the like.

[0002]

2. Description of the Related Art It is generally known that a digital signal has a spectrum spread over a much wider range than a data rate. For example, the data rate of a digital signal as shown in FIG.
When s), the spectrum is spread as shown in FIG.

[0003] On the other hand, in transmitting digital signals such as images and sounds, usable frequency bandwidths are finely divided according to applications and purposes. Therefore, in order to transmit a large amount of information in a limited frequency band, it is necessary to improve the data transfer rate or narrow a signal of a predetermined data transfer rate and multiplex some data by frequency division. Can be considered. In particular, in the field of wireless communication, it is effective to suppress unnecessary sidebands of a baseband signal and narrow the band in order to improve the efficiency of use of radio resources.

[0004] However, when the spectrum of the digital signal is narrowed, there is a possibility that interference between codes occurs and a bit error occurs. Therefore, a Nyquist filter is widely used as a filter that does not cause intersymbol interference while narrowing the band.

The characteristics of the roll-off filter R (f) provided by Nyquist and realizing the Nyquist filter without intersymbol interference are shown by the following equation and FIG.

[0006]

(Equation 1)

Here, T is a code interval, and α is 0 ≦ α.
It is a roll-off rate taking a value of ≦ 1. The roll-off filter R (f) is well known as a type of filter that realizes the function of a Nyquist filter, and in the following description, the Nyquist filter will be expressed as a roll-off filter.

In FIG. 11, W is a transition period, and when the ideal filter characteristic is α = 0, the transition period W becomes 0. As the roll-off rate α increases, the transition period W also increases. growing. In FIG. 11, the roll-off rate α
Indicates a transition period when is 0.5.

As shown in FIG. 11, a unit code interval 1
Completing the code transitions within T gives
In (b), even if there is an interference wave shown by a broken line, data shown by a solid line, that is, code data shown in FIG. 12A is reproduced from the read data read at a predetermined reading point shown by a circle. And a filter characteristic for realizing a transmission path free of intersymbol interference can be realized.

The impulse response r (t) of the roll-off filter R (f) is

[0011]

(Equation 2)

## EQU1 ## When a random impulse train δn (n = ..., -1, 0, 1, ...) having positive and negative polarities is given to such a roll-off filter R (f), the output becomes

[0013]

(Equation 3)

Is obtained.

In order to realize such filter characteristics using analog elements such as L, C, and R, an advanced design using a computer is required. However, the filter characteristics are not limited to the Nyquist filters but are widely used. (Finite Impulse Response) using delay circuit with tap
A digital filter called a filter or a non-recursive filter can be realized relatively easily.

FIG. 13 is a block diagram showing the electrical configuration of a typical prior art digital filter 1 of the FIR type. As shown in FIG. 13, a general FIR type digital filter is composed of a cascade-connected multi-stage delay device d.
, Dn, and multipliers g0, g1,.
And an adder circuit 2. Input signal x
(N) is sequentially delayed by each of the delay units d1 to dn,
Using the input and output of each of the delay units d1 to dn as taps, the data at each tap is multiplied by coefficients h0 to hn by multipliers g0 to gn, and the multiplication results are added by an adder 2 to obtain an output signal y (N) is obtained.

The adder circuit 2 includes two multipliers g0 and g1;
g2, g3; ...; adders k11, k12, ..., k1m for mutually adding outputs from g (n-1), gn; and two adders k11, k12; ...; k1 (m-1), k1m
, And k2j for sequentially adding the outputs of.

[0018]

In the digital filter 1 as described above, as the number of taps n increases, better filter characteristics can be obtained. However, when the number of taps n is increased, the delay units d1 to dn and the adder k
There is a problem that the circuit scale is increased with the increase of the multipliers g0 to gn which occupy a large proportion in the mounting space as well as the increase of 11 to k1m; k21 to k2j.

On the other hand, wireless communication, in particular, has many advantages such as confidentiality, data transmission capacity, and transmission power. In spread spectrum communication, which has attracted attention in recent years, modulation processing for adding a spread signal to a transmission signal and reception have been performed. A lot of digital signal processing such as demodulation processing for removing a spread signal from a signal is required.

For this reason, when used as a wireless unit for a personal computer for performing the spread spectrum communication or as a communication unit of a portable device, it is possible to reduce the circuit scale and to reduce the mounting space, cost and power consumption. There is a strong demand for a reduction in the number of parts used. Also,
Even when the integration of each circuit element is promoted for the purpose of miniaturization, it is advantageous to configure the circuit with as few circuits as possible from the viewpoint of shortening the development period and reducing the development cost.

An object of the present invention is to provide a digital filter having a simple configuration, which can reduce the number of parts, cost, power consumption, development period, and the like.

[0022]

According to a first aspect of the present invention, there is provided a digital filter in which a plurality of delay means having taps are connected in cascade, an output from each tap is multiplied by a predetermined coefficient, and then added to each other. In a non-recursive digital filter for obtaining interpolated samples, if the roll-off rate is not 0, the multiplication of the coefficients is realized by a shifter and an adding means.

According to the above arrangement, in the non-recursive (FIR) type digital filter, when the data obtained by the calculation is inserted between the actual data at each code interval T as an interpolation sample, the roll-off rate becomes zero. In other words, if it is not the ideal filter characteristic, first, a coefficient to be multiplied by the input data, that is, a desired oversample can be realized, and the sampling period t / T (t (t : Sampling period, T:
Code interval), for example, ± 0.5, ± 1.5... In the case of double oversampling, ± 0.33, ± 0.67, ± 1.33, ± 1.3. 67 ...
Is obtained from the impulse response characteristics of the roll-off filter shown in FIG. Next, input data is shifted by a shifter that performs a shift operation with a shift amount corresponding to each partial coefficient obtained by decomposing the coefficient, and an output from each shifter is added by an adding unit.
Create the interpolated sample. For example, when multiplying by a coefficient of 0.75, the input data is obtained by adding the data equivalent to 0.5 shifted by 1 bit to the LSB side and the data equivalent to 0.25 shifted by 2 bits to the LSB side. , To obtain data multiplied by the desired coefficient of 0.75.

Therefore, a multiplier having a complicated configuration is not required, and the configuration of the coefficient multiplying circuit can be greatly simplified. This makes it possible to reduce the number of components, cost, power consumption, development period, and the like, and can be suitably used in a data communication device using spread spectrum communication.

In the digital filter according to the second aspect of the present invention, a delay means with taps is cascade-connected in a plurality of stages, an output from each tap is multiplied by a predetermined coefficient, and then added to each other to obtain an interpolation sample. In the non-recursive digital filter that obtains the following equation, the number of taps is limited based on the level of an impulse response corresponding to a desired roll-off rate.

According to the above configuration, as is apparent from the impulse response characteristics of the roll-off filter shown in FIG. 4, when the roll-off rate α is other than 0, the impulse is increased when t / T is increased to some extent. The response is converging. For example, when α = 1.0, that is, when the transition region W in FIG. 11 is the widest and the impulse response is the slowest,
It converges at about /T=1.5. Therefore, in this case, there are only four taps of ± 0.5 and ± 1.5, and a required filtering characteristic can be obtained with a minimum configuration.

Still further, a digital filter according to the invention of claim 3 is characterized in that the number of taps is limited to t / T of ± 4.

According to the above configuration, as shown in FIG. 4, if the roll-off rate α is a value other than 0, the impulse response converges to almost t / T = 4 at an arbitrary value. Thus, even when the roll-off rate α is small, filtering can be performed without any practical problem.

In the digital filter according to the fourth aspect of the present invention, in realizing a low-pass filter, the shift amount and the number of shifts of two bits or more between the shifter for the positive coefficient and the shifter for the negative coefficient are determined. It is characterized by being equal to each other.

According to the above configuration, the minute coefficient becomes equal to each other on the positive coefficient side and the negative coefficient side, and even if the coefficient is truncated by a predetermined bit, the DC component included in the input data is reduced. A low-pass filter that can be stored accurately and has a response characteristic from a DC region can be realized.

Further, the digital filter according to the invention of claim 5 is characterized in that tap outputs multiplied by mutually equal coefficients are added to each other by adding means and then shifted by a shifter. .

According to the above configuration, the number of shifters can be reduced to almost half by utilizing the symmetry of the tap coefficients.

Further, the digital filter according to the invention of claim 6 is characterized in that the addition process is performed between coefficients of different signs.

According to the above configuration, it is possible to suppress the occurrence of overflow during the calculation and obtain an error-free output in which the addition result is correctly stored.

Usually, the multiplication of the negative coefficient is performed by inverting the polarity of all the bits of the data of the positive coefficient using a two's complementer and then adding "1". In the present invention, the addition of the negative coefficient component and the positive coefficient by the adder is performed by adding the coefficient of the opposite sign between the obtained negative coefficient and another positive coefficient. Is realized by adding

Therefore, an adder such as the complementer is not required, and the configuration can be simplified.

[0037]

FIG. 1 is a block diagram showing an electric configuration of a digital filter 11 according to an embodiment of the present invention. FIG. 2 is a block diagram for explaining a basic concept of the digital filter 11. FIG. 3 is a diagram for explaining the operation of the digital filter 11.

According to the present invention, pulses..., A (n−1), which are actual input data obtained by sampling the input signal X (n) at predetermined code intervals T indicated by ○ in FIG.
From A (n), A (n + 1), A (n + 2),... (Referred to by a reference numeral A when collectively referred to), pulses P, B (n),... (Indicated by the symbol B), and interpolate the pulse B between the pulses A to perform double oversampling to realize a low-pass filter operation.

FIG. 3 is a timing chart for explaining the state of interpolation. A (n) indicates the current level of the input pulse, and A (n-1) indicates one sample period (= 1
T (T: 1 code interval) represents the level of the input pulse before, and A (n + 1) and A (n + 2) represent the level of the input pulse preceding by one sample period and two sample periods, respectively.

In this example, as will be described later, the interpolation pulse B (n) is provided at an intermediate point between the timings n and n + 1 at two points before and after the interpolation point (a total of four samples) of the input pulse A (n + 2). ), A (n + 1); A (n), A (n
Approximation is performed by convolving the impulse response according to -1).

FIG. 4 shows the impulse response r (t) obtained by changing the roll-off rate α in accordance with the above equation 2 from the filter characteristics without intersymbol interference previously given by Nyquist.
6 is a graph showing a calculation result of the calculation. The vertical axis represents the level of the impulse response, that is, the coefficient, and the horizontal axis represents the sampling period t normalized by the code interval T.

First, a desired roll-off rate α for the digital filter 11 is determined. Note that, for the sake of simplicity, in this example, the description will be made with α = 0.5. However, in the present invention, any value other than α = 0 may be selected. Next, a desired multiple of oversampling is determined. Again, in this example, double oversampling is used for simplification of the description. However, it is needless to say that the order may be higher than three times.

In the case of the double oversampling, when the sampling period t is normalized (t / T) by the code interval T, it becomes 0.5. Therefore, interpolation of t / T = 0.5, 1.5, 2.5,... Between the pulses A of t / T = 0, 1, 2,... Obtained by the actual data of the input signal X (n). The pulse B is inserted. Further, since the impulse response r (t) has a temporally symmetric relationship, t / T
= ± 0.5, ± 1, ± 1.5,..., The level of the impulse response r (t) is the same. In this example, at α = 0.5, since the convergence is almost completed at t / T = ± 2 or more, the interpolation pulse B (n)
Is input pulse A (n +
2), A (n + 1); A (n), A (n-1) are approximated by convolving the impulse response components.

That is, a coefficient for multiplying the data of the input pulse A (n + 2) is H1, a coefficient for multiplying the data of the input pulse A (n + 1) is H2, a coefficient for multiplying the data of the input pulse A (n) is H3, Assuming that the coefficient by which the data of the input pulse A (n-1) is multiplied is H4, B (n) = H1 * A (n + 2) + H2 * A (n + 1) + H3 * A (n) + H4 * A (n-1) … (4)

For example, in the case where triple oversampling is performed, two interpolation pulses B (na) and B (n)
b), the interpolation pulse B (na) is calculated as t / T = ±
The level of the impulse response at 0.33 is represented by the coefficient H2
a, H3a, and the level of the impulse response at t / T = ± 1.33 as coefficients H1a, H4a, and the input pulses A (n + 2), A (n + 1); A (n), A (n
-1), and the interpolation pulse B (nb) is calculated as t /
The input pulse A (n + 2), A (n + 1), where the levels of the impulse response at T = ± 0.67 are coefficients H2b and H3b, and the levels of the impulse response at t / T = ± 1.67 are coefficients H1b and H4b. A (n), A
What is necessary is just to multiply (n-1) and obtain it.

Further, in the case of 4 times oversampling, t / T = ± 0.25 ± 0.5, ± 0.75;
The level of the impulse response in ± 1.25, ± 1.5,... May be used as a coefficient. When the roll-off rate α becomes a small value of about 0.3, for example, in the double oversampling, as shown in FIG. 4, t / T = ± 2.5 and t / T = ± 3.5. The convolution may be added by using the level of the impulse response at the timing (1) as a coefficient.

In this embodiment, as described later, in order to obtain the interpolation pulse B (n) with the minimum circuit configuration, the coefficient H1 (= H4) and the coefficient H2 (= H3) are obtained from FIG. Choose -0.078125 and 0.578125, which approximates the resulting values -0.11 and -0.58. These coefficients H1. H2 is decomposed into H1 = −0.078125 = −0.0625 + (− 0.015625) (5) H2 = 0.578125 = 0.5 + 0.0625 + 0.015625 (6) Coefficient multiplication is realized by a shifter that shifts input data to the LSB (Least Significant Bit) side. That is, 0.5, 0.0625,
Each of the partial coefficients of 0.015625 is 1 bit, 4 bits,
Bit, obtained with a 6-bit shifter.

That is, referring to FIG.
Input signal X (n) including pulse A at each code interval T
Are cascade-connected to each other and are sequentially delayed by delayers D1, D2, D3, and D4 that delay by the one symbol interval T in response to a clock signal from a clock signal source (not shown). Therefore, assuming that the output from the delay unit D3 is the current pulse A (n), the output from the delay unit D4 is the pulse A (n-1) one sample period earlier, and the outputs from the delay units D1 and D2. Are pulse A (n + 2) after two sample periods and pulse A (n + 1) after one sample period, respectively.

When multiplying the pulse A (n + 2) by the coefficient H1, shifters S11 and S12 corresponding to the partial coefficients obtained as shown in Expression 5 are provided. A 4-bit shift to the LSB side corresponding to 0.0625 and multiplication by (−1) are performed, and a partial coefficient −0.01 is obtained in shifter S12.
A 6-bit shift corresponding to 5625 and multiplication by (−1) are performed. The outputs from the shifters S11 and S12 are added to each other by an adder K1, whereby the pulses A (n
+2) can be obtained by multiplying the coefficient H1.
The multiplication process of (-1) in the shifters S11 and S12 is performed on the input side of the adder K1, as described later.

Similarly, the pulse A (n-1) includes shifters S41, S12 similar to the shifters S11, S12, respectively.
By 42, the partial coefficients 0.0625 and 0.015
The multiplication of 625 and the multiplication of (−1) are performed, and the multiplication results are added to each other by the adder K4 to obtain a multiplication value of the coefficient H4.

On the other hand, the pulse A (n + 1) includes
Each of the shifters S21, S22, and S23 corresponding to the partial coefficients obtained as shown in the above-described Expression 6 causes LS
The 1-bit, 4-bit, and 6-bit shift processes are performed on the B side, and their multiplied values are added to each other by adders K21 and K22 to obtain a multiplied value of the coefficient H2. Similarly, for the pulse A (n), the shifter S3
The multiplication is performed by shifting the LSB side by 1 bit, 4 bits and 6 bits by 1, S32 and S33, and the multiplied values are added to each other by adders K31 and K32 to obtain a multiplied value of the coefficient H3. Can be

The outputs from the adders K1 and K22; K32 and K4 are mutually added by the adders K51 and K52 by the adder K53 to obtain an interpolation pulse B (n). The interpolation pulse B (n) is interpolated by the multiplexer 12 following the actual input pulse A (n), and an output signal Y (n) is obtained.

The input of the multiplexer 12 is switched by a clock every half cycle of the code interval T. Thus, the actual input pulse A and the interpolation pulse B are alternately output to the output of the multiplexer 12, and the output is doubled. A low-pass filtering output due to oversampling is output.

If the coefficient is 1 or more, the shifter may shift the input data to the MSB (Most Significant Bit) side. For example, to obtain a multiplication value of 1.5, the shifter , Ie, the sum of the product of the coefficient 2 and the product of the coefficient 1 without shifting.

FIG. 1 shows a digital filter 1 according to the present invention.
FIG. 3 is a block diagram specifically illustrating 1, and portions corresponding to FIG. 2 are denoted by the same reference numerals and description thereof is omitted.
It should be noted that in the configuration of FIG.
A (n + 2) and A to be multiplied by
(N-1) are added to each other in advance by the adder K61, and then the multiplication process of the coefficient H1 (= H4) is performed.
11, S12, and similarly, the same coefficient H
After the pulses A (n + 1) and A (n) multiplied by 2 and H3, respectively, are added to each other in advance by the adder K62, the shifter S that performs the multiplication process of the coefficient H2 (= H3)
21, S22 and S23. As a result, the number of shifters can be reduced by half as compared with the configuration of FIG.

It should also be noted that each shifter S11, S1
2: When performing the addition processing of the multiplication values obtained by the shift processing of S21, S22, and S23, the addition processing is performed from the multiplication values of the partial coefficients having the same absolute value and different signs. That is, the partial coefficient −0.06
The output of the shifter S11 resulting from the multiplication of 25 and the output of the shifter S22 resulting from the multiplication of the partial coefficient 0.0625 are added to each other by an adder K71.
Shifter S as output of shifter S12 resulting from multiplication of 0.015625 and partial coefficient 0.015625
And the output of the adder 23 are added to each other by an adder K72. The outputs from the adders K71 and K72 and the output from the shifter S21 are sequentially added by the adders K81 and K82 to obtain the interpolation pulse B (n).

As described above, by performing the addition process from multiplication values of different signs, occurrence of overflow is suppressed,
The addition result can be accurately stored until the end.

In addition, addition of a positive number and a negative number is usually
As shown in FIG. 5A, the polarity of all the bits of the input data is inverted by the inversion buffer 15 using a two's complementer, and the adder 16 adds 1 to represent a negative number. Thereafter, the addition is performed by the adder 17 to obtain an addition value with a positive number. On the other hand, as shown in FIG. 5B, by adding the multiplication values of the coefficients of different codes as in the present invention, as shown in FIG.
A similar addition process can be realized by directly adding a positive number to the inverted data of all bits by 5 by the adder 18 and adding “1” from the carry bit input of the adder 18. it can.

Therefore, the configuration of the adder 16 and the like can be reduced, and the adders K71 and K72 are configured to add "1" from the carry bit input. Thereby, the adders K71, K7
2 also sets the input of the shifters S11 and S12 to a negative number as described above,
12 is substituted for the multiplication process (-1), and the configurations of the shifters S11 and S12 are simplified.

In the digital filter 11 configured as described above, for example, the input pulses A (n-1), A
Each shifter S11, when 3, 1, 3, -1 are input as (n), A (n + 1), and A (n + 2), respectively.
S12; S21, S22, S23 and the adder K61,
The outputs of K62; K71, K72; K81, K82 are shown in FIG. In contrast, the pulses A (n-1), A
(N), A (n + 1), and A (n + 2) are 1, 1, 1, 1, respectively, that is, shifters S11, S12; S21, S22, S when input signal X (n) is DC.
23 and adders K61, K62; K71, K72; K
The outputs of 81 and K82 are as shown in FIG.

In the present invention, the shift amount and the number of shifters for performing a shift process of 2 bits or more are made equal on the positive coefficient side and the negative coefficient side. That is, the shifter S11 having a negative coefficient and the shifter S having a positive coefficient shifted by 4 bits.
22 and a shifter S12 of a negative coefficient shifted by 6 bits and a shifter S23 of a positive coefficient.

It can be seen from FIG. 4 that the coefficient H2 (= H) at t / T = 0.5 is an arbitrary value of 0 <α ≦ 1.0.
3) is positive and the absolute value is 0.5 or more, and t
The coefficient H1 (= H4) of /T=1.5 is always negative and its absolute value is less than 0.25, and the shift amount of the coefficient H2 can be approximated by a combination of 1 bit and a larger shift amount. , The coefficient H1 can be approximated by a combination of 3 bits and a larger shift amount.

As described above, A (n + 2) = shown in FIG.
Considering a DC input of A (n + 1) = A (n) = A (n-1), the interpolation pulse B (n) should take the same value as the input data, but actually has an infinite impulse response. The values are not the same because the approximation is truncated to a finite number. However, as in the present invention, the shifter S1
1, S12; S21, S22, S23 and adder K6
1, K62; K71, K72; K81, K82, in the case of multiplication of coefficients, as described above, the shift amount and the number of shifters other than the one-bit shift are set to the positive coefficient side and the negative coefficient side. By making them equal to each other,
Terms other than 1-bit shift cancel each other out to have an added value of 0, and when the remaining positive 1-bit shift terms are added,
(1/2) × A (n + 1) + (1/2) × A (n) = B
(N)... (7), and data equal to the input data is obtained, and the DC component can be accurately stored.

Therefore, although the bit length of the coefficient is approximated by 6 bits, as shown in FIG. 7, the interpolation pulse B (n) becomes 1, and the DC component is accurately stored, and the DC pulse Response characteristics can be realized.
In this regard, for example, if shifter S23 is shifted by 7 bits, the partial coefficient in shifter S23 is 0.0078125.
And the interpolation pulse B (n) becomes 0.984375, and the DC component cannot be stored.

It is needless to say that the error caused by approximating the coefficient with a digital value decreases as the number of shifters increases and the number of bits handled increases.

FIG. 8 is a spectrum waveform diagram showing an experimental result of the digital filter 11 configured as described above by the present inventor. By passing the baseband signal of the spectrum shown in FIG. 8B through the digital filter 11, as shown in FIG.
It is understood that a band suppression effect of about 0 dB is obtained and the band is narrowed.

FIG. 9 is a block diagram showing a schematic configuration of a radio communication apparatus 21 using spread spectrum communication, which is an example of use of the digital filter configured as described above. In the transmission device 22, the transmission data is input to the spreading unit 23 to spread the spectrum, and then input to the digital filter 11 according to the present invention to narrow the spectrum. The output from the digital filter 11 is converted to an analog signal by a digital / analog conversion unit 24, and is, for example, 36-value QAM-modulated and amplified by a transmission unit 25, and then transmitted from an antenna 26. The operations of the diffusion unit 23, the digital filter 11, the digital / analog conversion unit 24, and the like are controlled by a clock signal from the control signal generation unit 27.

In the receiving device 32, the received signal received by the antenna 33 is amplified and demodulated in the receiving section 34. The demodulated signal is converted to a digital signal by an analog / digital converter 35,
In 6, a despreading process is performed to decode the data into faithful received data with no intersymbol interference corresponding to the transmitted data. The operations of the analog / digital conversion unit 35 and the despreading unit 36 are controlled by a clock signal from a control signal generation unit 37.

Since the radio communication device 21 using such spread spectrum communication uses a frequency band wider than the frequency band of the transmission data due to the spread, the digital filter 11 according to the present invention uses Unnecessary sideband components in the spread signal can be removed without interference to narrow the band, and even in a limited frequency band, many channels can be secured by frequency multiplexing etc. And the frequency band can be used effectively.

In such a wireless communication device 21,
While many circuits are required for digital signal processing such as diffusion processing and despreading processing, the digital filter 11 according to the present invention uses an FIR filter, which tends to have a large circuit scale, in the characteristics of a roll-off filter. Focusing on the number of taps, focusing on the number of taps, and realizing multiplication processing with shifters and adders can greatly reduce the circuit scale, so it can be integrated into digital signal processing integrated circuits. It is possible to reduce the size, weight, power consumption, cost, and development period.

As a representative of the prior art in which unnecessary sideband components can be removed using a digital filter, Japanese Patent Application Laid-Open No.
-46096. However, this prior art is an example of a quadrature detector, and a moving average filter (a filter similar to FIG. 13 in the present specification) uses a memory for weighting (corresponding to the coefficient in the present case). Therefore, the input data is simply weighted by the memory, and even if the data sequentially passes through the delay unit, each data remains the multiplied value in the memory. As in the present invention, an arbitrary coefficient is assigned to each tap output. Does not multiply.

[0072]

As described above, in the digital filter according to the first aspect of the present invention, a plurality of delay means with taps are connected in cascade, and the output from each tap is multiplied by a predetermined coefficient and then added to each other. When the roll-off ratio is not the ideal filter characteristic of 0 in the FIR digital filter in which the interpolation sample is obtained by performing the interpolation, the input is performed by a shifter that performs a shift operation with a shift amount corresponding to each partial coefficient obtained by decomposing the coefficient. Shift the data,
The interpolated samples are created by adding outputs from the respective shifters by adding means.

Therefore, a multiplier having a complicated configuration is not required, the configuration of the coefficient multiplication circuit can be greatly simplified, and the number of parts, cost, power consumption, development period, and the like can be reduced. It can be suitably used in a data communication device using spread communication.

In the digital filter according to the second aspect of the present invention, the delay means with taps are connected in cascade in a plurality of stages, and the output from each tap is multiplied by a predetermined coefficient and then added to each other. In the FIR type digital filter which obtains an interpolation sample by performing
When the roll-off rate is other than 0, utilizing the fact that the impulse response converges when t / T increases to some extent,
The number of taps is limited based on the level of the impulse response corresponding to the desired roll-off rate.

Therefore, required filtering characteristics can be obtained with a small number of taps.

Further, in the digital filter according to the third aspect of the present invention, as described above, the t / T at which the impulse response substantially converges when the number of taps is an arbitrary value other than 0 at the roll-off rate is set. Limited to ± 4.

Therefore, even when the roll-off rate is small, filtering can be performed without any practical problem.

In the digital filter according to the fourth aspect of the present invention, as described above, in realizing a low-pass filter, a shift that shifts by two bits or more between a shifter for a positive coefficient and a shifter for a negative coefficient. The amount and the number are made equal to each other, and the minute coefficient is made equal on the positive coefficient side and the negative coefficient side.

Therefore, even if the coefficients are truncated at the predetermined bits, the DC components included in the input data can be accurately stored, and a low-pass filter having a response characteristic from the DC region can be realized.

Further, as described above, the digital filter according to the fifth aspect of the present invention uses the symmetry of tap coefficients to generate tap outputs multiplied by mutually equal coefficients.
After mutually adding by the adding means, the shift processing is performed by the shifter.

Therefore, the number of shifters can be reduced to almost half.

Further, in the digital filter according to the invention of claim 6, as described above, the addition process is performed between coefficients of different signs.

Therefore, it is possible to suppress the occurrence of overflow during the calculation and obtain an error-free output in which the addition result is correctly stored.

Usually, the multiplication of the negative coefficient is performed by inverting the polarity of all the bits of the data of the positive coefficient using a two's complementer and then adding “1”. In the present invention, the addition of the negative coefficient component and the positive coefficient by the adder is performed by adding the coefficient of the opposite sign between the obtained negative coefficient and another positive coefficient. Is realized by adding

As a result, an adder such as the complementer is not required, and the configuration can be simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a specific configuration of a digital filter according to an embodiment of the present invention.

FIG. 2 is a block diagram for explaining a basic concept of a digital filter according to the present invention.

FIG. 3 is a diagram illustrating a method for calculating interpolation data of a digital filter according to an embodiment of the present invention.

FIG. 4 is a graph showing an impulse response of a roll-off filter.

FIG. 5 is a block diagram for explaining a method of adding a negative number according to the present invention and the related art.

FIG. 6 is a block diagram for explaining the operation of the digital filter shown in FIG.

FIG. 7 is a block diagram for explaining the operation of the digital filter shown in FIG.

FIG. 8 is a spectrum waveform chart showing experimental results of the present inventor for confirming the effect of narrowing the band by the digital filter shown in FIG.

FIG. 9 is a block diagram illustrating a schematic configuration of a wireless communication device according to a usage example of the digital filter illustrated in FIG. 1;

FIG. 10 is a diagram for explaining the spread of a sideband of a digital signal.

FIG. 11 is a graph for explaining a transfer function of a roll-off filter.

FIG. 12 is a waveform chart for explaining the operation of the roll-off filter.

FIG. 13 is a block diagram showing an electrical configuration of a typical conventional digital filter.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 Digital filter 12 Multiplexer 15 Inverting buffer 16, 17, 18 Adder 21 Wireless communication device 22 Transmitting device 23 Spreading unit 24 Digital / analog converting unit 25 Transmitting unit 26, 33 Antenna 27, 37 Control signal generating unit 32 Receiving device 34 Receiving Unit 35 analog / digital conversion unit 36 despreading unit D1, D2, D3, D4 delay unit K1; K21, K22; K31, K32; K4 adder K51, K52 adder K53 adder K61, K62 adder K71, K72 adder K81, K82 Adders S11, S12 Shifters S21, S22, S23 Shifters S31, S32, S33 Shifters S41, S42 Shifters

Claims (6)

[Claims] A non-cyclic digital filter in which delay means with taps are cascaded in a plurality of stages, an output from each tap is multiplied by a predetermined coefficient, and then added to each other to obtain an interpolation sample. 2. The digital filter according to claim 1, wherein when the roll-off rate is not 0, the multiplication of the coefficient is realized by a shifter and an adding unit. 2. A non-recursive digital filter in which delay means with taps are connected in cascade in a plurality of stages, an output from each tap is multiplied by a predetermined coefficient, and then added to each other to obtain an interpolated sample. 3. The digital filter according to claim 1, wherein the number of taps is limited based on a level of an impulse response corresponding to a desired roll-off rate. 3. The digital filter according to claim 2, wherein the number of taps is limited to t / T (t: sampling period, T: code interval) up to ± 4. 4. In realizing a low-pass filter,
The digital filter according to any one of claims 1 to 3, wherein the shift amount and the number of shifts of two bits or more are made equal between the shifter for the positive coefficient and the shifter for the negative coefficient. 5. The digital filter according to claim 4, wherein tap outputs multiplied by mutually equal coefficients are added to each other by an adder, and then subjected to shift processing by a shifter. 6. The digital filter according to claim 5, wherein said adding process is performed between coefficients of different signs.