JPH11330395A - Semiconductor device and manufacturer thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a capacitor to be more enhance in capacity so as to cope with a reduction in cell size, by a method wherein a conductive layer is formed on a semiconductor substrate, and the surface of the conductive layer is roughened. SOLUTION: A dynamic random access memory(DRAM) is of stack structure, wherein a lower electrode 108 of a memory cell is connected to source/drain regions 105 through the intermediary of a connection plug 109, and an upper electrode 11 of polysilicon is formed on the lower electrode 108 through the intermediary of a capacitor insulating film 110 to form a capacitor. At this point, the surface of the lower electrode 108 of the DRAM is roughened into a rugged surface A. By this setup, the surface of the lower electrode 108 is enlarged in surface area, so that a capacitor can be markedly enhanced in capacity. Therefore, a capacitor can be ensured of enough capacity so as to cope with a more reduction in cell size in future.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device such as a DRAM having a characteristic shape of a conductive layer such as a capacitor electrode having a large capacitance and a method of manufacturing the same.

[0002]

2. Description of the Related Art With the recent large-scale integration of semiconductor integrated circuits, there is a demand for further reduction in cell size. In particular, in a DRAM mainly having a one-transistor capacitor type memory cell structure, the structure of the memory cell is extremely simple, and many memory cells can be mounted on a memory chip of the same size. Therefore, it is most suitable for high integration, and there is a great merit that the mounting density can be increased by reducing the memory size.

On the other hand, a reduction in the memory size means a reduction in the capacitance of the capacitor. However, in order to prevent an accidental malfunction (soft error) due to natural radiation or the like, it is necessary to secure the capacitance of the capacitor to a certain value or more. There is.

For this reason, various measures have been taken to increase the effective area of the cell while keeping the cell size as small as possible. As one example, a conventional one-transistor, one-capacitor memory cell is shown in FIG. In FIG. 11A, reference numeral 401 denotes a p-type semiconductor substrate;
402 is a field oxide film, 405 is a source / drain region, 403 is a gate oxide film, 404 is a gate electrode (word line), 411 is a capacitor upper electrode, 408 is a charge storage layer, 419 is a bit line, 420 is a bit contact, 418 is SiO ₂ or PSG (Phospho-S)
Insulating layers such as ilicate-glass) are shown.

In FIG. 11A, the transfer transistor comprises an impurity diffusion region (405) as a source and a drain, a gate electrode 404, and a gate oxide film 403, while the capacitor is connected to a drain region 405 of the transistor. Charge storage layer 408,
Upper electrode 411 and insulating films 402 and 403 therebetween.
It consists of.

In the case of manufacturing the semiconductor device shown in FIG. 11A, for example, the gate electrode 404 and the capacitor upper electrode 411 can be formed of different polysilicon layers, respectively, and the bit line 419 can be formed of an aluminum layer. . That is, it can be manufactured by using a relatively simple two-layer polysilicon manufacturing process.

However, since the capacitor of the semiconductor device having this structure has a wide impurity diffusion region connected thereto,
A soft error due to α rays is likely to occur, and the area for a capacitor is small, which is disadvantageous for high integration and large capacity.

[0008]

As a solution to the above problems, there has been proposed a stacked-capacitor memory cell which is an improved one-transistor one-capacitor memory cell (for example, Technical Report of IEICE). , S
SD80-30, 1980).

FIG. 11B shows an example of the stacked capacitor type memory cell. That is, FIG.
In place of the charge storage layer 408, a capacitor lower electrode 415 connected to the source / drain region 405 by opening a contact hole is provided.

This semiconductor device has a capacitor lower electrode 4
Reference numeral 15 denotes a portion on the gate electrode 404 and the field insulating film 40
2, and in this case, is constituted by a counter electrode (upper electrode) 417 and these insulating films 416. The capacitance of the stacked capacitor type memory cell shown in FIG. 11B is larger than that of the one-transistor one-capacitor type memory cell of FIG.
Further, since the impurity diffusion region (source / drain region) is narrow, the rate of occurrence of soft errors due to α rays or the like can be reduced.

However, in the current trend of large-scale integration of semiconductor devices such as DRAMs, the above-mentioned stacked capacitor type memory cell having a capacitor lower electrode extending over the gate electrode 404 and the field oxide film 402 However, when the cell size is reduced, the capacitance of the cell capacitor is not sufficient.

As a means for improving this, a method has been proposed in which the thickness of the capacitor lower electrode is increased to increase the area of the electrode side surface. However, in this method, a load in dry etching of the electrode is increased. Also, from the viewpoint of yield, it is difficult to increase the thickness of the electrode in order to cope with a further reduction in cell size.

The present invention has been made in view of the above problems, and has a fine structure having a conductive layer such as a capacitor electrode having a large capacity in order to cope with further reduction in cell size. It is an object to provide a semiconductor device such as a DRAM and a method for manufacturing the same.

[0014]

In order to achieve the above object, the present invention provides a semiconductor device having a conductive layer on a semiconductor substrate, wherein the conductive layer has a roughened surface. A semiconductor device is provided.

The material constituting the conductive layer is, for example, a group consisting of polysilicon, doped polysilicon, aluminum, aluminum alloy, copper, copper alloy, titanium, titanium alloy, tungsten, tungsten alloy and organic conductor. One or more selected ones can be mentioned.

A semiconductor device according to the present invention is characterized in that it has a conductive layer whose surface has been subjected to a roughening treatment. The surface is subjected to a roughening treatment, that is, a treatment for forming irregularities on the surface of the conductive layer, and the surface area is increased. Therefore,
The semiconductor device of the present invention has a conductive layer whose capacity is significantly increased, and is required not only for present but also for future further reduction in cell size without increasing the thickness of the conductive layer. Thus, a sufficient capacitor capacity can be secured.

The semiconductor device of the present invention is preferably a semiconductor device having a conductive layer connected to source / drain regions provided on a semiconductor substrate, and more preferably using the conductive layer as an electrode.

Further, the present invention provides a semiconductor comprising a step of forming an insulating film on a semiconductor substrate, a step of forming a conductive layer on the insulating film, and a step of roughening the surface of the conductive layer. An apparatus manufacturing method is provided.

In the method of manufacturing a semiconductor device according to the present invention, the step of roughening the surface of the conductive layer preferably includes the step of forming the surface of the conductive layer with a hardness and a particle size which affect the shape of the surface of the conductive layer. This is a step of forming irregularities on the surface of the conductive layer by spraying particles having the same.

Further, in the method of manufacturing a semiconductor device according to the present invention, after the step of roughening the surface of the conductive layer,
It is preferable that the method further includes a step of removing particles having a hardness and a particle diameter which affect the shape of the conductive layer surface attached to the conductive layer surface.

Further, in the method of manufacturing a semiconductor device according to the present invention, the conductive layer is connected to the source / drain region before the step of forming a conductive layer on the insulating film on the source / drain region. It is preferable that the method further includes a step of forming a connection plug.

The step of forming a connection plug for connecting the conductive layer and the source / drain region includes the step of:
After opening a connection hole in the insulating film on the drain region,
Preferably, a conductive material is buried in the connection holes, and the surface of the base is flattened by, for example, a chemical mechanical polishing (CMP) method or an etch-back method.

The conductive material used in the step of forming the connection plug includes polysilicon, doped polysilicon, aluminum, aluminum alloy, copper, copper alloy, titanium, titanium alloy, tungsten, tungsten alloy, and organic conductor. Preferred examples include one or more materials selected from the group consisting of:

Further, in the manufacturing method according to the present invention, after the step of removing particles having a hardness and a particle size which affect the shape of the surface of the conductive layer and adhere to the surface of the conductive layer, the method further comprises: The method preferably includes a step of forming an insulating film so as to cover the layer, and a step of forming a second conductive layer over the insulating film. Accordingly, a semiconductor device having a so-called stacked structure in which the conductive layer whose surface is roughened is used as a lower electrode and has an upper electrode via an insulating film can be manufactured with high yield.

As the semiconductor device manufactured by the semiconductor device and the method of manufacturing the same according to the present invention, a DRAM (Dynamic Land) using the conductive layer as an electrode is used.
mA Access Memory) or SRAM (Stat
RAM (Random Access Memory) such as ic Random Access Memory
y) and mask ROM, EPROM, EEPROM, FR
ROM (Read Only Memory) such as OM
Etc.

According to the present invention, it is possible to provide a semiconductor device having a highly reliable microstructure having a conductive layer in which the capacitance of the capacitor is dramatically increased while keeping the cell size unchanged.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in more detail with reference to embodiments. First embodiment

The first embodiment of the present invention is a DRAM having a stacked structure shown in FIG. D of this stacked structure
The RAM includes a source / drain region 105 and a connection plug 1
Memory cell (lower electrode) 108 connected via
Is provided with a polysilicon layer (upper electrode) 111 interposed therebetween through a capacitor insulating film 110 to form a capacitor between polysilicon. It is composed of a capacitor for storing charges and a MOS transistor that operates as a cell selection switch. The gate 104 of the transistor is connected to a word line (not shown) to which a selection signal of a memory cell is supplied, and controls opening and closing of the memory cell. In addition, the drain (source
A drain region 105 is connected to a cell information extracting bit line 114 which is arranged orthogonally to a word line, and exchanges data between a memory cell and a read or write circuit.

The DRAM of this embodiment shown in FIG. 1 is characterized in that the surface of the lower electrode 108 is subjected to a surface roughening process, that is, the unevenness A is formed on the surface. The electrode whose surface is roughened as described above has a large surface area of the electrode surface, and the capacitance of the capacitor is greatly increased. Therefore, the semiconductor device can sufficiently secure the required capacitor capacity not only for the present but also for the future reduction of the cell size.

Second Embodiment A second embodiment of the present invention is an example of manufacturing the stacked DRAM shown in FIG. Hereinafter, this manufacturing process will be described with reference to the drawings.

First, a description will be given of the state up to the state shown in FIG. On a semiconductor substrate (p-type or n-type) 101,
For example, LOCOS (Local Oxidation
of thick device isolation film 1 by the
02 is formed to perform element isolation. Then
A thin gate oxide film 103 is formed in the element isolation region by, for example, a thermal oxidation method. Next, for example, after depositing polysilicon and forming a resist film (not shown), predetermined patterning is performed to form the gate electrode 104.

Further, a source / drain region 105 is formed in the peripheral portion of the gate electrode 104 by introducing an impurity of a conductivity type opposite to that of the semiconductor substrate by, for example, an ion implantation method. Then, for example, SiH ₄ —O ₂ , TEOS
(Tetraethylorthosilicate)
(Chemical Vap)
An insulating film 106 such as a silicon oxide film is formed on the entire surface by an our deposition method.

Subsequently, an etching stopper film 107 is formed on the insulating film 106. This film is an insulating film 1
06 is a film made of a material having an etching rate lower than that of the material composing 06. Examples of such a film include a silicon nitride film, a boron-doped silicon oxide film, and a SIP.
OS (Semi Insulating Polysi)
silicone) film.

The silicon nitride film is made of, for example, SiCl
_{4 -NH 3 -H 2, SiH 4} -NH 3 -N 2, SiH 2
A silicon oxide film doped with boron by a CVD method using Cl ₂ —N ₂ O or the like as a source gas is, for example, B ₂ H
By the ₆ -SiH ₄ -O ₂ CVD method using a raw material gas,
The SIPOS film is made of, for example, SiH ₄ —N ₂ O, S
Each of them can be formed by a CVD method using iH ₂ Cl ₂ —N ₂ O or the like as a source material.

Next, as shown in FIG. 2B, a resist film (not shown) is formed on the entire surface, patterning for forming a connection hole is performed, and a connection hole 112 reaching the source / drain region 105 is formed by etching. Form.

Next, as shown in FIG. 3C, a conductive material is deposited on the entire surface, and a connection plug 109 is formed, and at the same time, a conductive film 113 is formed on the entire surface. As a method for depositing a conductive substance, for example, a sputtering method, an evaporation method, C
There is a VD method or the like. Note that the conductive material that fills the connection hole 112 and the conductive material that forms the conductive film 113 may be different. In this case, the formation of the connection plug and the conductive film may be performed in different steps.

As the conductive material, any material can be used without particular limitation as long as it is a material having the same hardness or a lower hardness than the fine particles used for roughening later. For example, polysilicon, doped silicon, aluminum, aluminum alloy, titanium, titanium alloy,
Tungsten, a tungsten alloy or a combination thereof can be used.

Further, as shown in FIG. 3D, after forming a resist film (not shown) on the conductive film 113 and performing predetermined patterning, the lower electrode 108 is formed by, for example, a photo-etching technique. Form.

Next, for example, a particle size of 0.01 to 0.5 μm
A small amount of fine particles 1 are sprayed on the device surface at high speed.
This is a so-called sandblasting process. By this operation, as shown in FIG.
Innumerable irregularities A are formed on the surface 08. At this time,
Similar irregularities (surface roughness) are also formed on the surface of the etching stopper film 107.

The fine particles can be used without any particular limitation as long as they have the same or higher hardness as the conductive material and preferably have no reactivity with the conductive material. For example, silicon oxide, silicon nitride, silicon,
Zirconium oxide, cesium oxide, and the like can be given. These are, depending on the conductive material to be subjected to the surface roughening treatment,
It can be selected as appropriate.

The roughness of the electrode surface changes depending on the particle diameter of the fine particles and the speed at which the fine particles are sprayed. However, the conditions of the surface roughening treatment such as the electrode material, the type of the fine particles, the particle size, and the speed at which the fine particles are sprayed are appropriately changed. By doing so, an electrode having a desired capacity can be formed.

Next, as shown in FIG.
Fine particles adhering to the surface of the etching stopper film 107 and the surface of the etching stopper film 107 are removed using, for example, hydrofluoric acid. This removal treatment is performed, particularly when the fine particles are an insulator such as silicon oxide silicon nitride, because the insulator remains on the surface of the electrode, causing an obstacle to conductivity.

Thereafter, the etching stopper film 107 is removed under the etching conditions for removing only the etching stopper film 107 while leaving the electrode 108 and the insulating film 106. For example, when the etching stopper film 107 is a silicon nitride film and the insulating film 106 is a silicon oxide film, etching can be performed by plasma etching using CF ₄ —O ₂ or the like.

Subsequently, as shown in FIG. 5G, a capacitor insulating film 110 made of, for example, silicon oxide or the like is formed so as to cover the lower electrode 108 by, for example, a CVD method.

Further, as shown in FIG. 5 (h), a conductive material for forming an upper electrode is deposited on the entire surface of the capacitor insulating film 116 by, for example, a sputtering method, a vapor deposition method, a CVD method, or the like. Then, the upper electrode 111 is formed by performing electrode processing. Next, an insulating film 112 such as a silicon oxide film is formed on the entire surface by, for example, a CVD method.

Finally, by forming the bit line (wiring layer) 114 and the bit contact 119 connecting the bit line 114 to the source / drain region 105, the DRAM having the stacked structure shown in FIG. 1 can be manufactured. .

According to the present embodiment, a DRAM having a lower electrode in which countless irregularities are formed on the surface by the surface roughening treatment and the capacitance of the capacitor is greatly increased can be manufactured easily and with good yield.

Third Embodiment This embodiment is an example of manufacturing a semiconductor device in which a surface of a conductive film is subjected to a surface roughening treatment after a conductive film is formed and before the electrode is processed, and then the electrode is processed.

First, from the state shown in FIG. 2B, a conductive material is deposited on the entire surface to form the connection plug 209 and the conductive film 213, thereby obtaining the state shown in FIG. 6A. Examples of the conductive substance include polysilicon, silicon doped with impurities, aluminum, an aluminum alloy, titanium, a titanium alloy, tungsten, a tungsten alloy, a combination thereof, and the like.

Next, as shown in FIG. 6B, for example, a so-called sand blasting process in which fine particles 2 having a diameter of about 0.01 to 0.5 μm are sprayed on the device surface at a high speed is performed. By this operation, countless irregularities B are formed on the surface of the conductive film 213. After that, a process of removing fine particles (insulator) attached to the surface of the conductive film 213 using, for example, hydrogen fluoride or the like is performed as necessary. As the types of fine particles that can be used here, those similar to those listed in the first embodiment can be used.

Next, after a resist film (not shown) is formed on the entire surface, patterning for forming an electrode is performed.
An electrode as shown in (c) is formed.

Finally, an insulating film 210 such as a silicon oxide film is formed on the entire surface of the electrode 208, thereby forming a planar D-type transistor shown in FIG.
RAM can be manufactured.

According to the present embodiment, an infinite number of irregularities B are formed on the upper surface of the electrode by a roughening process, and a DRAM having a lower electrode with a significantly increased capacitor capacity can be manufactured simply and with good yield.

Fourth Embodiment A fourth embodiment of the present invention is an example of manufacturing a semiconductor device in which after an electrode is formed using a dummy film, the surface of the electrode is subjected to a surface roughening treatment.

First, a description will be given of the state up to the state shown in FIG. From the state shown in FIG. 2B, an etching stopper film 307 is formed. Next, a dummy film 308 having a desired thickness is formed on the etching stopper film 307.
To form The dummy film 308 is formed of a material having a higher etching rate than the material of the etching stopper film 307. As such a high etching rate material, for example, PSG (Phospho Silicat) is used.
e Glass) film, SOG (Spin on Glass)
s) A film, a dielectric organic film, and the like can be given, but there is no particular limitation as long as the material has a higher etching rate than the material forming the etching stopper film 307.

The PSG film is made of, for example, PH ₃ -SiH
_The SOG film can be formed, for example, by CVD using _4- O ₂ or the like as a source gas, after spin-coating glass dissolved in an organic solvent on a substrate, and then performing heat treatment.

Examples of the dielectric organic film include cyclic fluororesin, polytetrafluoroethylene, polyfluoroethylene propylene, ethylene tetrafluoride-perfluoroalkoxyethylene copolymer, polyvinylidene fluoride, and polytrifluoride. Examples include fluorinated ethylene chloride, fluorinated aryl ether resin, fluorinated polyimide, polyimide, benzocyclobutene polymer (BCB), monomethyltrihydroxysilane condensate (organic SOG), and aryl ether resin. These organic films are formed, for example, by forming a polymer precursor using a spin coater,
The film can be formed by firing at a temperature of about 500 ° C.

Thereafter, as shown in FIG. 8B, a resist film (not shown) is formed on the entire surface, and patterning for electrode formation is performed on the electrode formation region on the source / drain region 305, for example, by dry etching. Thereby, a penetrating contact hole 309 is formed.

Next, a conductive material is deposited on the entire surface so as to fill the contact hole. Examples of a method for depositing a conductive material include a sputtering method, a vapor deposition method, and a CVD method.
And the like. In addition, as the conductive material, polysilicon, silicon doped with impurities, aluminum, aluminum alloy, titanium, titanium alloy,
Tungsten, a tungsten alloy and the like can be given.

Next, a coating such as a resist film is applied to the entire surface,
An etch-back method for etching the entire surface, or a chemical-mechanical polishing method for polishing the surface using an abrasive (CMP
By the method, the conductive material is selectively left in the contact hole 309 to obtain the state shown in FIG.

Examples of the abrasive that can be used in the CMP method include alumina, manganese dioxide, silica-based slurry, tungsten oxide, cesium oxide, and zirconium oxide represented by the formula W _X O _y. Thereby, hydrogen peroxide, potassium hydroxide, ammonia and the like can be contained in these.

Subsequently, as shown in FIG. 9D, the dummy film 308 is selectively removed, and the contact plug 311 is removed.
And the electrode 310 are formed simultaneously.

Next, as shown in FIG. 10 (e), fine particles 3 having a diameter of, for example, about 0.01 to 0.5 μm are sprayed on the device surface at a high speed to form an uneven shape C on the electrode surface. The types of fine particles that can be used here are the same as those listed in the first embodiment.

Finally, a planar DRAM shown in FIG. 10F can be manufactured by forming an insulating film 311 such as a silicon oxide film on the entire surface of the electrode 310.

According to the present embodiment, an infinite number of irregularities are formed on the upper surface of the electrode by a roughening process, and a DRAM having a lower electrode with a significantly increased capacitor capacity can be manufactured simply and with high yield.

[0066]

As described above, the present invention is a semiconductor device characterized by having a conductive layer whose surface has been subjected to a surface roughening treatment. Since the semiconductor device of the present invention has a myriad of irregularities on the surface of the conductive layer, the capacity of the conductive layer is greatly increased. Therefore, the semiconductor device of the present invention is a semiconductor device having a conductive layer in which a sufficient capacity required is secured not only for the present time but also for the further reduction of the cell size in the future.

Further, the present invention is a method for manufacturing a semiconductor device, characterized by comprising a step of forming a myriad of irregularities on the surface of the conductive layer by spraying fine particles on the surface of the conductive layer at a high speed. According to the present invention, a semiconductor device having a conductive layer whose capacitance is greatly increased can be manufactured easily and with good yield.

[Brief description of the drawings]

FIG. 1 is a structural cross-sectional view of a stacked DRAM which is a semiconductor device of the present invention.

FIG. 2 is a sectional view of a main step in a manufacturing process of the semiconductor device of the present invention.

FIG. 3 is a sectional view of a main step in a manufacturing process of the semiconductor device of the present invention.

FIG. 4 is a sectional view of a main step in a manufacturing process of the semiconductor device of the present invention.

FIG. 5 is a sectional view of a main step in a manufacturing process of the semiconductor device of the present invention.

FIG. 6 is a sectional view of a main step in a manufacturing process of the semiconductor device of the present invention.

FIG. 7 is a sectional view of a main process in a manufacturing process of the semiconductor device of the present invention.

FIG. 8 is a sectional view of a main step in a manufacturing process of the semiconductor device of the present invention.

FIG. 9 is a sectional view of a main step in a manufacturing process of the semiconductor device of the present invention.

FIG. 10 is a sectional view of a main step in a manufacturing process of the semiconductor device of the present invention.

FIG. 11 is a DRAM as a conventional semiconductor device.
2A is a structural sectional view of a conventional Planer type DRAM, and FIG. 2B is a structural sectional view of a conventional stacked DRAM.

[Explanation of symbols]

1,2,3 ... fine particles, 101,201,301,401
... Semiconductor substrate, 102, 202, 302, 402 ... Field oxide film, 103, 203, 303, 403 ... Gate oxide film, 104, 204, 304, 404 ... Gate electrode, 105, 205, 305, 405 ... Source / drain Regions (impurity diffusion regions), 106, 112, 206,
306, 418 ... interlayer insulating films, 107, 207, 307
... Etching stopper film, 108, 208, 310,
415 ... electrodes (lower electrodes), 109, 209, 309 ...
Connection plug, 110, 210, 311, 416: capacitor insulating film, 111, 411, 417: upper electrode, 11
5 ... connection holes, 113, 213 ... conductive films, 114, 419
... bit lines, 119, 420 ... bit contacts, 30
8: dummy film, 408: charge storage layer, A, B, C: uneven shape

Claims (16)

[Claims] 1. A semiconductor device having a conductive layer on a semiconductor substrate, wherein the conductive layer is a conductive layer whose surface has been subjected to a roughening treatment. 2. The semiconductor device according to claim 1, wherein said conductive layer is a conductive layer connected to source / drain regions provided on a semiconductor substrate. 3. The semiconductor device according to claim 1, wherein said conductive layer is a lower electrode. 4. The semiconductor device according to claim 1, wherein said semiconductor device is a semiconductor device having a stacked structure in which said conductive layer is used as a lower electrode and an upper electrode is further provided thereon via an insulating film. 5. The material forming the conductive layer is selected from the group consisting of polysilicon, doped polysilicon, aluminum, aluminum alloy, copper, copper alloy, titanium, titanium alloy, tungsten, tungsten alloy and organic conductor. The semiconductor device according to claim 1, wherein the device is one or more types. 6. A method of manufacturing a semiconductor device, comprising: a step of forming an insulating film on a semiconductor substrate; a step of forming a conductive layer on the insulating film; and a step of roughening the surface of the conductive layer. Method. 7. The step of roughening the surface of the conductive layer includes spraying particles having a hardness and a particle size that affect the shape of the surface of the conductive layer onto the surface of the conductive layer. The method for manufacturing a semiconductor device according to claim 6, wherein the step is a step of forming irregularities on the surface. 8. The method of manufacturing a semiconductor device according to claim 6, wherein the particles having a hardness and a particle size that affect the shape of the surface of the conductive layer are particles made of silicon oxide, silicon nitride, or silicon. 9. After the step of roughening the surface of the conductive layer, further removing particles having a hardness and a particle size that affect the shape of the surface of the conductive layer and adhere to the surface of the conductive layer. The method of manufacturing a semiconductor device according to claim 6, further comprising: 10. The conductive material is polysilicon, doped polysilicon, aluminum, an aluminum alloy,
The method of manufacturing a semiconductor device according to claim 6, wherein the method is one or more kinds selected from the group consisting of copper, copper alloy, titanium, titanium alloy, tungsten, tungsten alloy, and organic conductor. 11. The method according to claim 6, further comprising, before the step of forming a conductive layer on the insulating film, a step of forming a connection plug for connecting the conductive layer to a source / drain region provided on a semiconductor substrate. The manufacturing method of the semiconductor device described in the above. 12. The step of forming the connection plug includes the steps of: opening a connection hole in the insulating film on the source / drain region provided in the semiconductor substrate; filling a conductive material in the connection hole; 12. The method for manufacturing a semiconductor device according to claim 11, wherein the step is a step of flattening. 13. The method according to claim 12, wherein the step of flattening the surface of the base is a step of flattening the surface by a chemical mechanical polishing (CMP) method. 14. The conductive material is polysilicon, doped polysilicon, aluminum, an aluminum alloy,
The method of manufacturing a semiconductor device according to claim 11, wherein the material is at least one material selected from the group consisting of copper, a copper alloy, titanium, a titanium alloy, tungsten, a tungsten alloy, and an organic conductor. 15. The method according to claim 15, wherein the electrode is a DRAM (Dynamic).
The method of manufacturing a semiconductor device according to claim 6, wherein the lower electrode is a lower electrode of a random access memory. 16. An insulating film is further formed to cover the conductive layer after the step of removing particles having a hardness and a particle size affecting the shape of the conductive layer surface attached to the conductive layer surface. The method of manufacturing a semiconductor device according to claim 9, further comprising: forming a second conductive layer on the insulating film.