JPH11330391A - Capacity element and its manufacture - Google Patents

Capacity element and its manufacture

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Publication number
JPH11330391A
JPH11330391A JP11110756A JP11075699A JPH11330391A JP H11330391 A JPH11330391 A JP H11330391A JP 11110756 A JP11110756 A JP 11110756A JP 11075699 A JP11075699 A JP 11075699A JP H11330391 A JPH11330391 A JP H11330391A
Authority
JP
Japan
Prior art keywords
insulating film
film
electrode
forming
ferroelectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11110756A
Other languages
Japanese (ja)
Other versions
JP3130299B2 (en
Inventor
Akihiro Matsuda
明浩 松田
Yoshihisa Nagano
能久 長野
Toru Nasu
徹 那須
Koji Arita
浩二 有田
Yasuhiro Uemoto
康裕 上本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP11110756A priority Critical patent/JP3130299B2/en
Publication of JPH11330391A publication Critical patent/JPH11330391A/en
Application granted granted Critical
Publication of JP3130299B2 publication Critical patent/JP3130299B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To provide a capacity element having excellent electric characteristics and high reliability by flattening a surface of a capacity insulating film and a method for manufacturing it. SOLUTION: The capacity element comprises a supporting board 1, a first electrode 2 formed on the board 1, a first insulating film 5 formed on the electrode 2 and constituted by a ferroelectric material or a high dielectric material, a second insulating film 8 formed on the film 5 and constituted by the same material as that of the film 5, and a second electrode 4 formed on the film 8 in such a manner that a mean particle size of crystal grain of an insulator for constituting the film 8 is smaller than that of the insulator for constituting the film 5.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体集積回路に
内蔵される強誘電体膜または高誘電率を有する誘電体膜
を容量絶縁膜とする容量素子およびその製造方法に関す
る。
The present invention relates to a capacitive element using a ferroelectric film or a dielectric film having a high dielectric constant incorporated in a semiconductor integrated circuit as a capacitive insulating film, and a method of manufacturing the same.

【0002】[0002]

【従来の技術】近年、民生用電子機器を構成する多くの
半導体装置の高密度化に伴い使用される半導体素子の微
細化が進んできており、電子機器から発生される電磁波
雑音である不要輻射が大きな問題になっている。この不
要輻射低減対策として強誘電体または高誘電率を有する
誘電体膜(以下、これらを高誘電体膜という)を容量絶
縁膜とする大容量の容量素子を半導体集積回路に内蔵す
る技術が注目を浴びている。
2. Description of the Related Art In recent years, with the increase in the density of many semiconductor devices constituting consumer electronic equipment, the miniaturization of semiconductor elements used has been advanced, and unnecessary radiation, which is electromagnetic noise generated from electronic equipment, has been advanced. Is a big problem. As a countermeasure for reducing this unnecessary radiation, attention is paid to a technology for incorporating a large-capacity capacitive element in a semiconductor integrated circuit using a ferroelectric or a dielectric film having a high dielectric constant (hereinafter referred to as a high dielectric film) as a capacitive insulating film. Is taking a bath.

【0003】また、従来にない低動作電圧、高速書き込
みおよび高速読み出し可能な不揮発性RAMの実用化を
目指し、自発分極特性を有する強誘電体膜を容量絶縁膜
とする容量素子を半導体集積回路の上に形成するための
技術開発が盛んに行われている。
In addition, with the aim of putting a non-volatile RAM capable of low operating voltage, high speed writing and high speed reading to a practical level, a capacitor element using a ferroelectric film having spontaneous polarization characteristics as a capacitor insulating film has been developed. Technical development for forming on top is being actively carried out.

【0004】以下図2(a)〜(c)を用いて従来の強
誘電体薄膜を用いた容量素子の製造方法を説明する。支
持基板1上に選択的にPt膜よりなる第1の電極2がス
パッタにより形成される(a)。つぎに第1の電極2上
にSrBi2Ta29よりなる容量絶縁膜3が塗布法ま
たはCVD(Chemical Vapor Deposition)法またはス
パッタ法により膜厚100〜250nmの範囲内の厚さ
に形成された後、酸素雰囲気中で650〜800℃の範
囲内の温度で焼結される(b)。引き続き膜厚100〜
300nmの範囲内の厚さのPt膜よりなる第2の電極
4が、容量絶縁膜3の表面にスパッタ法により形成され
て、図2(c)に示す容量素子が形成される。
A method of manufacturing a capacitor using a conventional ferroelectric thin film will be described below with reference to FIGS. A first electrode 2 made of a Pt film is selectively formed on a support substrate 1 by sputtering (a). Next, a capacitance insulating film 3 made of SrBi 2 Ta 2 O 9 is formed on the first electrode 2 by a coating method, a CVD (Chemical Vapor Deposition) method, or a sputtering method to a thickness in a range of 100 to 250 nm. After that, it is sintered at a temperature in the range of 650 to 800 ° C. in an oxygen atmosphere (b). Continue film thickness 100 ~
A second electrode 4 made of a Pt film having a thickness in the range of 300 nm is formed on the surface of the capacitive insulating film 3 by a sputtering method, thereby forming the capacitive element shown in FIG.

【0005】[0005]

【発明が解決しようとする課題】しかしながら上記従来
の製造方法では、容量絶縁膜3が高誘電体として十分な
高誘電率を得るためには、または強誘電体として十分な
自発分極量を確保するためには、最低でも約100nm
の大きさの結晶粒を形成することが必要であり、平均の
厚さが約200nm程度の容量絶縁膜3では強誘電体薄
膜の結晶粒の大きさが容量絶縁膜としての必要な厚さに
比較して大きくなる。そのため、強誘電体薄膜の表面の
凹凸が大きくなり、このような強誘電体薄膜を用いて容
量素子を製作した場合、絶縁耐圧および誘電率または自
発分極量等の電気特性の大きなばらつきを生じたり、容
量絶縁膜3上に形成された配線に断線が発生したりする
という工程での加工上の問題および容量素子を内蔵する
半導体装置の信頼性上の問題等があった。
However, in the above-mentioned conventional manufacturing method, a sufficient amount of spontaneous polarization is required for the capacitor insulating film 3 to obtain a sufficiently high dielectric constant as a high dielectric substance or as a ferroelectric substance. For this, at least about 100nm
It is necessary to form crystal grains of the size of the ferroelectric thin film in the capacitance insulating film 3 having an average thickness of about 200 nm. It will be larger in comparison. Therefore, the surface irregularities of the ferroelectric thin film become large, and when a capacitive element is manufactured using such a ferroelectric thin film, large variations in electrical characteristics such as dielectric strength and dielectric constant or spontaneous polarization may occur. In addition, there is a problem in processing in a process such as disconnection of wiring formed on the capacitor insulating film 3 and a problem in reliability of a semiconductor device having a built-in capacitor.

【0006】本発明は上記従来の課題を解決するもので
あり、容量絶縁膜の表面を平坦化することにより優れた
電気特性と高い信頼性を備えた容量素子およびその製造
方法を提供することを目的とする。
An object of the present invention is to solve the above-mentioned conventional problems and to provide a capacitive element having excellent electrical characteristics and high reliability by flattening the surface of a capacitive insulating film and a method of manufacturing the same. Aim.

【0007】[0007]

【課題を解決するための手段】上記目的を達成するため
に本発明は、支持基板の一表面上に金属膜あるいは導電
性酸化物膜よりなる第1の電極を形成する工程と、第1
の電極上に主成分が強誘電体または高誘電率を有する誘
電体からなる第1の絶縁膜を焼結して形成する工程と、
その第1の絶縁膜上に第2の絶縁膜を熱処理して形成す
る工程と、その第2の絶縁膜上に金属膜あるいは導電性
酸化物膜よりなる第2の電極を形成する工程とを備える
ものである。
In order to achieve the above object, the present invention provides a method for forming a first electrode made of a metal film or a conductive oxide film on one surface of a supporting substrate;
A step of sintering and forming a first insulating film whose main component is a ferroelectric or a dielectric having a high dielectric constant on the electrode of
A step of forming a second insulating film by heat treatment on the first insulating film, and a step of forming a second electrode made of a metal film or a conductive oxide film on the second insulating film. It is provided.

【0008】また第2の絶縁膜を構成する材料の結晶粒
の平均粒径が第1の絶縁膜を構成する材料の平均粒径よ
りも小さいか、または第2の絶縁膜を構成する材料が結
晶以外に非晶質領域を含んでいるものであり、第2の絶
縁膜の主成分が第1の絶縁膜の主成分と同じ強誘電体ま
たは高誘電率を有する誘電体からなり、さらに第2の絶
縁膜を熱処理して形成する工程における処理温度を第1
の絶縁膜を焼結して形成する工程における焼結温度より
も低くしたものである。
The average grain size of the crystal grains of the material forming the second insulating film is smaller than the average grain size of the material forming the first insulating film, or the material forming the second insulating film is The second insulating film has a main component of the same ferroelectric or high dielectric constant as the main component of the first insulating film. The processing temperature in the step of forming the second insulating film by heat treatment is set to a first temperature.
Is lower than the sintering temperature in the step of forming the insulating film by sintering.

【0009】またさらに第1の絶縁膜を構成する材料と
して少なくともBiを含む強誘電体を用いたものであ
る。
Further, a ferroelectric material containing at least Bi is used as a material constituting the first insulating film.

【0010】したがって本発明によれば、強誘電体また
は高誘電率を有する誘電体からなる第1の絶縁膜を焼結
し、その表面の凹凸の大きい第1の絶縁膜の表面を結晶
粒の平均粒径が第1の絶縁膜の平均粒径よりも小さい
か、または結晶以外に非晶質領域を含んでいる第2の絶
縁膜によって被覆することで、表面が平坦な容量絶縁膜
を得ることができる。
Therefore, according to the present invention, the first insulating film made of a ferroelectric or a dielectric having a high dielectric constant is sintered, and the surface of the first insulating film having large irregularities on the surface is formed of crystal grains. A capacitor insulating film having a flat surface is obtained by covering with a second insulating film having an average particle size smaller than the average particle size of the first insulating film or including an amorphous region other than a crystal. be able to.

【0011】[0011]

【発明の実施の形態】以下、本発明の実施の形態につい
て、図面を参照しながら説明する。
Embodiments of the present invention will be described below with reference to the drawings.

【0012】図1は本発明の第1の実施の形態における
容量素子の製造方法を説明する工程断面図である。な
お、図1において、図2と対応する部分には同じ符号を
付して説明する。
FIG. 1 is a process sectional view for explaining a method of manufacturing a capacitive element according to a first embodiment of the present invention. Note that, in FIG. 1, portions corresponding to those in FIG.

【0013】支持基板1上にPt膜よりなる第1の電極
2を50〜400nmの範囲内の厚さに形成する(図1
(a))。つぎに、第1の電極2上にSrBi2Ta2
9よりなる第1の絶縁膜5を回転塗布法またはCVD(C
hemical Vapor Deposition)法、またはスパッタ法を用
いて50〜250nmの範囲内の厚さに形成し、酸素雰
囲気中において800℃で焼結する(図1(b))。つ
ぎに焼結によって結晶化させ、結晶粒子によって凹凸が
生じた第1の絶縁膜5の表面に第2の絶縁膜としてTa
25薄膜6を形成する(図1(c))。つぎにそのTa
25薄膜6の表面に膜厚50〜300nmの範囲内の厚
さでPt膜よりなる第2の電極4を形成することによ
り、図1(d)に示す容量素子ができる。
A first electrode 2 made of a Pt film is formed on a supporting substrate 1 to a thickness in the range of 50 to 400 nm (FIG. 1).
(A)). Next, SrBi 2 Ta 2 O is formed on the first electrode 2.
The first insulating film 5 of 9 is formed by spin coating or CVD (C
It is formed to a thickness in the range of 50 to 250 nm using a chemical vapor deposition method or a sputtering method, and sintered at 800 ° C. in an oxygen atmosphere (FIG. 1B). Next, it is crystallized by sintering, and Ta is used as a second insulating film on the surface of the first insulating film 5 where irregularities are generated by crystal grains.
A 2 O 5 thin film 6 is formed (FIG. 1C). Next, the Ta
By forming the second electrode 4 made of a Pt film on the surface of the 2 O 5 thin film 6 with a thickness in the range of 50 to 300 nm, the capacitor shown in FIG.

【0014】このように上記実施の形態によれば、Sr
Bi2Ta29よりなる第1の絶縁膜5の表面に生じた
凹凸部の凹部にはTa25薄膜6が埋め込まれることに
よって平坦化され、第1の絶縁膜5と第2の絶縁膜であ
るTa25薄膜6とから構成される容量素子の容量絶縁
膜表面は平坦な面を形成することになる。
As described above, according to the above embodiment, Sr
The Ta 2 O 5 thin film 6 is buried in the concave portion of the uneven portion formed on the surface of the first insulating film 5 made of Bi 2 Ta 2 O 9 , whereby the first insulating film 5 and the second insulating film 5 are flattened. The surface of the capacitive insulating film of the capacitive element composed of the Ta 2 O 5 thin film 6 serving as the insulating film forms a flat surface.

【0015】また、本実施の形態では第2の絶縁膜とし
てTa25薄膜を用いたが、Bi23薄膜など他の絶縁
膜を用いても同様の効果を得ることは可能である。
In this embodiment, a Ta 2 O 5 thin film is used as the second insulating film, but the same effect can be obtained by using another insulating film such as a Bi 2 O 3 thin film. .

【0016】つぎに本発明の第2の実施の形態について
説明する。本実施の形態における容量素子の製造工程は
第1の実施の形態と同じであり、第1の実施の形態との
相違点は第2の絶縁膜として用いる絶縁材料が異なるこ
とである。
Next, a second embodiment of the present invention will be described. The manufacturing process of the capacitor in this embodiment is the same as that in the first embodiment, and is different from the first embodiment in that an insulating material used for the second insulating film is different.

【0017】第1の実施の形態の場合と同様に支持基板
1上に第1の電極膜2、第1の絶縁膜5を形成し、その
表面に回転塗布法により第2の絶縁膜として(Bax
1-x)TiO3薄膜7を形成させたのち、その表面に第
2の電極4を形成することにより、第2の実施の形態の
容量素子が形成される。
As in the case of the first embodiment, a first electrode film 2 and a first insulating film 5 are formed on a support substrate 1, and the surfaces thereof are formed as a second insulating film by spin coating. Ba x S
After the formation of the r 1-x ) TiO 3 thin film 7, the second electrode 4 is formed on the surface of the thin film 7, thereby forming the capacitive element according to the second embodiment.

【0018】このように上記実施の形態によれば、Sr
Bi2Ta29薄膜よりなる第1の絶縁膜5の表面に生
じた凹凸部の凹部にはSrBi2Ta29薄膜の結晶よ
りも結晶粒の小さな(BaxSr1-x)TiO3薄膜7が
埋め込まれることにより平坦化され、第1の絶縁膜5と
第2の絶縁膜である(BaxSr1-x)TiO3薄膜7と
から構成される容量素子の容量絶縁膜表面は平坦な面を
形成することになる。
As described above, according to the above embodiment, Sr
Bi 2 Ta 2 O 9 first in concave portions of the concavo-convex portion generated on the surface of the insulating film 5 having a small grain than SrBi 2 Ta 2 O 9 thin film of a crystal made of a thin film (Ba x Sr 1-x) TiO The surface of the capacitive insulating film of the capacitive element composed of the first insulating film 5 and the (Ba x Sr 1 -x ) TiO 3 thin film 7 as the second insulating film is planarized by embedding the three thin films 7. Will form a flat surface.

【0019】また、本実施の形態では第2の絶縁膜とし
て(BaxSr1-x)TiO3薄膜7を用いたが、SrB
2Ta29薄膜よりなる第1の絶縁膜5の結晶粒より
粒径が小さな他の絶縁体を用いても同様の効果を得るこ
とができる。
In this embodiment, the (Ba x Sr 1 -x ) TiO 3 thin film 7 is used as the second insulating film.
The same effect can be obtained by using another insulator having a smaller grain size than the crystal grains of the first insulating film 5 made of the i 2 Ta 2 O 9 thin film.

【0020】つぎに本発明の第3の実施の形態について
説明する。本実施の形態における容量素子の製造工程は
第1の実施の形態と同じであり、第1の実施の形態との
相違点は第2の絶縁膜として用いる絶縁材料は第1の実
施の形態と同じ材料であるが、その熱処理方法が異なる
ことである。
Next, a third embodiment of the present invention will be described. The manufacturing process of the capacitor in this embodiment is the same as that of the first embodiment. The difference from the first embodiment is that the insulating material used for the second insulating film is different from that of the first embodiment. The same material is used, but the heat treatment method is different.

【0021】第1、第2の実施の形態の場合と同様に支
持基板1上に第1の電極膜2、第1の絶縁膜5を形成
し、その表面に第2の絶縁膜としてSrBi2Ta29
薄膜8を回転塗布法あるいはCVD法、またはスパッタ
法を用いて膜厚20〜50nm形成し、600℃で熱処
理して形成させたのち、その表面に第2の電極4を形成
することにより、第3の実施の形態の容量素子が形成さ
れる。
As in the first and second embodiments, a first electrode film 2 and a first insulating film 5 are formed on a support substrate 1, and SrBi 2 as a second insulating film is formed on the surface thereof. Ta 2 O 9
The thin film 8 is formed to a thickness of 20 to 50 nm by spin coating, CVD, or sputtering, and is heat-treated at 600 ° C., and then the second electrode 4 is formed on the surface thereof. The capacitance element according to the third embodiment is formed.

【0022】このように上記実施の形態によれば、Sr
Bi2Ta29薄膜よりなる第1の絶縁膜5の表面に生
じた凹凸部の凹部には熱処理温度が低いことにより粒径
が第1の絶縁膜5より小さいSrBi2Ta29薄膜8
によって埋められているため、第1の絶縁膜5と第2の
絶縁膜であるSrBi2Ta29薄膜8とから構成され
る容量素子の容量絶縁膜表面は平坦な面を形成すること
になる。
As described above, according to the above embodiment, Sr
The SrBi 2 Ta 2 O 9 thin film having a grain size smaller than that of the first insulating film 5 due to the low heat treatment temperature in the concave portion of the uneven portion formed on the surface of the first insulating film 5 made of the Bi 2 Ta 2 O 9 thin film. 8
Therefore, the surface of the capacitive insulating film of the capacitive element composed of the first insulating film 5 and the SrBi 2 Ta 2 O 9 thin film 8 as the second insulating film has a flat surface. Become.

【0023】さらに本実施の形態の場合、第1の絶縁膜
5のSrBi2Ta29薄膜における焼結温度と第2の
絶縁膜であるSrBi2Ta29薄膜8の熱処理温度と
では異なっており、結晶化の程度は異なるが単一物質で
容量絶縁膜を構成できるため、第2の絶縁膜形成用の設
備を設ける必要がなくなり、コスト的に有利となる。ま
た成分的に同一物質であるため第1の絶縁膜と第2の絶
縁膜間の膜剥離(通常、熱ストレス等により発生するこ
とがある)を心配する必要がない等の利点がある。
Further, in the case of the present embodiment, the sintering temperature of the SrBi 2 Ta 2 O 9 thin film of the first insulating film 5 and the heat treatment temperature of the SrBi 2 Ta 2 O 9 thin film 8 of the second insulating film are different. Although different, and the degree of crystallization is different, the capacitance insulating film can be formed with a single substance, so that it is not necessary to provide facilities for forming the second insulating film, which is advantageous in cost. In addition, since the components are made of the same material, there is an advantage that there is no need to worry about peeling of the film between the first insulating film and the second insulating film (generally, this may occur due to thermal stress or the like).

【0024】なお、上記第1、第2、第3の実施の形態
では、第1の絶縁膜5として強誘電体のSrBi2Ta2
9薄膜を用いたが、他の誘電体薄膜を用いることも可
能である。特に第1の絶縁膜5としてBi4Ti312
SrBi2Ta29、あるいはSrBi2Nb29などの
ようなBiを含む強誘電体薄膜を用いる場合は、これら
の粒子径が他種の誘電体薄膜に比べて大きいため、本発
明による製造方法は容量素子の耐電圧向上に対して非常
に効果的である。また容量素子用の第1の電極および第
2の電極の電極用金属としてPt膜を用いたが、他の金
属またはRuO2のような導電性酸化物を用いても同様
の効果を得ることができる。
In the first, second, and third embodiments, the first insulating film 5 is made of ferroelectric SrBi 2 Ta 2.
Although an O 9 thin film was used, other dielectric thin films can be used. In particular, when a ferroelectric thin film containing Bi, such as Bi 4 Ti 3 O 12 , SrBi 2 Ta 2 O 9 , or SrBi 2 Nb 2 O 9, is used as the first insulating film 5, the particle diameter of these particles is small. Since it is larger than other types of dielectric thin films, the manufacturing method according to the present invention is very effective for improving the withstand voltage of the capacitor. Although the Pt film is used as the electrode metal of the first and second electrodes for the capacitor, the same effect can be obtained by using another metal or a conductive oxide such as RuO 2. it can.

【0025】[0025]

【発明の効果】本発明は、支持基板の一表面上に金属膜
あるいは導電性酸化物膜よりなる第1の電極を形成する
工程と、その第1の電極上に主成分が強誘電体または高
誘電率を有する誘電体からなる第1の絶縁膜を焼結して
形成する工程と、その第1の絶縁膜上に第2の絶縁膜を
焼結して形成する工程と、その第2の絶縁膜上に金属膜
あるいは導電性酸化物膜よりなる第2の電極を形成する
工程とを備えているために、結晶粒の凹凸による大きな
段差を有する誘電体薄膜の表面にもう一つの絶縁膜を積
層することにより、凹凸を生じる原因となる結晶を作ら
ない非晶質領域、または第1の絶縁膜を構成する誘電体
薄膜の結晶粒よりも小さな結晶粒からなる第2の絶縁膜
で覆うことで表面が平坦な容量絶縁膜を得ることがで
き、耐電圧の向上、さらには加工工程の簡略化を実現で
きるものである。
According to the present invention, there is provided a step of forming a first electrode made of a metal film or a conductive oxide film on one surface of a supporting substrate, and forming a ferroelectric substance or a main component on the first electrode. A step of sintering and forming a first insulating film made of a dielectric having a high dielectric constant, a step of sintering and forming a second insulating film on the first insulating film; Forming a second electrode made of a metal film or a conductive oxide film on the insulating film of (1), another insulating film is formed on the surface of the dielectric thin film having a large step due to unevenness of crystal grains. By laminating the films, an amorphous region where no crystal causing irregularities is formed or a second insulating film made of crystal grains smaller than the crystal grains of the dielectric thin film forming the first insulating film is formed. By covering, a capacitor insulating film with a flat surface can be obtained, The al those that can achieve simplification of the processing steps.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態における容量素子の製造方
法を示す工程断面図
FIG. 1 is a process cross-sectional view illustrating a method for manufacturing a capacitive element according to an embodiment of the present invention.

【図2】従来の容量素子の製造方法を示す工程断面図FIG. 2 is a process sectional view showing a conventional method for manufacturing a capacitive element.

【符号の説明】[Explanation of symbols]

1 支持基板 2 Pt膜(第1の電極膜) 4 Pt膜(第2の電極膜) 5 SrBi2Ta29薄膜(第1の絶縁膜) 6 Ta25薄膜(第2の絶縁膜) 7 (BaxSr1-x)TiO3薄膜(第2の絶縁膜) 8 非晶質SrBi2Ta29薄膜(第2の絶縁膜)Reference Signs List 1 support substrate 2 Pt film (first electrode film) 4 Pt film (second electrode film) 5 SrBi 2 Ta 2 O 9 thin film (first insulating film) 6 Ta 2 O 5 thin film (second insulating film) ) 7 (Ba x Sr 1- x) TiO 3 thin film (second insulating film) 8 amorphous SrBi 2 Ta 2 O 9 thin film (second insulating film)

───────────────────────────────────────────────────── フロントページの続き (72)発明者 有田 浩二 大阪府高槻市幸町1番1号 松下電子工業 株式会社内 (72)発明者 上本 康裕 大阪府高槻市幸町1番1号 松下電子工業 株式会社内 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Koji Arita, Inventor 1-1, Yukicho, Takatsuki-shi, Osaka Matsushita Electronics Corporation (72) Inventor Yasuhiro Uemoto 1-1, Yukicho, Takatsuki-shi, Osaka Matsushita Electronics Industrial Co., Ltd.

Claims (12)

【特許請求の範囲】[Claims] 【請求項1】 支持基板と、前記支持基板上に形成され
た第1の電極と、前記第1の電極上に形成され、強誘電
体または高誘電体で構成された第1の絶縁膜と、前記第
1の絶縁膜上に形成され、前記第1の絶縁膜と同一の材
料で構成された第2の絶縁膜と、前記第2の絶縁膜上に
形成された第2の電極とを有し、前記第2の絶縁膜を構
成する絶縁体の結晶粒の平均粒径が、前記第1の絶縁膜
を構成する絶縁体の結晶粒の平均粒径よりも小さいこと
を特徴とする容量素子。
1. A support substrate, a first electrode formed on the support substrate, and a first insulating film formed on the first electrode and made of a ferroelectric or high dielectric. A second insulating film formed on the first insulating film and made of the same material as the first insulating film; and a second electrode formed on the second insulating film. Wherein the average grain size of the crystal grains of the insulator forming the second insulating film is smaller than the average grain size of the crystal grains of the insulator forming the first insulating film. element.
【請求項2】 前記第1の絶縁膜が、粒径が100nm
を超える結晶粒を有することを特徴とする請求項1記載
の容量素子。
2. The method according to claim 1, wherein the first insulating film has a particle size of 100 nm.
The capacitive element according to claim 1, wherein the capacitive element has crystal grains exceeding the number of grains.
【請求項3】 支持基板と、前記支持基板上に形成され
た第1の電極と、前記第1の電極上に形成され、強誘電
体または高誘電体で構成された第1の絶縁膜と、前記第
1の絶縁膜上に形成され、前記第1の絶縁膜と同一の材
料で構成された第2の絶縁膜と、前記第2の絶縁膜上に
形成された第2の電極とを有し、前記第1の絶縁膜が、
粒径が100nmを超える結晶粒を含み、前記第2の絶
縁膜を構成する絶縁体の結晶粒の平均粒径が、前記第1
の絶縁膜を構成する絶縁体の結晶粒の平均粒径よりも小
さいことを特徴とする容量素子。
3. A support substrate, a first electrode formed on the support substrate, and a first insulating film formed on the first electrode and made of a ferroelectric or a high dielectric. A second insulating film formed on the first insulating film and made of the same material as the first insulating film; and a second electrode formed on the second insulating film. Having the first insulating film,
The second insulating film includes crystal grains having a grain diameter of more than 100 nm, and the average grain diameter of the crystal grains of the insulator constituting the second insulating film is the first grain diameter.
A capacitor element smaller than the average grain size of the crystal grains of the insulator constituting the insulating film.
【請求項4】 前記第1の絶縁膜の膜厚が50nmない
し250nmであることを特徴とする請求項1ないし請
求項3に記載の容量素子。
4. The capacitor according to claim 1, wherein the first insulating film has a thickness of 50 nm to 250 nm.
【請求項5】 前記第2の絶縁膜の膜厚が20nmない
し50nmであることを特徴とする請求項1ないし請求
項4に記載の容量素子。
5. The capacitor according to claim 1, wherein the second insulating film has a thickness of 20 nm to 50 nm.
【請求項6】 前記第2の絶縁膜が、非晶質領域を含む
ことを特徴とする請求項1ないし請求項5に記載の容量
素子。
6. The capacitor according to claim 1, wherein the second insulating film includes an amorphous region.
【請求項7】 支持基板上に第1の電極を形成する工程
と、前記第1の電極上に強誘電体または高誘電体を主成
分とする第1の絶縁膜を形成する工程と、前記第1の絶
縁膜を焼結する工程と、前記第1の絶縁膜上に強誘電体
または高誘電体を主成分とする第2の絶縁膜を形成する
工程と、前記第1の絶縁膜を焼結する温度よりも低い温
度で前記第2の絶縁膜を熱処理する工程と、前記第2の
絶縁膜上に第2の電極を形成する工程とを有することを
特徴とする容量素子の製造方法。
7. A step of forming a first electrode on a supporting substrate, a step of forming a first insulating film mainly composed of a ferroelectric or a high dielectric on the first electrode, A step of sintering the first insulating film, a step of forming a second insulating film mainly containing a ferroelectric or a high dielectric on the first insulating film, A method for heat-treating the second insulating film at a temperature lower than the sintering temperature; and a step of forming a second electrode on the second insulating film. .
【請求項8】 前記第1の絶縁膜の主成分と前記第2の
絶縁膜の主成分とが同じであることを特徴とする請求項
7記載の容量素子の製造方法。
8. The method according to claim 7, wherein a main component of the first insulating film is the same as a main component of the second insulating film.
【請求項9】 前記第1の絶縁膜の膜厚が50nmない
し250nmであることを特徴とする請求項7または請
求項8に記載の容量素子の製造方法。
9. The method according to claim 7, wherein the thickness of the first insulating film is 50 nm to 250 nm.
【請求項10】 前記第2の絶縁膜の膜厚が20nmな
いし50nmであることを特徴とする請求項7ないし請
求項9に記載の容量素子の製造方法。
10. The method according to claim 7, wherein the second insulating film has a thickness of 20 nm to 50 nm.
【請求項11】 前記第2の絶縁膜が、非晶質領域を含
むことを特徴とする請求項7ないし請求項10に記載の
容量素子の製造方法。
11. The method according to claim 7, wherein the second insulating film includes an amorphous region.
【請求項12】 第1の絶縁膜を構成する材料がビスマ
ス(Bi)を含む強誘電体を有することを特徴とする請
求項7ないし請求項11に記載の容量素子の製造方法。
12. The method according to claim 7, wherein the material forming the first insulating film includes a ferroelectric substance containing bismuth (Bi).
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Publication number Priority date Publication date Assignee Title
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